Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	584208	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3288511

1

T5

25

T6

8

T7

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	953581	1			T5	42		T6	16		T7	1
values[0x0]	1340847	1			T5	19		T6	3		T7	1
values[0x1]	1578291	1			T5	20		T6	9		T7	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	325448	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3547271

1

T5

33

T6

14

T7

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14266	1			T1	3		T122	1		T3	263
valid_sources[0x01]	14476	1			T25	1		T1	9		T2	2
valid_sources[0x02]	15277	1			T27	1		T1	1		T2	4
valid_sources[0x03]	14599	1			T1	3		T2	5		T22	10
valid_sources[0x04]	14490	1			T1	12		T42	1		T79	1
valid_sources[0x05]	15884	1			T1	13		T3	266		T76	1
valid_sources[0x06]	16640	1			T25	1		T1	15		T2	5
valid_sources[0x07]	15074	1			T1	10		T2	5		T3	304
valid_sources[0x08]	16008	1			T1	5		T2	5		T3	276
valid_sources[0x09]	14722	1			T25	1		T1	1		T17	1
valid_sources[0x0a]	15182	1			T25	1		T1	4		T2	1
valid_sources[0x0b]	14572	1			T1	5		T2	2		T42	1
valid_sources[0x0c]	17047	1			T1	8		T3	324		T73	2
valid_sources[0x0d]	14963	1			T27	3		T3	310		T76	1
valid_sources[0x0e]	15199	1			T1	1		T17	3		T2	5
valid_sources[0x0f]	15323	1			T1	3		T2	1		T42	1
valid_sources[0x10]	15115	1			T1	5		T17	1		T3	319
valid_sources[0x11]	14271	1			T1	7		T2	1		T79	1
valid_sources[0x12]	16557	1			T25	1		T1	7		T79	1
valid_sources[0x13]	15290	1			T1	17		T2	1		T42	1
valid_sources[0x14]	15132	1			T25	1		T1	13		T2	1
valid_sources[0x15]	14458	1			T25	1		T1	8		T2	2
valid_sources[0x16]	14700	1			T2	3		T3	294		T11	322
valid_sources[0x17]	14392	1			T1	6		T3	320		T31	1
valid_sources[0x18]	14249	1			T1	9		T42	1		T3	320
valid_sources[0x19]	15686	1			T25	1		T1	8		T3	254
valid_sources[0x1a]	14665	1			T1	2		T2	4		T3	328
valid_sources[0x1b]	14571	1			T1	2		T22	1		T79	1
valid_sources[0x1c]	15998	1			T27	1		T1	9		T2	5
valid_sources[0x1d]	14294	1			T1	5		T79	1		T3	264
valid_sources[0x1e]	16060	1			T1	8		T2	2		T42	1
valid_sources[0x1f]	14279	1			T1	39		T3	294		T11	324
valid_sources[0x20]	15283	1			T1	6		T3	241		T31	1
valid_sources[0x21]	15971	1			T5	3		T27	3		T1	23
valid_sources[0x22]	16042	1			T25	2		T1	6		T2	9
valid_sources[0x23]	15027	1			T1	12		T3	351		T31	2
valid_sources[0x24]	14434	1			T1	10		T2	8		T3	273
valid_sources[0x25]	16071	1			T1	1		T3	280		T31	1
valid_sources[0x26]	13908	1			T1	11		T3	330		T73	1
valid_sources[0x27]	15049	1			T1	14		T2	9		T3	295
valid_sources[0x28]	14855	1			T25	2		T1	3		T22	6
valid_sources[0x29]	13919	1			T25	1		T27	3		T1	15
valid_sources[0x2a]	15351	1			T1	12		T3	286		T76	1
valid_sources[0x2b]	15215	1			T1	3		T42	1		T3	225
valid_sources[0x2c]	15011	1			T1	15		T3	289		T73	1
valid_sources[0x2d]	14425	1			T1	16		T22	23		T79	1
valid_sources[0x2e]	17873	1			T25	2		T1	15		T2	2
valid_sources[0x2f]	15256	1			T25	1		T3	282		T77	1
valid_sources[0x30]	15909	1			T1	11		T3	335		T31	1
valid_sources[0x31]	14838	1			T1	9		T42	1		T3	272
valid_sources[0x32]	15424	1			T1	14		T42	2		T3	334
valid_sources[0x33]	14731	1			T27	4		T1	13		T79	2
valid_sources[0x34]	14393	1			T1	12		T17	1		T3	321
valid_sources[0x35]	15143	1			T42	1		T3	321		T73	1
valid_sources[0x36]	16365	1			T25	2		T27	1		T1	4
valid_sources[0x37]	15281	1			T1	19		T3	293		T31	1
valid_sources[0x38]	15588	1			T2	3		T3	334		T73	2
valid_sources[0x39]	14555	1			T5	5		T25	1		T1	10
valid_sources[0x3a]	15868	1			T1	17		T3	316		T74	6
valid_sources[0x3b]	14499	1			T5	10		T1	11		T42	1
valid_sources[0x3c]	13931	1			T25	2		T1	7		T42	1
valid_sources[0x3d]	14498	1			T1	9		T42	1		T3	267
valid_sources[0x3e]	16572	1			T25	2		T1	11		T42	1
valid_sources[0x3f]	15157	1			T1	1		T2	5		T3	308
valid_sources[0x40]	14707	1			T25	1		T1	6		T42	1
valid_sources[0x41]	15729	1			T1	9		T2	3		T79	1
valid_sources[0x42]	15213	1			T1	1		T17	1		T2	1
valid_sources[0x43]	13958	1			T1	14		T17	2		T3	284
valid_sources[0x44]	14156	1			T1	15		T22	2		T3	317
valid_sources[0x45]	16633	1			T5	29		T27	2		T1	2
valid_sources[0x46]	16050	1			T25	1		T1	12		T2	1
valid_sources[0x47]	15073	1			T1	1		T3	306		T74	9
valid_sources[0x48]	14655	1			T5	11		T1	11		T2	3
valid_sources[0x49]	15744	1			T1	8		T42	1		T3	248
valid_sources[0x4a]	15771	1			T1	16		T3	275		T34	1
valid_sources[0x4b]	15335	1			T25	1		T1	16		T2	4
valid_sources[0x4c]	14169	1			T1	3		T2	3		T3	237
valid_sources[0x4d]	14353	1			T25	1		T3	310		T11	207
valid_sources[0x4e]	13832	1			T5	1		T25	1		T1	13
valid_sources[0x4f]	14673	1			T25	2		T1	8		T2	1
valid_sources[0x50]	16232	1			T3	334		T11	536		T112	1
valid_sources[0x51]	14921	1			T25	1		T1	3		T3	306
valid_sources[0x52]	14920	1			T25	3		T1	6		T17	5
valid_sources[0x53]	14721	1			T1	3		T2	1		T42	2
valid_sources[0x54]	15137	1			T1	7		T2	1		T3	230
valid_sources[0x55]	16066	1			T24	1		T1	8		T3	352
valid_sources[0x56]	15206	1			T25	1		T1	4		T42	1
valid_sources[0x57]	14323	1			T25	3		T1	1		T2	1
valid_sources[0x58]	14603	1			T1	19		T22	20		T79	1
valid_sources[0x59]	15818	1			T1	14		T3	240		T74	1
valid_sources[0x5a]	15191	1			T24	3		T1	2		T2	1
valid_sources[0x5b]	15702	1			T1	26		T3	360		T73	1
valid_sources[0x5c]	16058	1			T1	7		T3	234		T74	4
valid_sources[0x5d]	13930	1			T1	10		T79	1		T3	240
valid_sources[0x5e]	14878	1			T25	1		T2	8		T3	317
valid_sources[0x5f]	15194	1			T27	1		T1	5		T22	1
valid_sources[0x60]	14686	1			T5	1		T25	1		T1	7
valid_sources[0x61]	15476	1			T1	2		T22	13		T3	279
valid_sources[0x62]	15249	1			T24	8		T1	12		T42	1
valid_sources[0x63]	14260	1			T22	4		T3	300		T31	2
valid_sources[0x64]	14190	1			T25	2		T1	5		T2	2
valid_sources[0x65]	15026	1			T1	21		T79	2		T3	307
valid_sources[0x66]	15563	1			T1	1		T3	268		T74	7
valid_sources[0x67]	15062	1			T1	10		T122	1		T3	267
valid_sources[0x68]	14157	1			T25	1		T27	4		T1	5
valid_sources[0x69]	14156	1			T1	2		T42	1		T3	326
valid_sources[0x6a]	15714	1			T1	2		T79	1		T3	262
valid_sources[0x6b]	14302	1			T1	4		T2	6		T3	298
valid_sources[0x6c]	15671	1			T25	1		T27	1		T3	252
valid_sources[0x6d]	15313	1			T1	2		T42	1		T3	258
valid_sources[0x6e]	15986	1			T25	2		T1	12		T3	291
valid_sources[0x6f]	14905	1			T2	10		T3	315		T73	1
valid_sources[0x70]	14883	1			T22	18		T42	1		T3	298
valid_sources[0x71]	15598	1			T1	8		T3	268		T31	2
valid_sources[0x72]	15201	1			T79	1		T3	284		T31	4
valid_sources[0x73]	15912	1			T25	3		T1	19		T18	58
valid_sources[0x74]	16677	1			T25	2		T1	7		T17	1
valid_sources[0x75]	14465	1			T5	1		T1	1		T3	356
valid_sources[0x76]	14630	1			T27	2		T1	1		T2	6
valid_sources[0x77]	15941	1			T1	4		T3	307		T76	1
valid_sources[0x78]	15422	1			T2	2		T122	1		T3	272
valid_sources[0x79]	16190	1			T1	6		T2	2		T3	317
valid_sources[0x7a]	15577	1			T1	6		T2	1		T3	266
valid_sources[0x7b]	14456	1			T42	1		T122	1		T3	253
valid_sources[0x7c]	15591	1			T1	15		T42	1		T3	334
valid_sources[0x7d]	14694	1			T25	1		T1	3		T3	326
valid_sources[0x7e]	15850	1			T1	15		T2	5		T42	2
valid_sources[0x7f]	16068	1			T27	2		T1	12		T3	264
valid_sources[0x80]	15153	1			T2	1		T42	1		T79	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

830222

1

T5

19

T6

7

T7

1

values[0x0]

all_enables

biggest_size

1250096

1

T5

4

T7

1

T24

2

values[0x1]

all_enables

biggest_size

1208193

1

T5

2

T6

1

T24

1