Summary for Variable csr_enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for csr_enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
333164 |
1 |
|
|
T5 |
7 |
|
T6 |
2 |
|
T7 |
2 |
auto[1] |
230153481 |
1 |
|
|
T5 |
849 |
|
T6 |
2705 |
|
T7 |
716 |
Summary for Variable ip_clk_en_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for ip_clk_en_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8823 |
1 |
|
|
T5 |
2 |
|
T6 |
2 |
|
T7 |
2 |
auto[1] |
230477822 |
1 |
|
|
T5 |
854 |
|
T6 |
2705 |
|
T7 |
716 |
Summary for Variable scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for scanmode_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
146425980 |
1 |
|
|
T5 |
850 |
|
T6 |
1993 |
|
T7 |
718 |
auto[1] |
84060665 |
1 |
|
|
T5 |
6 |
|
T6 |
714 |
|
T24 |
73 |
Summary for Cross peri_cross
Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for peri_cross
Bins
csr_enable_cp | ip_clk_en_cp | scanmode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
5472 |
1 |
|
|
T6 |
2 |
|
T7 |
2 |
|
T24 |
2 |
auto[0] |
auto[0] |
auto[1] |
1524 |
1 |
|
|
T5 |
2 |
|
T25 |
2 |
|
T27 |
2 |
auto[0] |
auto[1] |
auto[0] |
247730 |
1 |
|
|
T5 |
5 |
|
T26 |
25 |
|
T1 |
27 |
auto[0] |
auto[1] |
auto[1] |
78438 |
1 |
|
|
T26 |
10 |
|
T1 |
52 |
|
T3 |
235 |
auto[1] |
auto[1] |
auto[0] |
146170951 |
1 |
|
|
T5 |
845 |
|
T6 |
1991 |
|
T7 |
716 |
auto[1] |
auto[1] |
auto[1] |
83980703 |
1 |
|
|
T5 |
4 |
|
T6 |
714 |
|
T24 |
73 |
User Defined Cross Bins for peri_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
ignore_enable_off |
0 |
Excluded |
Summary for Variable csr_enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for csr_enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
155866 |
1 |
|
|
T5 |
4 |
|
T6 |
2 |
|
T7 |
2 |
auto[1] |
115085742 |
1 |
|
|
T5 |
424 |
|
T6 |
1352 |
|
T7 |
357 |
Summary for Variable ip_clk_en_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for ip_clk_en_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7920 |
1 |
|
|
T5 |
2 |
|
T6 |
2 |
|
T7 |
2 |
auto[1] |
115233688 |
1 |
|
|
T5 |
426 |
|
T6 |
1352 |
|
T7 |
357 |
Summary for Variable scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for scanmode_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
73211253 |
1 |
|
|
T5 |
425 |
|
T6 |
997 |
|
T7 |
359 |
auto[1] |
42030355 |
1 |
|
|
T5 |
3 |
|
T6 |
357 |
|
T24 |
37 |
Summary for Cross peri_cross
Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for peri_cross
Bins
csr_enable_cp | ip_clk_en_cp | scanmode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
5472 |
1 |
|
|
T6 |
2 |
|
T7 |
2 |
|
T24 |
2 |
auto[0] |
auto[0] |
auto[1] |
1524 |
1 |
|
|
T5 |
2 |
|
T25 |
2 |
|
T27 |
2 |
auto[0] |
auto[1] |
auto[0] |
113125 |
1 |
|
|
T5 |
2 |
|
T26 |
11 |
|
T1 |
15 |
auto[0] |
auto[1] |
auto[1] |
35745 |
1 |
|
|
T26 |
5 |
|
T1 |
24 |
|
T3 |
139 |
auto[1] |
auto[1] |
auto[0] |
73091732 |
1 |
|
|
T5 |
423 |
|
T6 |
995 |
|
T7 |
357 |
auto[1] |
auto[1] |
auto[1] |
41993086 |
1 |
|
|
T5 |
1 |
|
T6 |
357 |
|
T24 |
37 |
User Defined Cross Bins for peri_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
ignore_enable_off |
0 |
Excluded |
Summary for Variable csr_enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for csr_enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
607840 |
1 |
|
|
T5 |
11 |
|
T6 |
2 |
|
T7 |
2 |
auto[1] |
459794409 |
1 |
|
|
T5 |
1701 |
|
T6 |
5413 |
|
T7 |
1401 |
Summary for Variable ip_clk_en_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for ip_clk_en_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10640 |
1 |
|
|
T5 |
2 |
|
T6 |
2 |
|
T7 |
2 |
auto[1] |
460391609 |
1 |
|
|
T5 |
1710 |
|
T6 |
5413 |
|
T7 |
1401 |
Summary for Variable scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for scanmode_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
292280949 |
1 |
|
|
T5 |
1700 |
|
T6 |
3987 |
|
T7 |
1403 |
auto[1] |
168121300 |
1 |
|
|
T5 |
12 |
|
T6 |
1428 |
|
T24 |
147 |
Summary for Cross peri_cross
Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for peri_cross
Bins
csr_enable_cp | ip_clk_en_cp | scanmode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
5472 |
1 |
|
|
T6 |
2 |
|
T7 |
2 |
|
T24 |
2 |
auto[0] |
auto[0] |
auto[1] |
1524 |
1 |
|
|
T5 |
2 |
|
T25 |
2 |
|
T27 |
2 |
auto[0] |
auto[1] |
auto[0] |
460619 |
1 |
|
|
T5 |
9 |
|
T26 |
54 |
|
T1 |
67 |
auto[0] |
auto[1] |
auto[1] |
140225 |
1 |
|
|
T26 |
17 |
|
T1 |
88 |
|
T3 |
504 |
auto[1] |
auto[1] |
auto[0] |
291811214 |
1 |
|
|
T5 |
1691 |
|
T6 |
3985 |
|
T7 |
1401 |
auto[1] |
auto[1] |
auto[1] |
167979551 |
1 |
|
|
T5 |
10 |
|
T6 |
1428 |
|
T24 |
147 |
User Defined Cross Bins for peri_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
ignore_enable_off |
0 |
Excluded |
Summary for Variable csr_enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for csr_enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
313755 |
1 |
|
|
T5 |
6 |
|
T6 |
2 |
|
T7 |
2 |
auto[1] |
235160341 |
1 |
|
|
T5 |
850 |
|
T6 |
2706 |
|
T7 |
700 |
Summary for Variable ip_clk_en_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for ip_clk_en_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8450 |
1 |
|
|
T5 |
2 |
|
T6 |
2 |
|
T7 |
2 |
auto[1] |
235465646 |
1 |
|
|
T5 |
854 |
|
T6 |
2706 |
|
T7 |
700 |
Summary for Variable scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for scanmode_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
149156849 |
1 |
|
|
T5 |
850 |
|
T6 |
1994 |
|
T7 |
702 |
auto[1] |
86317247 |
1 |
|
|
T5 |
6 |
|
T6 |
714 |
|
T24 |
74 |
Summary for Cross peri_cross
Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for peri_cross
Bins
csr_enable_cp | ip_clk_en_cp | scanmode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
5456 |
1 |
|
|
T6 |
2 |
|
T7 |
2 |
|
T24 |
2 |
auto[0] |
auto[0] |
auto[1] |
1540 |
1 |
|
|
T5 |
2 |
|
T25 |
2 |
|
T27 |
2 |
auto[0] |
auto[1] |
auto[0] |
230119 |
1 |
|
|
T5 |
4 |
|
T26 |
31 |
|
T1 |
33 |
auto[0] |
auto[1] |
auto[1] |
76640 |
1 |
|
|
T26 |
4 |
|
T1 |
46 |
|
T3 |
289 |
auto[1] |
auto[1] |
auto[0] |
148919820 |
1 |
|
|
T5 |
846 |
|
T6 |
1992 |
|
T7 |
700 |
auto[1] |
auto[1] |
auto[1] |
86239067 |
1 |
|
|
T5 |
4 |
|
T6 |
714 |
|
T24 |
74 |
User Defined Cross Bins for peri_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
ignore_enable_off |
0 |
Excluded |