Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T26,T1
0	1	Covered	T26,T1,T3
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T26,T1
1	0	Covered	T23,T39,T40
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1044280492	14326	0	0
GateOpen_A	1044280492	21024	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044280492	14326	0	0
T1	1688401	32	0	0
T2	407637	0	0	0
T3	0	114	0	0
T5	4251	4	0	0
T6	12493	0	0	0
T7	3552	0	0	0
T17	23821	0	0	0
T23	0	5	0	0
T24	4746	0	0	0
T25	14426	0	0	0
T26	3210	18	0	0
T27	24468	0	0	0
T32	0	72	0	0
T39	0	8	0	0
T40	0	4	0	0
T42	0	4	0	0
T73	0	3	0	0
T77	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044280492	21024	0	0
T1	1688401	44	0	0
T2	407637	0	0	0
T4	0	4	0	0
T5	4251	4	0	0
T6	12493	4	0	0
T7	3552	4	0	0
T17	23821	0	0	0
T19	0	4	0	0
T20	0	4	0	0
T23	0	9	0	0
T24	4746	4	0	0
T25	14426	0	0	0
T26	3210	22	0	0
T27	24468	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T26,T1
0	1	Covered	T26,T1,T3
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T26,T1
1	0	Covered	T23,T39,T40
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	115176885	3419	0	0
GateOpen_A	115176885	5092	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115176885	3419	0	0
T1	185306	7	0	0
T2	45275	0	0	0
T3	0	26	0	0
T5	453	1	0	0
T6	1375	0	0	0
T7	394	0	0	0
T17	2913	0	0	0
T23	0	1	0	0
T24	543	0	0	0
T25	1588	0	0	0
T26	348	5	0	0
T27	2942	0	0	0
T32	0	16	0	0
T39	0	2	0	0
T40	0	4	0	0
T42	0	1	0	0
T77	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115176885	5092	0	0
T1	185306	10	0	0
T2	45275	0	0	0
T4	0	1	0	0
T5	453	1	0	0
T6	1375	1	0	0
T7	394	1	0	0
T17	2913	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T23	0	2	0	0
T24	543	1	0	0
T25	1588	0	0	0
T26	348	6	0	0
T27	2942	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T26,T1
0	1	Covered	T26,T1,T3
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T26,T1
1	0	Covered	T23,T39,T40
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	230354616	3644	0	0
GateOpen_A	230354616	5317	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230354616	3644	0	0
T1	370613	9	0	0
T2	90550	0	0	0
T3	0	30	0	0
T5	905	1	0	0
T6	2750	0	0	0
T7	788	0	0	0
T17	5829	0	0	0
T23	0	1	0	0
T24	1086	0	0	0
T25	3175	0	0	0
T26	696	4	0	0
T27	5887	0	0	0
T32	0	20	0	0
T39	0	2	0	0
T42	0	1	0	0
T73	0	1	0	0
T77	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230354616	5317	0	0
T1	370613	12	0	0
T2	90550	0	0	0
T4	0	1	0	0
T5	905	1	0	0
T6	2750	1	0	0
T7	788	1	0	0
T17	5829	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T23	0	2	0	0
T24	1086	1	0	0
T25	3175	0	0	0
T26	696	5	0	0
T27	5887	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T26,T1
0	1	Covered	T26,T1,T3
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T26,T1
1	0	Covered	T23,T39,T40
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	462284794	3637	0	0
GateOpen_A	462284794	5312	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462284794	3637	0	0
T1	741536	9	0	0
T2	181205	0	0	0
T3	0	30	0	0
T5	1929	1	0	0
T6	5578	0	0	0
T7	1580	0	0	0
T17	10052	0	0	0
T23	0	1	0	0
T24	2078	0	0	0
T25	6442	0	0	0
T26	1444	4	0	0
T27	10426	0	0	0
T32	0	17	0	0
T39	0	2	0	0
T42	0	1	0	0
T73	0	1	0	0
T77	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462284794	5312	0	0
T1	741536	12	0	0
T2	181205	0	0	0
T4	0	1	0	0
T5	1929	1	0	0
T6	5578	1	0	0
T7	1580	1	0	0
T17	10052	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T23	0	2	0	0
T24	2078	1	0	0
T25	6442	0	0	0
T26	1444	5	0	0
T27	10426	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T26,T1
0	1	Covered	T26,T1,T3
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T26,T1
1	0	Covered	T23,T39,T40
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	236464197	3626	0	0
GateOpen_A	236464197	5303	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236464197	3626	0	0
T1	390946	7	0	0
T2	90607	0	0	0
T3	0	28	0	0
T5	964	1	0	0
T6	2790	0	0	0
T7	790	0	0	0
T17	5027	0	0	0
T23	0	2	0	0
T24	1039	0	0	0
T25	3221	0	0	0
T26	722	5	0	0
T27	5213	0	0	0
T32	0	19	0	0
T39	0	2	0	0
T42	0	1	0	0
T73	0	1	0	0
T77	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236464197	5303	0	0
T1	390946	10	0	0
T2	90607	0	0	0
T4	0	1	0	0
T5	964	1	0	0
T6	2790	1	0	0
T7	790	1	0	0
T17	5027	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T23	0	3	0	0
T24	1039	1	0	0
T25	3221	0	0	0
T26	722	6	0	0
T27	5213	0	0	0