Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	733835855	67605	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733835855	67605	0	0
T1	3705785	881	0	0
T2	471900	144	0	0
T3	0	1158	0	0
T4	187070	0	0	0
T10	0	73	0	0
T11	0	329	0	0
T12	0	829	0	0
T13	0	600	0	0
T14	0	156	0	0
T15	0	457	0	0
T16	0	397	0	0
T17	7850	0	0	0
T18	13110	0	0	0
T19	9350	0	0	0
T20	4145	0	0	0
T21	11590	0	0	0
T22	481080	0	0	0
T23	6125	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	146767171	10078	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146767171	10078	0	0
T1	741157	118	0	0
T2	94380	22	0	0
T3	0	149	0	0
T4	37414	0	0	0
T10	0	11	0	0
T11	0	49	0	0
T12	0	108	0	0
T13	0	78	0	0
T14	0	26	0	0
T15	0	60	0	0
T16	0	53	0	0
T17	1570	0	0	0
T18	2622	0	0	0
T19	1870	0	0	0
T20	829	0	0	0
T21	2318	0	0	0
T22	96216	0	0	0
T23	1225	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	146767171	9858	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146767171	9858	0	0
T1	741157	117	0	0
T2	94380	20	0	0
T3	0	167	0	0
T4	37414	0	0	0
T10	0	10	0	0
T11	0	48	0	0
T12	0	121	0	0
T13	0	76	0	0
T14	0	26	0	0
T15	0	59	0	0
T16	0	52	0	0
T17	1570	0	0	0
T18	2622	0	0	0
T19	1870	0	0	0
T20	829	0	0	0
T21	2318	0	0	0
T22	96216	0	0	0
T23	1225	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	146767171	13576	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146767171	13576	0	0
T1	741157	177	0	0
T2	94380	28	0	0
T3	0	229	0	0
T4	37414	0	0	0
T10	0	15	0	0
T11	0	67	0	0
T12	0	164	0	0
T13	0	123	0	0
T14	0	32	0	0
T15	0	96	0	0
T16	0	80	0	0
T17	1570	0	0	0
T18	2622	0	0	0
T19	1870	0	0	0
T20	829	0	0	0
T21	2318	0	0	0
T22	96216	0	0	0
T23	1225	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	146767171	13567	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146767171	13567	0	0
T1	741157	179	0	0
T2	94380	29	0	0
T3	0	228	0	0
T4	37414	0	0	0
T10	0	15	0	0
T11	0	65	0	0
T12	0	166	0	0
T13	0	122	0	0
T14	0	32	0	0
T15	0	93	0	0
T16	0	80	0	0
T17	1570	0	0	0
T18	2622	0	0	0
T19	1870	0	0	0
T20	829	0	0	0
T21	2318	0	0	0
T22	96216	0	0	0
T23	1225	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	146767171	20526	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146767171	20526	0	0
T1	741157	290	0	0
T2	94380	45	0	0
T3	0	385	0	0
T4	37414	0	0	0
T10	0	22	0	0
T11	0	100	0	0
T12	0	270	0	0
T13	0	201	0	0
T14	0	40	0	0
T15	0	149	0	0
T16	0	132	0	0
T17	1570	0	0	0
T18	2622	0	0	0
T19	1870	0	0	0
T20	829	0	0	0
T21	2318	0	0	0
T22	96216	0	0	0
T23	1225	0	0	0