Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Module :
prim_mubi4_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Module :
prim_mubi4_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Module :
prim_mubi4_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22540 |
22540 |
0 |
0 |
T1 |
28 |
28 |
0 |
0 |
T2 |
28 |
28 |
0 |
0 |
T5 |
28 |
28 |
0 |
0 |
T6 |
28 |
28 |
0 |
0 |
T7 |
28 |
28 |
0 |
0 |
T17 |
28 |
28 |
0 |
0 |
T24 |
28 |
28 |
0 |
0 |
T25 |
28 |
28 |
0 |
0 |
T26 |
28 |
28 |
0 |
0 |
T27 |
28 |
28 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
20082247 |
20065739 |
0 |
0 |
T2 |
3609019 |
3605140 |
0 |
0 |
T5 |
52362 |
46866 |
0 |
0 |
T6 |
89875 |
87591 |
0 |
0 |
T7 |
42038 |
37836 |
0 |
0 |
T17 |
150090 |
147385 |
0 |
0 |
T24 |
56594 |
50846 |
0 |
0 |
T25 |
121632 |
117801 |
0 |
0 |
T26 |
38389 |
34780 |
0 |
0 |
T27 |
159986 |
159137 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
880603026 |
865197402 |
0 |
14490 |
T1 |
4446942 |
4442886 |
0 |
18 |
T2 |
566280 |
565584 |
0 |
18 |
T5 |
12048 |
10674 |
0 |
18 |
T6 |
8364 |
8100 |
0 |
18 |
T7 |
9474 |
8400 |
0 |
18 |
T17 |
9420 |
9198 |
0 |
18 |
T24 |
12984 |
11526 |
0 |
18 |
T25 |
17304 |
16668 |
0 |
18 |
T26 |
8658 |
7746 |
0 |
18 |
T27 |
11724 |
11634 |
0 |
18 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
16905 |
T1 |
5457678 |
5452645 |
0 |
21 |
T2 |
1125013 |
1123645 |
0 |
21 |
T5 |
13977 |
12383 |
0 |
21 |
T6 |
31606 |
30668 |
0 |
21 |
T7 |
11317 |
10036 |
0 |
21 |
T17 |
55076 |
53866 |
0 |
21 |
T24 |
15062 |
13370 |
0 |
21 |
T25 |
39050 |
37632 |
0 |
21 |
T26 |
10345 |
9257 |
0 |
21 |
T27 |
57773 |
57386 |
0 |
21 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
188341 |
0 |
0 |
T1 |
5457678 |
372 |
0 |
0 |
T2 |
1125013 |
4 |
0 |
0 |
T3 |
0 |
294 |
0 |
0 |
T5 |
8032 |
16 |
0 |
0 |
T6 |
23240 |
60 |
0 |
0 |
T7 |
11317 |
19 |
0 |
0 |
T17 |
55076 |
184 |
0 |
0 |
T18 |
7866 |
150 |
0 |
0 |
T19 |
5535 |
79 |
0 |
0 |
T20 |
0 |
23 |
0 |
0 |
T24 |
15062 |
120 |
0 |
0 |
T25 |
39050 |
214 |
0 |
0 |
T26 |
10345 |
32 |
0 |
0 |
T27 |
57773 |
225 |
0 |
0 |
T76 |
0 |
89 |
0 |
0 |
T122 |
0 |
25 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
10177627 |
10169981 |
0 |
0 |
T2 |
1917726 |
1915872 |
0 |
0 |
T5 |
26337 |
23770 |
0 |
0 |
T6 |
49905 |
48784 |
0 |
0 |
T7 |
21247 |
19361 |
0 |
0 |
T17 |
85594 |
84282 |
0 |
0 |
T24 |
28548 |
25911 |
0 |
0 |
T25 |
65278 |
63462 |
0 |
0 |
T26 |
19386 |
17738 |
0 |
0 |
T27 |
90489 |
90078 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T7,T24,T27 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T7,T24,T27 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T7,T24,T27 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T7,T24,T27 |
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T24,T27 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T24,T27 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T24,T27 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T24,T27 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462284330 |
457953853 |
0 |
0 |
T1 |
741536 |
740838 |
0 |
0 |
T2 |
181205 |
180988 |
0 |
0 |
T5 |
1929 |
1712 |
0 |
0 |
T6 |
5578 |
5415 |
0 |
0 |
T7 |
1579 |
1403 |
0 |
0 |
T17 |
10052 |
9835 |
0 |
0 |
T24 |
2078 |
1847 |
0 |
0 |
T25 |
6442 |
6211 |
0 |
0 |
T26 |
1443 |
1294 |
0 |
0 |
T27 |
10425 |
10359 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462284330 |
457946842 |
0 |
2415 |
T1 |
741536 |
740823 |
0 |
3 |
T2 |
181205 |
180985 |
0 |
3 |
T5 |
1929 |
1709 |
0 |
3 |
T6 |
5578 |
5412 |
0 |
3 |
T7 |
1579 |
1400 |
0 |
3 |
T17 |
10052 |
9832 |
0 |
3 |
T24 |
2078 |
1844 |
0 |
3 |
T25 |
6442 |
6208 |
0 |
3 |
T26 |
1443 |
1291 |
0 |
3 |
T27 |
10425 |
10356 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462284330 |
26101 |
0 |
0 |
T1 |
741536 |
0 |
0 |
0 |
T2 |
181205 |
0 |
0 |
0 |
T3 |
0 |
118 |
0 |
0 |
T7 |
1579 |
5 |
0 |
0 |
T17 |
10052 |
71 |
0 |
0 |
T18 |
2622 |
76 |
0 |
0 |
T19 |
1795 |
38 |
0 |
0 |
T20 |
0 |
15 |
0 |
0 |
T24 |
2078 |
37 |
0 |
0 |
T25 |
6442 |
0 |
0 |
0 |
T26 |
1443 |
0 |
0 |
0 |
T27 |
10425 |
87 |
0 |
0 |
T76 |
0 |
38 |
0 |
0 |
T122 |
0 |
11 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146767171 |
144206730 |
0 |
0 |
T1 |
741157 |
740500 |
0 |
0 |
T2 |
94380 |
94267 |
0 |
0 |
T5 |
2008 |
1782 |
0 |
0 |
T6 |
1394 |
1353 |
0 |
0 |
T7 |
1579 |
1403 |
0 |
0 |
T17 |
1570 |
1536 |
0 |
0 |
T24 |
2164 |
1924 |
0 |
0 |
T25 |
2884 |
2781 |
0 |
0 |
T26 |
1443 |
1294 |
0 |
0 |
T27 |
1954 |
1942 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146767171 |
144206730 |
0 |
0 |
T1 |
741157 |
740500 |
0 |
0 |
T2 |
94380 |
94267 |
0 |
0 |
T5 |
2008 |
1782 |
0 |
0 |
T6 |
1394 |
1353 |
0 |
0 |
T7 |
1579 |
1403 |
0 |
0 |
T17 |
1570 |
1536 |
0 |
0 |
T24 |
2164 |
1924 |
0 |
0 |
T25 |
2884 |
2781 |
0 |
0 |
T26 |
1443 |
1294 |
0 |
0 |
T27 |
1954 |
1942 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146767171 |
144206730 |
0 |
0 |
T1 |
741157 |
740500 |
0 |
0 |
T2 |
94380 |
94267 |
0 |
0 |
T5 |
2008 |
1782 |
0 |
0 |
T6 |
1394 |
1353 |
0 |
0 |
T7 |
1579 |
1403 |
0 |
0 |
T17 |
1570 |
1536 |
0 |
0 |
T24 |
2164 |
1924 |
0 |
0 |
T25 |
2884 |
2781 |
0 |
0 |
T26 |
1443 |
1294 |
0 |
0 |
T27 |
1954 |
1942 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146767171 |
144206730 |
0 |
0 |
T1 |
741157 |
740500 |
0 |
0 |
T2 |
94380 |
94267 |
0 |
0 |
T5 |
2008 |
1782 |
0 |
0 |
T6 |
1394 |
1353 |
0 |
0 |
T7 |
1579 |
1403 |
0 |
0 |
T17 |
1570 |
1536 |
0 |
0 |
T24 |
2164 |
1924 |
0 |
0 |
T25 |
2884 |
2781 |
0 |
0 |
T26 |
1443 |
1294 |
0 |
0 |
T27 |
1954 |
1942 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T7,T24,T27 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T7,T24,T27 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T7,T24,T27 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T7,T24,T27 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T24,T27 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T24,T27 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T24,T27 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T24,T27 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146767171 |
144206730 |
0 |
0 |
T1 |
741157 |
740500 |
0 |
0 |
T2 |
94380 |
94267 |
0 |
0 |
T5 |
2008 |
1782 |
0 |
0 |
T6 |
1394 |
1353 |
0 |
0 |
T7 |
1579 |
1403 |
0 |
0 |
T17 |
1570 |
1536 |
0 |
0 |
T24 |
2164 |
1924 |
0 |
0 |
T25 |
2884 |
2781 |
0 |
0 |
T26 |
1443 |
1294 |
0 |
0 |
T27 |
1954 |
1942 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146767171 |
144199567 |
0 |
2415 |
T1 |
741157 |
740481 |
0 |
3 |
T2 |
94380 |
94264 |
0 |
3 |
T5 |
2008 |
1779 |
0 |
3 |
T6 |
1394 |
1350 |
0 |
3 |
T7 |
1579 |
1400 |
0 |
3 |
T17 |
1570 |
1533 |
0 |
3 |
T24 |
2164 |
1921 |
0 |
3 |
T25 |
2884 |
2778 |
0 |
3 |
T26 |
1443 |
1291 |
0 |
3 |
T27 |
1954 |
1939 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146767171 |
16007 |
0 |
0 |
T1 |
741157 |
0 |
0 |
0 |
T2 |
94380 |
0 |
0 |
0 |
T3 |
0 |
89 |
0 |
0 |
T7 |
1579 |
4 |
0 |
0 |
T17 |
1570 |
29 |
0 |
0 |
T18 |
2622 |
49 |
0 |
0 |
T19 |
1870 |
25 |
0 |
0 |
T20 |
0 |
4 |
0 |
0 |
T24 |
2164 |
22 |
0 |
0 |
T25 |
2884 |
0 |
0 |
0 |
T26 |
1443 |
0 |
0 |
0 |
T27 |
1954 |
40 |
0 |
0 |
T76 |
0 |
25 |
0 |
0 |
T122 |
0 |
5 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T7,T24,T27 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T7,T24,T27 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T7,T24,T27 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T7,T24,T27 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T24,T27 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T24,T27 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T24,T27 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T24,T27 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146767171 |
144206730 |
0 |
0 |
T1 |
741157 |
740500 |
0 |
0 |
T2 |
94380 |
94267 |
0 |
0 |
T5 |
2008 |
1782 |
0 |
0 |
T6 |
1394 |
1353 |
0 |
0 |
T7 |
1579 |
1403 |
0 |
0 |
T17 |
1570 |
1536 |
0 |
0 |
T24 |
2164 |
1924 |
0 |
0 |
T25 |
2884 |
2781 |
0 |
0 |
T26 |
1443 |
1294 |
0 |
0 |
T27 |
1954 |
1942 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146767171 |
144199567 |
0 |
2415 |
T1 |
741157 |
740481 |
0 |
3 |
T2 |
94380 |
94264 |
0 |
3 |
T5 |
2008 |
1779 |
0 |
3 |
T6 |
1394 |
1350 |
0 |
3 |
T7 |
1579 |
1400 |
0 |
3 |
T17 |
1570 |
1533 |
0 |
3 |
T24 |
2164 |
1921 |
0 |
3 |
T25 |
2884 |
2778 |
0 |
3 |
T26 |
1443 |
1291 |
0 |
3 |
T27 |
1954 |
1939 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146767171 |
18428 |
0 |
0 |
T1 |
741157 |
0 |
0 |
0 |
T2 |
94380 |
0 |
0 |
0 |
T3 |
0 |
87 |
0 |
0 |
T7 |
1579 |
2 |
0 |
0 |
T17 |
1570 |
34 |
0 |
0 |
T18 |
2622 |
25 |
0 |
0 |
T19 |
1870 |
16 |
0 |
0 |
T20 |
0 |
4 |
0 |
0 |
T24 |
2164 |
21 |
0 |
0 |
T25 |
2884 |
0 |
0 |
0 |
T26 |
1443 |
0 |
0 |
0 |
T27 |
1954 |
38 |
0 |
0 |
T76 |
0 |
26 |
0 |
0 |
T122 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492655958 |
490389093 |
0 |
0 |
T1 |
808457 |
808130 |
0 |
0 |
T2 |
188762 |
188650 |
0 |
0 |
T5 |
2008 |
1882 |
0 |
0 |
T6 |
5810 |
5727 |
0 |
0 |
T7 |
1645 |
1605 |
0 |
0 |
T17 |
10471 |
10387 |
0 |
0 |
T24 |
2164 |
2067 |
0 |
0 |
T25 |
6710 |
6613 |
0 |
0 |
T26 |
1504 |
1449 |
0 |
0 |
T27 |
10860 |
10834 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492655958 |
490389093 |
0 |
0 |
T1 |
808457 |
808130 |
0 |
0 |
T2 |
188762 |
188650 |
0 |
0 |
T5 |
2008 |
1882 |
0 |
0 |
T6 |
5810 |
5727 |
0 |
0 |
T7 |
1645 |
1605 |
0 |
0 |
T17 |
10471 |
10387 |
0 |
0 |
T24 |
2164 |
2067 |
0 |
0 |
T25 |
6710 |
6613 |
0 |
0 |
T26 |
1504 |
1449 |
0 |
0 |
T27 |
10860 |
10834 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462284330 |
460141252 |
0 |
0 |
T1 |
741536 |
741223 |
0 |
0 |
T2 |
181205 |
181098 |
0 |
0 |
T5 |
1929 |
1808 |
0 |
0 |
T6 |
5578 |
5498 |
0 |
0 |
T7 |
1579 |
1540 |
0 |
0 |
T17 |
10052 |
9972 |
0 |
0 |
T24 |
2078 |
1984 |
0 |
0 |
T25 |
6442 |
6348 |
0 |
0 |
T26 |
1443 |
1390 |
0 |
0 |
T27 |
10425 |
10400 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462284330 |
460141252 |
0 |
0 |
T1 |
741536 |
741223 |
0 |
0 |
T2 |
181205 |
181098 |
0 |
0 |
T5 |
1929 |
1808 |
0 |
0 |
T6 |
5578 |
5498 |
0 |
0 |
T7 |
1579 |
1540 |
0 |
0 |
T17 |
10052 |
9972 |
0 |
0 |
T24 |
2078 |
1984 |
0 |
0 |
T25 |
6442 |
6348 |
0 |
0 |
T26 |
1443 |
1390 |
0 |
0 |
T27 |
10425 |
10400 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
230354170 |
230354170 |
0 |
0 |
T1 |
370613 |
370613 |
0 |
0 |
T2 |
90549 |
90549 |
0 |
0 |
T5 |
904 |
904 |
0 |
0 |
T6 |
2749 |
2749 |
0 |
0 |
T7 |
787 |
787 |
0 |
0 |
T17 |
5828 |
5828 |
0 |
0 |
T24 |
1085 |
1085 |
0 |
0 |
T25 |
3174 |
3174 |
0 |
0 |
T26 |
695 |
695 |
0 |
0 |
T27 |
5886 |
5886 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
230354170 |
230354170 |
0 |
0 |
T1 |
370613 |
370613 |
0 |
0 |
T2 |
90549 |
90549 |
0 |
0 |
T5 |
904 |
904 |
0 |
0 |
T6 |
2749 |
2749 |
0 |
0 |
T7 |
787 |
787 |
0 |
0 |
T17 |
5828 |
5828 |
0 |
0 |
T24 |
1085 |
1085 |
0 |
0 |
T25 |
3174 |
3174 |
0 |
0 |
T26 |
695 |
695 |
0 |
0 |
T27 |
5886 |
5886 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
115176481 |
115176481 |
0 |
0 |
T1 |
185306 |
185306 |
0 |
0 |
T2 |
45275 |
45275 |
0 |
0 |
T5 |
452 |
452 |
0 |
0 |
T6 |
1375 |
1375 |
0 |
0 |
T7 |
393 |
393 |
0 |
0 |
T17 |
2913 |
2913 |
0 |
0 |
T24 |
542 |
542 |
0 |
0 |
T25 |
1587 |
1587 |
0 |
0 |
T26 |
348 |
348 |
0 |
0 |
T27 |
2941 |
2941 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
115176481 |
115176481 |
0 |
0 |
T1 |
185306 |
185306 |
0 |
0 |
T2 |
45275 |
45275 |
0 |
0 |
T5 |
452 |
452 |
0 |
0 |
T6 |
1375 |
1375 |
0 |
0 |
T7 |
393 |
393 |
0 |
0 |
T17 |
2913 |
2913 |
0 |
0 |
T24 |
542 |
542 |
0 |
0 |
T25 |
1587 |
1587 |
0 |
0 |
T26 |
348 |
348 |
0 |
0 |
T27 |
2941 |
2941 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
236463771 |
235368120 |
0 |
0 |
T1 |
390945 |
390789 |
0 |
0 |
T2 |
90607 |
90554 |
0 |
0 |
T5 |
964 |
904 |
0 |
0 |
T6 |
2789 |
2749 |
0 |
0 |
T7 |
789 |
770 |
0 |
0 |
T17 |
5026 |
4986 |
0 |
0 |
T24 |
1039 |
993 |
0 |
0 |
T25 |
3221 |
3174 |
0 |
0 |
T26 |
722 |
696 |
0 |
0 |
T27 |
5213 |
5201 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
236463771 |
235368120 |
0 |
0 |
T1 |
390945 |
390789 |
0 |
0 |
T2 |
90607 |
90554 |
0 |
0 |
T5 |
964 |
904 |
0 |
0 |
T6 |
2789 |
2749 |
0 |
0 |
T7 |
789 |
770 |
0 |
0 |
T17 |
5026 |
4986 |
0 |
0 |
T24 |
1039 |
993 |
0 |
0 |
T25 |
3221 |
3174 |
0 |
0 |
T26 |
722 |
696 |
0 |
0 |
T27 |
5213 |
5201 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Assert Coverage for Instance : tb.dut.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146767171 |
144206730 |
0 |
0 |
T1 |
741157 |
740500 |
0 |
0 |
T2 |
94380 |
94267 |
0 |
0 |
T5 |
2008 |
1782 |
0 |
0 |
T6 |
1394 |
1353 |
0 |
0 |
T7 |
1579 |
1403 |
0 |
0 |
T17 |
1570 |
1536 |
0 |
0 |
T24 |
2164 |
1924 |
0 |
0 |
T25 |
2884 |
2781 |
0 |
0 |
T26 |
1443 |
1294 |
0 |
0 |
T27 |
1954 |
1942 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146767171 |
144199567 |
0 |
2415 |
T1 |
741157 |
740481 |
0 |
3 |
T2 |
94380 |
94264 |
0 |
3 |
T5 |
2008 |
1779 |
0 |
3 |
T6 |
1394 |
1350 |
0 |
3 |
T7 |
1579 |
1400 |
0 |
3 |
T17 |
1570 |
1533 |
0 |
3 |
T24 |
2164 |
1921 |
0 |
3 |
T25 |
2884 |
2778 |
0 |
3 |
T26 |
1443 |
1291 |
0 |
3 |
T27 |
1954 |
1939 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146767171 |
144206730 |
0 |
0 |
T1 |
741157 |
740500 |
0 |
0 |
T2 |
94380 |
94267 |
0 |
0 |
T5 |
2008 |
1782 |
0 |
0 |
T6 |
1394 |
1353 |
0 |
0 |
T7 |
1579 |
1403 |
0 |
0 |
T17 |
1570 |
1536 |
0 |
0 |
T24 |
2164 |
1924 |
0 |
0 |
T25 |
2884 |
2781 |
0 |
0 |
T26 |
1443 |
1294 |
0 |
0 |
T27 |
1954 |
1942 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146767171 |
144199567 |
0 |
2415 |
T1 |
741157 |
740481 |
0 |
3 |
T2 |
94380 |
94264 |
0 |
3 |
T5 |
2008 |
1779 |
0 |
3 |
T6 |
1394 |
1350 |
0 |
3 |
T7 |
1579 |
1400 |
0 |
3 |
T17 |
1570 |
1533 |
0 |
3 |
T24 |
2164 |
1921 |
0 |
3 |
T25 |
2884 |
2778 |
0 |
3 |
T26 |
1443 |
1291 |
0 |
3 |
T27 |
1954 |
1939 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146767171 |
144206730 |
0 |
0 |
T1 |
741157 |
740500 |
0 |
0 |
T2 |
94380 |
94267 |
0 |
0 |
T5 |
2008 |
1782 |
0 |
0 |
T6 |
1394 |
1353 |
0 |
0 |
T7 |
1579 |
1403 |
0 |
0 |
T17 |
1570 |
1536 |
0 |
0 |
T24 |
2164 |
1924 |
0 |
0 |
T25 |
2884 |
2781 |
0 |
0 |
T26 |
1443 |
1294 |
0 |
0 |
T27 |
1954 |
1942 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146767171 |
144199567 |
0 |
2415 |
T1 |
741157 |
740481 |
0 |
3 |
T2 |
94380 |
94264 |
0 |
3 |
T5 |
2008 |
1779 |
0 |
3 |
T6 |
1394 |
1350 |
0 |
3 |
T7 |
1579 |
1400 |
0 |
3 |
T17 |
1570 |
1533 |
0 |
3 |
T24 |
2164 |
1921 |
0 |
3 |
T25 |
2884 |
2778 |
0 |
3 |
T26 |
1443 |
1291 |
0 |
3 |
T27 |
1954 |
1939 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146767171 |
144206730 |
0 |
0 |
T1 |
741157 |
740500 |
0 |
0 |
T2 |
94380 |
94267 |
0 |
0 |
T5 |
2008 |
1782 |
0 |
0 |
T6 |
1394 |
1353 |
0 |
0 |
T7 |
1579 |
1403 |
0 |
0 |
T17 |
1570 |
1536 |
0 |
0 |
T24 |
2164 |
1924 |
0 |
0 |
T25 |
2884 |
2781 |
0 |
0 |
T26 |
1443 |
1294 |
0 |
0 |
T27 |
1954 |
1942 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146767171 |
144199567 |
0 |
2415 |
T1 |
741157 |
740481 |
0 |
3 |
T2 |
94380 |
94264 |
0 |
3 |
T5 |
2008 |
1779 |
0 |
3 |
T6 |
1394 |
1350 |
0 |
3 |
T7 |
1579 |
1400 |
0 |
3 |
T17 |
1570 |
1533 |
0 |
3 |
T24 |
2164 |
1921 |
0 |
3 |
T25 |
2884 |
2778 |
0 |
3 |
T26 |
1443 |
1291 |
0 |
3 |
T27 |
1954 |
1939 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146767171 |
144206730 |
0 |
0 |
T1 |
741157 |
740500 |
0 |
0 |
T2 |
94380 |
94267 |
0 |
0 |
T5 |
2008 |
1782 |
0 |
0 |
T6 |
1394 |
1353 |
0 |
0 |
T7 |
1579 |
1403 |
0 |
0 |
T17 |
1570 |
1536 |
0 |
0 |
T24 |
2164 |
1924 |
0 |
0 |
T25 |
2884 |
2781 |
0 |
0 |
T26 |
1443 |
1294 |
0 |
0 |
T27 |
1954 |
1942 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146767171 |
144199567 |
0 |
2415 |
T1 |
741157 |
740481 |
0 |
3 |
T2 |
94380 |
94264 |
0 |
3 |
T5 |
2008 |
1779 |
0 |
3 |
T6 |
1394 |
1350 |
0 |
3 |
T7 |
1579 |
1400 |
0 |
3 |
T17 |
1570 |
1533 |
0 |
3 |
T24 |
2164 |
1921 |
0 |
3 |
T25 |
2884 |
2778 |
0 |
3 |
T26 |
1443 |
1291 |
0 |
3 |
T27 |
1954 |
1939 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146767171 |
144206730 |
0 |
0 |
T1 |
741157 |
740500 |
0 |
0 |
T2 |
94380 |
94267 |
0 |
0 |
T5 |
2008 |
1782 |
0 |
0 |
T6 |
1394 |
1353 |
0 |
0 |
T7 |
1579 |
1403 |
0 |
0 |
T17 |
1570 |
1536 |
0 |
0 |
T24 |
2164 |
1924 |
0 |
0 |
T25 |
2884 |
2781 |
0 |
0 |
T26 |
1443 |
1294 |
0 |
0 |
T27 |
1954 |
1942 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146767171 |
144199567 |
0 |
2415 |
T1 |
741157 |
740481 |
0 |
3 |
T2 |
94380 |
94264 |
0 |
3 |
T5 |
2008 |
1779 |
0 |
3 |
T6 |
1394 |
1350 |
0 |
3 |
T7 |
1579 |
1400 |
0 |
3 |
T17 |
1570 |
1533 |
0 |
3 |
T24 |
2164 |
1921 |
0 |
3 |
T25 |
2884 |
2778 |
0 |
3 |
T26 |
1443 |
1291 |
0 |
3 |
T27 |
1954 |
1939 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146767171 |
144206730 |
0 |
0 |
T1 |
741157 |
740500 |
0 |
0 |
T2 |
94380 |
94267 |
0 |
0 |
T5 |
2008 |
1782 |
0 |
0 |
T6 |
1394 |
1353 |
0 |
0 |
T7 |
1579 |
1403 |
0 |
0 |
T17 |
1570 |
1536 |
0 |
0 |
T24 |
2164 |
1924 |
0 |
0 |
T25 |
2884 |
2781 |
0 |
0 |
T26 |
1443 |
1294 |
0 |
0 |
T27 |
1954 |
1942 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146767171 |
144206730 |
0 |
0 |
T1 |
741157 |
740500 |
0 |
0 |
T2 |
94380 |
94267 |
0 |
0 |
T5 |
2008 |
1782 |
0 |
0 |
T6 |
1394 |
1353 |
0 |
0 |
T7 |
1579 |
1403 |
0 |
0 |
T17 |
1570 |
1536 |
0 |
0 |
T24 |
2164 |
1924 |
0 |
0 |
T25 |
2884 |
2781 |
0 |
0 |
T26 |
1443 |
1294 |
0 |
0 |
T27 |
1954 |
1942 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146767171 |
144206730 |
0 |
0 |
T1 |
741157 |
740500 |
0 |
0 |
T2 |
94380 |
94267 |
0 |
0 |
T5 |
2008 |
1782 |
0 |
0 |
T6 |
1394 |
1353 |
0 |
0 |
T7 |
1579 |
1403 |
0 |
0 |
T17 |
1570 |
1536 |
0 |
0 |
T24 |
2164 |
1924 |
0 |
0 |
T25 |
2884 |
2781 |
0 |
0 |
T26 |
1443 |
1294 |
0 |
0 |
T27 |
1954 |
1942 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146767171 |
144206730 |
0 |
0 |
T1 |
741157 |
740500 |
0 |
0 |
T2 |
94380 |
94267 |
0 |
0 |
T5 |
2008 |
1782 |
0 |
0 |
T6 |
1394 |
1353 |
0 |
0 |
T7 |
1579 |
1403 |
0 |
0 |
T17 |
1570 |
1536 |
0 |
0 |
T24 |
2164 |
1924 |
0 |
0 |
T25 |
2884 |
2781 |
0 |
0 |
T26 |
1443 |
1294 |
0 |
0 |
T27 |
1954 |
1942 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146767171 |
144206730 |
0 |
0 |
T1 |
741157 |
740500 |
0 |
0 |
T2 |
94380 |
94267 |
0 |
0 |
T5 |
2008 |
1782 |
0 |
0 |
T6 |
1394 |
1353 |
0 |
0 |
T7 |
1579 |
1403 |
0 |
0 |
T17 |
1570 |
1536 |
0 |
0 |
T24 |
2164 |
1924 |
0 |
0 |
T25 |
2884 |
2781 |
0 |
0 |
T26 |
1443 |
1294 |
0 |
0 |
T27 |
1954 |
1942 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146767171 |
144206730 |
0 |
0 |
T1 |
741157 |
740500 |
0 |
0 |
T2 |
94380 |
94267 |
0 |
0 |
T5 |
2008 |
1782 |
0 |
0 |
T6 |
1394 |
1353 |
0 |
0 |
T7 |
1579 |
1403 |
0 |
0 |
T17 |
1570 |
1536 |
0 |
0 |
T24 |
2164 |
1924 |
0 |
0 |
T25 |
2884 |
2781 |
0 |
0 |
T26 |
1443 |
1294 |
0 |
0 |
T27 |
1954 |
1942 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146767171 |
144206730 |
0 |
0 |
T1 |
741157 |
740500 |
0 |
0 |
T2 |
94380 |
94267 |
0 |
0 |
T5 |
2008 |
1782 |
0 |
0 |
T6 |
1394 |
1353 |
0 |
0 |
T7 |
1579 |
1403 |
0 |
0 |
T17 |
1570 |
1536 |
0 |
0 |
T24 |
2164 |
1924 |
0 |
0 |
T25 |
2884 |
2781 |
0 |
0 |
T26 |
1443 |
1294 |
0 |
0 |
T27 |
1954 |
1942 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146767171 |
144206730 |
0 |
0 |
T1 |
741157 |
740500 |
0 |
0 |
T2 |
94380 |
94267 |
0 |
0 |
T5 |
2008 |
1782 |
0 |
0 |
T6 |
1394 |
1353 |
0 |
0 |
T7 |
1579 |
1403 |
0 |
0 |
T17 |
1570 |
1536 |
0 |
0 |
T24 |
2164 |
1924 |
0 |
0 |
T25 |
2884 |
2781 |
0 |
0 |
T26 |
1443 |
1294 |
0 |
0 |
T27 |
1954 |
1942 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492655958 |
488072278 |
0 |
0 |
T1 |
808457 |
807730 |
0 |
0 |
T2 |
188762 |
188536 |
0 |
0 |
T5 |
2008 |
1782 |
0 |
0 |
T6 |
5810 |
5642 |
0 |
0 |
T7 |
1645 |
1462 |
0 |
0 |
T17 |
10471 |
10245 |
0 |
0 |
T24 |
2164 |
1924 |
0 |
0 |
T25 |
6710 |
6470 |
0 |
0 |
T26 |
1504 |
1349 |
0 |
0 |
T27 |
10860 |
10791 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492655958 |
488065192 |
0 |
2415 |
T1 |
808457 |
807715 |
0 |
3 |
T2 |
188762 |
188533 |
0 |
3 |
T5 |
2008 |
1779 |
0 |
3 |
T6 |
5810 |
5639 |
0 |
3 |
T7 |
1645 |
1459 |
0 |
3 |
T17 |
10471 |
10242 |
0 |
3 |
T24 |
2164 |
1921 |
0 |
3 |
T25 |
6710 |
6467 |
0 |
3 |
T26 |
1504 |
1346 |
0 |
3 |
T27 |
10860 |
10788 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492655958 |
31988 |
0 |
0 |
T1 |
808457 |
98 |
0 |
0 |
T2 |
188762 |
1 |
0 |
0 |
T5 |
2008 |
4 |
0 |
0 |
T6 |
5810 |
14 |
0 |
0 |
T7 |
1645 |
1 |
0 |
0 |
T17 |
10471 |
6 |
0 |
0 |
T24 |
2164 |
9 |
0 |
0 |
T25 |
6710 |
53 |
0 |
0 |
T26 |
1504 |
8 |
0 |
0 |
T27 |
10860 |
15 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492655958 |
488072278 |
0 |
0 |
T1 |
808457 |
807730 |
0 |
0 |
T2 |
188762 |
188536 |
0 |
0 |
T5 |
2008 |
1782 |
0 |
0 |
T6 |
5810 |
5642 |
0 |
0 |
T7 |
1645 |
1462 |
0 |
0 |
T17 |
10471 |
10245 |
0 |
0 |
T24 |
2164 |
1924 |
0 |
0 |
T25 |
6710 |
6470 |
0 |
0 |
T26 |
1504 |
1349 |
0 |
0 |
T27 |
10860 |
10791 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492655958 |
488072278 |
0 |
0 |
T1 |
808457 |
807730 |
0 |
0 |
T2 |
188762 |
188536 |
0 |
0 |
T5 |
2008 |
1782 |
0 |
0 |
T6 |
5810 |
5642 |
0 |
0 |
T7 |
1645 |
1462 |
0 |
0 |
T17 |
10471 |
10245 |
0 |
0 |
T24 |
2164 |
1924 |
0 |
0 |
T25 |
6710 |
6470 |
0 |
0 |
T26 |
1504 |
1349 |
0 |
0 |
T27 |
10860 |
10791 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492655958 |
488072278 |
0 |
0 |
T1 |
808457 |
807730 |
0 |
0 |
T2 |
188762 |
188536 |
0 |
0 |
T5 |
2008 |
1782 |
0 |
0 |
T6 |
5810 |
5642 |
0 |
0 |
T7 |
1645 |
1462 |
0 |
0 |
T17 |
10471 |
10245 |
0 |
0 |
T24 |
2164 |
1924 |
0 |
0 |
T25 |
6710 |
6470 |
0 |
0 |
T26 |
1504 |
1349 |
0 |
0 |
T27 |
10860 |
10791 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492655958 |
488065192 |
0 |
2415 |
T1 |
808457 |
807715 |
0 |
3 |
T2 |
188762 |
188533 |
0 |
3 |
T5 |
2008 |
1779 |
0 |
3 |
T6 |
5810 |
5639 |
0 |
3 |
T7 |
1645 |
1459 |
0 |
3 |
T17 |
10471 |
10242 |
0 |
3 |
T24 |
2164 |
1921 |
0 |
3 |
T25 |
6710 |
6467 |
0 |
3 |
T26 |
1504 |
1346 |
0 |
3 |
T27 |
10860 |
10788 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492655958 |
31888 |
0 |
0 |
T1 |
808457 |
95 |
0 |
0 |
T2 |
188762 |
1 |
0 |
0 |
T5 |
2008 |
4 |
0 |
0 |
T6 |
5810 |
17 |
0 |
0 |
T7 |
1645 |
3 |
0 |
0 |
T17 |
10471 |
17 |
0 |
0 |
T24 |
2164 |
15 |
0 |
0 |
T25 |
6710 |
56 |
0 |
0 |
T26 |
1504 |
8 |
0 |
0 |
T27 |
10860 |
17 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492655958 |
488072278 |
0 |
0 |
T1 |
808457 |
807730 |
0 |
0 |
T2 |
188762 |
188536 |
0 |
0 |
T5 |
2008 |
1782 |
0 |
0 |
T6 |
5810 |
5642 |
0 |
0 |
T7 |
1645 |
1462 |
0 |
0 |
T17 |
10471 |
10245 |
0 |
0 |
T24 |
2164 |
1924 |
0 |
0 |
T25 |
6710 |
6470 |
0 |
0 |
T26 |
1504 |
1349 |
0 |
0 |
T27 |
10860 |
10791 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492655958 |
488072278 |
0 |
0 |
T1 |
808457 |
807730 |
0 |
0 |
T2 |
188762 |
188536 |
0 |
0 |
T5 |
2008 |
1782 |
0 |
0 |
T6 |
5810 |
5642 |
0 |
0 |
T7 |
1645 |
1462 |
0 |
0 |
T17 |
10471 |
10245 |
0 |
0 |
T24 |
2164 |
1924 |
0 |
0 |
T25 |
6710 |
6470 |
0 |
0 |
T26 |
1504 |
1349 |
0 |
0 |
T27 |
10860 |
10791 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492655958 |
488072278 |
0 |
0 |
T1 |
808457 |
807730 |
0 |
0 |
T2 |
188762 |
188536 |
0 |
0 |
T5 |
2008 |
1782 |
0 |
0 |
T6 |
5810 |
5642 |
0 |
0 |
T7 |
1645 |
1462 |
0 |
0 |
T17 |
10471 |
10245 |
0 |
0 |
T24 |
2164 |
1924 |
0 |
0 |
T25 |
6710 |
6470 |
0 |
0 |
T26 |
1504 |
1349 |
0 |
0 |
T27 |
10860 |
10791 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492655958 |
488065192 |
0 |
2415 |
T1 |
808457 |
807715 |
0 |
3 |
T2 |
188762 |
188533 |
0 |
3 |
T5 |
2008 |
1779 |
0 |
3 |
T6 |
5810 |
5639 |
0 |
3 |
T7 |
1645 |
1459 |
0 |
3 |
T17 |
10471 |
10242 |
0 |
3 |
T24 |
2164 |
1921 |
0 |
3 |
T25 |
6710 |
6467 |
0 |
3 |
T26 |
1504 |
1346 |
0 |
3 |
T27 |
10860 |
10788 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492655958 |
31883 |
0 |
0 |
T1 |
808457 |
111 |
0 |
0 |
T2 |
188762 |
1 |
0 |
0 |
T5 |
2008 |
4 |
0 |
0 |
T6 |
5810 |
13 |
0 |
0 |
T7 |
1645 |
3 |
0 |
0 |
T17 |
10471 |
12 |
0 |
0 |
T24 |
2164 |
9 |
0 |
0 |
T25 |
6710 |
51 |
0 |
0 |
T26 |
1504 |
10 |
0 |
0 |
T27 |
10860 |
11 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492655958 |
488072278 |
0 |
0 |
T1 |
808457 |
807730 |
0 |
0 |
T2 |
188762 |
188536 |
0 |
0 |
T5 |
2008 |
1782 |
0 |
0 |
T6 |
5810 |
5642 |
0 |
0 |
T7 |
1645 |
1462 |
0 |
0 |
T17 |
10471 |
10245 |
0 |
0 |
T24 |
2164 |
1924 |
0 |
0 |
T25 |
6710 |
6470 |
0 |
0 |
T26 |
1504 |
1349 |
0 |
0 |
T27 |
10860 |
10791 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492655958 |
488072278 |
0 |
0 |
T1 |
808457 |
807730 |
0 |
0 |
T2 |
188762 |
188536 |
0 |
0 |
T5 |
2008 |
1782 |
0 |
0 |
T6 |
5810 |
5642 |
0 |
0 |
T7 |
1645 |
1462 |
0 |
0 |
T17 |
10471 |
10245 |
0 |
0 |
T24 |
2164 |
1924 |
0 |
0 |
T25 |
6710 |
6470 |
0 |
0 |
T26 |
1504 |
1349 |
0 |
0 |
T27 |
10860 |
10791 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492655958 |
488072278 |
0 |
0 |
T1 |
808457 |
807730 |
0 |
0 |
T2 |
188762 |
188536 |
0 |
0 |
T5 |
2008 |
1782 |
0 |
0 |
T6 |
5810 |
5642 |
0 |
0 |
T7 |
1645 |
1462 |
0 |
0 |
T17 |
10471 |
10245 |
0 |
0 |
T24 |
2164 |
1924 |
0 |
0 |
T25 |
6710 |
6470 |
0 |
0 |
T26 |
1504 |
1349 |
0 |
0 |
T27 |
10860 |
10791 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492655958 |
488065192 |
0 |
2415 |
T1 |
808457 |
807715 |
0 |
3 |
T2 |
188762 |
188533 |
0 |
3 |
T5 |
2008 |
1779 |
0 |
3 |
T6 |
5810 |
5639 |
0 |
3 |
T7 |
1645 |
1459 |
0 |
3 |
T17 |
10471 |
10242 |
0 |
3 |
T24 |
2164 |
1921 |
0 |
3 |
T25 |
6710 |
6467 |
0 |
3 |
T26 |
1504 |
1346 |
0 |
3 |
T27 |
10860 |
10788 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492655958 |
32046 |
0 |
0 |
T1 |
808457 |
68 |
0 |
0 |
T2 |
188762 |
1 |
0 |
0 |
T5 |
2008 |
4 |
0 |
0 |
T6 |
5810 |
16 |
0 |
0 |
T7 |
1645 |
1 |
0 |
0 |
T17 |
10471 |
15 |
0 |
0 |
T24 |
2164 |
7 |
0 |
0 |
T25 |
6710 |
54 |
0 |
0 |
T26 |
1504 |
6 |
0 |
0 |
T27 |
10860 |
17 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492655958 |
488072278 |
0 |
0 |
T1 |
808457 |
807730 |
0 |
0 |
T2 |
188762 |
188536 |
0 |
0 |
T5 |
2008 |
1782 |
0 |
0 |
T6 |
5810 |
5642 |
0 |
0 |
T7 |
1645 |
1462 |
0 |
0 |
T17 |
10471 |
10245 |
0 |
0 |
T24 |
2164 |
1924 |
0 |
0 |
T25 |
6710 |
6470 |
0 |
0 |
T26 |
1504 |
1349 |
0 |
0 |
T27 |
10860 |
10791 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492655958 |
488072278 |
0 |
0 |
T1 |
808457 |
807730 |
0 |
0 |
T2 |
188762 |
188536 |
0 |
0 |
T5 |
2008 |
1782 |
0 |
0 |
T6 |
5810 |
5642 |
0 |
0 |
T7 |
1645 |
1462 |
0 |
0 |
T17 |
10471 |
10245 |
0 |
0 |
T24 |
2164 |
1924 |
0 |
0 |
T25 |
6710 |
6470 |
0 |
0 |
T26 |
1504 |
1349 |
0 |
0 |
T27 |
10860 |
10791 |
0 |
0 |