Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T3,T31

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	146767171	144082951	0	0
AllClkBypReqTrue_A	146767171	121442	0	0
IoClkBypReqFalse_A	146767171	144007213	0	2415
IoClkBypReqTrue_A	146767171	192506	0	0
LcClkBypAckFalse_A	146767171	144089587	0	0
LcClkBypAckTrue_A	146767171	114806	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146767171	144082951	0	0
T1	741157	740495	0	0
T2	94380	94266	0	0
T5	2008	1781	0	0
T6	1394	1352	0	0
T7	1579	1402	0	0
T17	1570	1370	0	0
T24	2164	1873	0	0
T25	2884	2780	0	0
T26	1443	1293	0	0
T27	1954	1730	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146767171	121442	0	0
T1	741157	0	0	0
T2	94380	0	0	0
T3	0	641	0	0
T11	0	1425	0	0
T17	1570	165	0	0
T18	2622	36	0	0
T19	1870	30	0	0
T20	829	49	0	0
T24	2164	50	0	0
T25	2884	0	0	0
T26	1443	0	0	0
T27	1954	211	0	0
T76	0	224	0	0
T122	0	30	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146767171	144007213	0	2415
T1	741157	740485	0	3
T2	94380	94264	0	3
T5	2008	1779	0	3
T6	1394	1350	0	3
T7	1579	1365	0	3
T17	1570	1244	0	3
T24	2164	1617	0	3
T25	2884	2778	0	3
T26	1443	1291	0	3
T27	1954	1513	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146767171	192506	0	0
T1	741157	0	0	0
T2	94380	0	0	0
T3	0	1252	0	0
T7	1579	35	0	0
T17	1570	289	0	0
T18	2622	606	0	0
T19	1870	170	0	0
T20	0	53	0	0
T24	2164	304	0	0
T25	2884	0	0	0
T26	1443	0	0	0
T27	1954	426	0	0
T76	0	295	0	0
T122	0	53	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146767171	144089587	0	0
T1	741157	740495	0	0
T2	94380	94266	0	0
T5	2008	1781	0	0
T6	1394	1352	0	0
T7	1579	1372	0	0
T17	1570	1321	0	0
T24	2164	1741	0	0
T25	2884	2780	0	0
T26	1443	1293	0	0
T27	1954	1724	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146767171	114806	0	0
T1	741157	0	0	0
T2	94380	0	0	0
T3	0	713	0	0
T7	1579	30	0	0
T17	1570	214	0	0
T18	2622	274	0	0
T19	1870	59	0	0
T20	0	30	0	0
T24	2164	182	0	0
T25	2884	0	0	0
T26	1443	0	0	0
T27	1954	217	0	0
T76	0	207	0	0
T122	0	20	0	0