Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1970625664	14925	0	0
TransStop_A	1970625664	7538	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1970625664	14925	0	0
T1	3233832	75	0	0
T2	755048	0	0	0
T3	0	169	0	0
T5	8036	4	0	0
T6	23240	6	0	0
T7	6584	0	0	0
T17	41884	0	0	0
T21	0	41	0	0
T24	8660	0	0	0
T25	26840	34	0	0
T26	6016	0	0	0
T27	43440	0	0	0
T42	0	4	0	0
T73	0	4	0	0
T74	0	38	0	0
T75	0	1	0	0
T79	0	11	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1970625664	7538	0	0
T1	3233832	39	0	0
T2	755048	0	0	0
T3	0	73	0	0
T5	8036	4	0	0
T6	23240	3	0	0
T7	6584	0	0	0
T17	41884	0	0	0
T21	0	10	0	0
T24	8660	0	0	0
T25	26840	12	0	0
T26	6016	0	0	0
T27	43440	0	0	0
T42	0	4	0	0
T73	0	4	0	0
T74	0	19	0	0
T77	0	1	0	0
T79	0	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	492656416	3767	0	0
TransStop_A	492656416	1887	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492656416	3767	0	0
T1	808458	21	0	0
T2	188762	0	0	0
T3	0	38	0	0
T5	2009	1	0	0
T6	5810	0	0	0
T7	1646	0	0	0
T17	10471	0	0	0
T21	0	9	0	0
T24	2165	0	0	0
T25	6710	5	0	0
T26	1504	0	0	0
T27	10860	0	0	0
T42	0	1	0	0
T73	0	1	0	0
T74	0	11	0	0
T75	0	1	0	0
T79	0	3	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492656416	1887	0	0
T1	808458	10	0	0
T2	188762	0	0	0
T3	0	16	0	0
T5	2009	1	0	0
T6	5810	0	0	0
T7	1646	0	0	0
T17	10471	0	0	0
T21	0	3	0	0
T24	2165	0	0	0
T25	6710	1	0	0
T26	1504	0	0	0
T27	10860	0	0	0
T42	0	1	0	0
T73	0	1	0	0
T74	0	7	0	0
T77	0	1	0	0
T79	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	492656416	3698	0	0
TransStop_A	492656416	1884	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492656416	3698	0	0
T1	808458	17	0	0
T2	188762	0	0	0
T3	0	42	0	0
T5	2009	1	0	0
T6	5810	2	0	0
T7	1646	0	0	0
T17	10471	0	0	0
T21	0	12	0	0
T24	2165	0	0	0
T25	6710	12	0	0
T26	1504	0	0	0
T27	10860	0	0	0
T42	0	1	0	0
T73	0	1	0	0
T74	0	9	0	0
T79	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492656416	1884	0	0
T1	808458	10	0	0
T2	188762	0	0	0
T3	0	20	0	0
T5	2009	1	0	0
T6	5810	1	0	0
T7	1646	0	0	0
T17	10471	0	0	0
T21	0	1	0	0
T24	2165	0	0	0
T25	6710	4	0	0
T26	1504	0	0	0
T27	10860	0	0	0
T42	0	1	0	0
T73	0	1	0	0
T74	0	5	0	0
T79	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	492656416	3742	0	0
TransStop_A	492656416	1884	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492656416	3742	0	0
T1	808458	21	0	0
T2	188762	0	0	0
T3	0	45	0	0
T5	2009	1	0	0
T6	5810	2	0	0
T7	1646	0	0	0
T17	10471	0	0	0
T21	0	8	0	0
T24	2165	0	0	0
T25	6710	10	0	0
T26	1504	0	0	0
T27	10860	0	0	0
T42	0	1	0	0
T73	0	1	0	0
T74	0	11	0	0
T79	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492656416	1884	0	0
T1	808458	10	0	0
T2	188762	0	0	0
T3	0	18	0	0
T5	2009	1	0	0
T6	5810	1	0	0
T7	1646	0	0	0
T17	10471	0	0	0
T21	0	2	0	0
T24	2165	0	0	0
T25	6710	3	0	0
T26	1504	0	0	0
T27	10860	0	0	0
T42	0	1	0	0
T73	0	1	0	0
T74	0	5	0	0
T79	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	492656416	3718	0	0
TransStop_A	492656416	1883	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492656416	3718	0	0
T1	808458	16	0	0
T2	188762	0	0	0
T3	0	44	0	0
T5	2009	1	0	0
T6	5810	2	0	0
T7	1646	0	0	0
T17	10471	0	0	0
T21	0	12	0	0
T24	2165	0	0	0
T25	6710	7	0	0
T26	1504	0	0	0
T27	10860	0	0	0
T42	0	1	0	0
T73	0	1	0	0
T74	0	7	0	0
T79	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492656416	1883	0	0
T1	808458	9	0	0
T2	188762	0	0	0
T3	0	19	0	0
T5	2009	1	0	0
T6	5810	1	0	0
T7	1646	0	0	0
T17	10471	0	0	0
T21	0	4	0	0
T24	2165	0	0	0
T25	6710	4	0	0
T26	1504	0	0	0
T27	10860	0	0	0
T42	0	1	0	0
T73	0	1	0	0
T74	0	2	0	0
T79	0	3	0	0