Module Definition
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Module Instance : tb.dut.u_clkmgr_byp.u_io_byp_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_clkmgr_byp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00
gen_sec_buf.u_prim_sec_buf 100.00 100.00



Module Instance : tb.dut.u_clkmgr_byp.u_all_byp_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_clkmgr_byp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00
gen_sec_buf.u_prim_sec_buf 100.00 100.00



Module Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_clkmgr_byp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_aes_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_hmac_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_kmac_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_otbn_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00

Line Coverage for Module : prim_mubi4_sender ( parameter AsyncOn=1,EnSecBuf=1,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_clkmgr_byp.u_io_byp_req

SCORELINE
100.00 100.00
tb.dut.u_clkmgr_byp.u_all_byp_req

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
85 1 1


Line Coverage for Module : prim_mubi4_sender ( parameter AsyncOn=1,EnSecBuf=0,ResetValue=6 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_clkmgr_byp.u_hi_speed_sel

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_infra

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_main_infra

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_usb_infra

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_infra

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_div2_infra

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_secure

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_main_secure

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_timers

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_peri

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_div2_peri

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_peri

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_usb_peri

SCORELINE
100.00 100.00
tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender

SCORELINE
100.00 100.00
tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender

SCORELINE
100.00 100.00
tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender

SCORELINE
100.00 100.00
tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender

Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Module : prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 2147483647 2147483647 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 10821625 10812426 0 0
T2 2321534 2318967 0 0
T5 27474 24598 0 0
T6 66774 64987 0 0
T7 22489 20063 0 0
T17 121000 118616 0 0
T24 30048 26922 0 0
T25 80934 78219 0 0
T26 20465 18450 0 0
T27 125834 125104 0 0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_byp_req
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_byp_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 146767171 144206730 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 146767171 144206730 0 0
T1 741157 740500 0 0
T2 94380 94267 0 0
T5 2008 1782 0 0
T6 1394 1353 0 0
T7 1579 1403 0 0
T17 1570 1536 0 0
T24 2164 1924 0 0
T25 2884 2781 0 0
T26 1443 1294 0 0
T27 1954 1942 0 0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_byp_req
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_byp_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 146767171 144206730 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 146767171 144206730 0 0
T1 741157 740500 0 0
T2 94380 94267 0 0
T5 2008 1782 0 0
T6 1394 1353 0 0
T7 1579 1403 0 0
T17 1570 1536 0 0
T24 2164 1924 0 0
T25 2884 2781 0 0
T26 1443 1294 0 0
T27 1954 1942 0 0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 146767171 144206730 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 146767171 144206730 0 0
T1 741157 740500 0 0
T2 94380 94267 0 0
T5 2008 1782 0 0
T6 1394 1353 0 0
T7 1579 1403 0 0
T17 1570 1536 0 0
T24 2164 1924 0 0
T25 2884 2781 0 0
T26 1443 1294 0 0
T27 1954 1942 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 115176481 114629457 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 115176481 114629457 0 0
T1 185306 185209 0 0
T2 45275 45247 0 0
T5 452 428 0 0
T6 1375 1354 0 0
T7 393 359 0 0
T17 2913 2879 0 0
T24 542 508 0 0
T25 1587 1553 0 0
T26 348 324 0 0
T27 2941 2931 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 492655958 488072278 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 492655958 488072278 0 0
T1 808457 807730 0 0
T2 188762 188536 0 0
T5 2008 1782 0 0
T6 5810 5642 0 0
T7 1645 1462 0 0
T17 10471 10245 0 0
T24 2164 1924 0 0
T25 6710 6470 0 0
T26 1504 1349 0 0
T27 10860 10791 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 236463771 234249859 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 236463771 234249859 0 0
T1 390945 390597 0 0
T2 90607 90499 0 0
T5 964 856 0 0
T6 2789 2708 0 0
T7 789 702 0 0
T17 5026 4917 0 0
T24 1039 924 0 0
T25 3221 3106 0 0
T26 722 648 0 0
T27 5213 5180 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 462284330 457953853 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462284330 457953853 0 0
T1 741536 740838 0 0
T2 181205 180988 0 0
T5 1929 1712 0 0
T6 5578 5415 0 0
T7 1579 1403 0 0
T17 10052 9835 0 0
T24 2078 1847 0 0
T25 6442 6211 0 0
T26 1443 1294 0 0
T27 10425 10359 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 230354170 229259986 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 230354170 229259986 0 0
T1 370613 370420 0 0
T2 90549 90494 0 0
T5 904 856 0 0
T6 2749 2707 0 0
T7 787 718 0 0
T17 5828 5759 0 0
T24 1085 1016 0 0
T25 3174 3105 0 0
T26 695 647 0 0
T27 5886 5865 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 115176481 114629457 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 115176481 114629457 0 0
T1 185306 185209 0 0
T2 45275 45247 0 0
T5 452 428 0 0
T6 1375 1354 0 0
T7 393 359 0 0
T17 2913 2879 0 0
T24 542 508 0 0
T25 1587 1553 0 0
T26 348 324 0 0
T27 2941 2931 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 492655958 488072278 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 492655958 488072278 0 0
T1 808457 807730 0 0
T2 188762 188536 0 0
T5 2008 1782 0 0
T6 5810 5642 0 0
T7 1645 1462 0 0
T17 10471 10245 0 0
T24 2164 1924 0 0
T25 6710 6470 0 0
T26 1504 1349 0 0
T27 10860 10791 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 115176481 114629457 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 115176481 114629457 0 0
T1 185306 185209 0 0
T2 45275 45247 0 0
T5 452 428 0 0
T6 1375 1354 0 0
T7 393 359 0 0
T17 2913 2879 0 0
T24 542 508 0 0
T25 1587 1553 0 0
T26 348 324 0 0
T27 2941 2931 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 115176481 114629457 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 115176481 114629457 0 0
T1 185306 185209 0 0
T2 45275 45247 0 0
T5 452 428 0 0
T6 1375 1354 0 0
T7 393 359 0 0
T17 2913 2879 0 0
T24 542 508 0 0
T25 1587 1553 0 0
T26 348 324 0 0
T27 2941 2931 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 230354170 229259986 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 230354170 229259986 0 0
T1 370613 370420 0 0
T2 90549 90494 0 0
T5 904 856 0 0
T6 2749 2707 0 0
T7 787 718 0 0
T17 5828 5759 0 0
T24 1085 1016 0 0
T25 3174 3105 0 0
T26 695 647 0 0
T27 5886 5865 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 462284330 457953853 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462284330 457953853 0 0
T1 741536 740838 0 0
T2 181205 180988 0 0
T5 1929 1712 0 0
T6 5578 5415 0 0
T7 1579 1403 0 0
T17 10052 9835 0 0
T24 2078 1847 0 0
T25 6442 6211 0 0
T26 1443 1294 0 0
T27 10425 10359 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 236463771 234249859 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 236463771 234249859 0 0
T1 390945 390597 0 0
T2 90607 90499 0 0
T5 964 856 0 0
T6 2789 2708 0 0
T7 789 702 0 0
T17 5026 4917 0 0
T24 1039 924 0 0
T25 3221 3106 0 0
T26 722 648 0 0
T27 5213 5180 0 0

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 492655958 488072278 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 492655958 488072278 0 0
T1 808457 807730 0 0
T2 188762 188536 0 0
T5 2008 1782 0 0
T6 5810 5642 0 0
T7 1645 1462 0 0
T17 10471 10245 0 0
T24 2164 1924 0 0
T25 6710 6470 0 0
T26 1504 1349 0 0
T27 10860 10791 0 0

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 492655958 488072278 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 492655958 488072278 0 0
T1 808457 807730 0 0
T2 188762 188536 0 0
T5 2008 1782 0 0
T6 5810 5642 0 0
T7 1645 1462 0 0
T17 10471 10245 0 0
T24 2164 1924 0 0
T25 6710 6470 0 0
T26 1504 1349 0 0
T27 10860 10791 0 0

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 492655958 488072278 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 492655958 488072278 0 0
T1 808457 807730 0 0
T2 188762 188536 0 0
T5 2008 1782 0 0
T6 5810 5642 0 0
T7 1645 1462 0 0
T17 10471 10245 0 0
T24 2164 1924 0 0
T25 6710 6470 0 0
T26 1504 1349 0 0
T27 10860 10791 0 0

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 492655958 488072278 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 492655958 488072278 0 0
T1 808457 807730 0 0
T2 188762 188536 0 0
T5 2008 1782 0 0
T6 5810 5642 0 0
T7 1645 1462 0 0
T17 10471 10245 0 0
T24 2164 1924 0 0
T25 6710 6470 0 0
T26 1504 1349 0 0
T27 10860 10791 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%