SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_clkmgr_byp.u_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_clkmgr_byp.u_lc_byp_req | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_clkmgr_byp |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_clkmgr_byp |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1610 | 1610 | 0 | 0 |
OutputsKnown_A | 293534342 | 288413460 | 0 | 0 |
gen_flops.OutputDelay_A | 293534342 | 288399134 | 0 | 4830 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1610 | 1610 | 0 | 0 |
T1 | 2 | 2 | 0 | 0 |
T2 | 2 | 2 | 0 | 0 |
T5 | 2 | 2 | 0 | 0 |
T6 | 2 | 2 | 0 | 0 |
T7 | 2 | 2 | 0 | 0 |
T17 | 2 | 2 | 0 | 0 |
T24 | 2 | 2 | 0 | 0 |
T25 | 2 | 2 | 0 | 0 |
T26 | 2 | 2 | 0 | 0 |
T27 | 2 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 293534342 | 288413460 | 0 | 0 |
T1 | 1482314 | 1481000 | 0 | 0 |
T2 | 188760 | 188534 | 0 | 0 |
T5 | 4016 | 3564 | 0 | 0 |
T6 | 2788 | 2706 | 0 | 0 |
T7 | 3158 | 2806 | 0 | 0 |
T17 | 3140 | 3072 | 0 | 0 |
T24 | 4328 | 3848 | 0 | 0 |
T25 | 5768 | 5562 | 0 | 0 |
T26 | 2886 | 2588 | 0 | 0 |
T27 | 3908 | 3884 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 293534342 | 288399134 | 0 | 4830 |
T1 | 1482314 | 1480962 | 0 | 6 |
T2 | 188760 | 188528 | 0 | 6 |
T5 | 4016 | 3558 | 0 | 6 |
T6 | 2788 | 2700 | 0 | 6 |
T7 | 3158 | 2800 | 0 | 6 |
T17 | 3140 | 3066 | 0 | 6 |
T24 | 4328 | 3842 | 0 | 6 |
T25 | 5768 | 5556 | 0 | 6 |
T26 | 2886 | 2582 | 0 | 6 |
T27 | 3908 | 3878 | 0 | 6 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 805 | 805 | 0 | 0 |
OutputsKnown_A | 146767171 | 144206730 | 0 | 0 |
gen_flops.OutputDelay_A | 146767171 | 144199567 | 0 | 2415 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 805 | 805 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T25 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 146767171 | 144206730 | 0 | 0 |
T1 | 741157 | 740500 | 0 | 0 |
T2 | 94380 | 94267 | 0 | 0 |
T5 | 2008 | 1782 | 0 | 0 |
T6 | 1394 | 1353 | 0 | 0 |
T7 | 1579 | 1403 | 0 | 0 |
T17 | 1570 | 1536 | 0 | 0 |
T24 | 2164 | 1924 | 0 | 0 |
T25 | 2884 | 2781 | 0 | 0 |
T26 | 1443 | 1294 | 0 | 0 |
T27 | 1954 | 1942 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 146767171 | 144199567 | 0 | 2415 |
T1 | 741157 | 740481 | 0 | 3 |
T2 | 94380 | 94264 | 0 | 3 |
T5 | 2008 | 1779 | 0 | 3 |
T6 | 1394 | 1350 | 0 | 3 |
T7 | 1579 | 1400 | 0 | 3 |
T17 | 1570 | 1533 | 0 | 3 |
T24 | 2164 | 1921 | 0 | 3 |
T25 | 2884 | 2778 | 0 | 3 |
T26 | 1443 | 1291 | 0 | 3 |
T27 | 1954 | 1939 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 805 | 805 | 0 | 0 |
OutputsKnown_A | 146767171 | 144206730 | 0 | 0 |
gen_flops.OutputDelay_A | 146767171 | 144199567 | 0 | 2415 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 805 | 805 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T25 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 146767171 | 144206730 | 0 | 0 |
T1 | 741157 | 740500 | 0 | 0 |
T2 | 94380 | 94267 | 0 | 0 |
T5 | 2008 | 1782 | 0 | 0 |
T6 | 1394 | 1353 | 0 | 0 |
T7 | 1579 | 1403 | 0 | 0 |
T17 | 1570 | 1536 | 0 | 0 |
T24 | 2164 | 1924 | 0 | 0 |
T25 | 2884 | 2781 | 0 | 0 |
T26 | 1443 | 1294 | 0 | 0 |
T27 | 1954 | 1942 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 146767171 | 144199567 | 0 | 2415 |
T1 | 741157 | 740481 | 0 | 3 |
T2 | 94380 | 94264 | 0 | 3 |
T5 | 2008 | 1779 | 0 | 3 |
T6 | 1394 | 1350 | 0 | 3 |
T7 | 1579 | 1400 | 0 | 3 |
T17 | 1570 | 1533 | 0 | 3 |
T24 | 2164 | 1921 | 0 | 3 |
T25 | 2884 | 2778 | 0 | 3 |
T26 | 1443 | 1291 | 0 | 3 |
T27 | 1954 | 1939 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |