Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	146767171	18603911	0	56

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146767171	18603911	0	56
T1	741157	101326	0	0
T2	94380	12833	0	1
T3	0	128931	0	0
T4	37414	0	0	0
T10	0	9439	0	1
T11	0	46610	0	0
T12	0	98089	0	0
T13	0	73215	0	1
T14	0	9062	0	1
T15	0	0	0	1
T16	0	0	0	1
T17	1570	0	0	0
T18	2622	0	0	0
T19	1870	0	0	0
T20	829	0	0	0
T21	2318	0	0	0
T22	96216	0	0	0
T23	1225	0	0	0
T28	0	1078	0	0
T29	0	0	0	1
T30	0	0	0	1
T33	0	955	0	1
T123	0	0	0	1