Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Module :
prim_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
921608 |
0 |
0 |
T1 |
3588295 |
2038 |
0 |
0 |
T2 |
781269 |
428 |
0 |
0 |
T3 |
0 |
5041 |
0 |
0 |
T4 |
138483 |
122 |
0 |
0 |
T10 |
0 |
152 |
0 |
0 |
T11 |
0 |
7489 |
0 |
0 |
T12 |
0 |
1042 |
0 |
0 |
T13 |
0 |
1156 |
0 |
0 |
T17 |
42490 |
0 |
0 |
0 |
T18 |
12985 |
0 |
0 |
0 |
T19 |
8710 |
0 |
0 |
0 |
T20 |
13285 |
0 |
0 |
0 |
T21 |
36014 |
0 |
0 |
0 |
T22 |
415732 |
480 |
0 |
0 |
T23 |
5669 |
0 |
0 |
0 |
T31 |
0 |
60 |
0 |
0 |
T32 |
0 |
272 |
0 |
0 |
T57 |
17042 |
4 |
0 |
0 |
T58 |
9722 |
2 |
0 |
0 |
T60 |
8258 |
1 |
0 |
0 |
T62 |
8484 |
3 |
0 |
0 |
T63 |
32610 |
2 |
0 |
0 |
T64 |
25028 |
1 |
0 |
0 |
T65 |
8398 |
1 |
0 |
0 |
T126 |
22272 |
2 |
0 |
0 |
T127 |
4737 |
1 |
0 |
0 |
T128 |
14549 |
1 |
0 |
0 |
T129 |
5111 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
917942 |
0 |
0 |
T1 |
1861039 |
2038 |
0 |
0 |
T2 |
280905 |
428 |
0 |
0 |
T3 |
0 |
5044 |
0 |
0 |
T4 |
87628 |
122 |
0 |
0 |
T10 |
0 |
152 |
0 |
0 |
T11 |
0 |
7489 |
0 |
0 |
T12 |
0 |
1042 |
0 |
0 |
T13 |
0 |
1156 |
0 |
0 |
T17 |
11900 |
0 |
0 |
0 |
T18 |
7440 |
0 |
0 |
0 |
T19 |
5171 |
0 |
0 |
0 |
T20 |
4287 |
0 |
0 |
0 |
T21 |
11665 |
0 |
0 |
0 |
T22 |
234509 |
480 |
0 |
0 |
T23 |
3374 |
0 |
0 |
0 |
T31 |
0 |
60 |
0 |
0 |
T32 |
0 |
272 |
0 |
0 |
T57 |
6600 |
4 |
0 |
0 |
T58 |
17266 |
2 |
0 |
0 |
T60 |
18646 |
1 |
0 |
0 |
T62 |
7382 |
3 |
0 |
0 |
T63 |
13816 |
2 |
0 |
0 |
T64 |
43376 |
1 |
0 |
0 |
T65 |
15694 |
1 |
0 |
0 |
T126 |
9128 |
2 |
0 |
0 |
T127 |
2678 |
1 |
0 |
0 |
T128 |
14291 |
1 |
0 |
0 |
T129 |
21710 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464922437 |
24212 |
0 |
0 |
T1 |
741536 |
138 |
0 |
0 |
T2 |
181205 |
32 |
0 |
0 |
T3 |
0 |
243 |
0 |
0 |
T4 |
25129 |
6 |
0 |
0 |
T10 |
0 |
12 |
0 |
0 |
T11 |
0 |
348 |
0 |
0 |
T12 |
0 |
82 |
0 |
0 |
T17 |
10052 |
0 |
0 |
0 |
T18 |
2622 |
0 |
0 |
0 |
T19 |
1795 |
0 |
0 |
0 |
T20 |
3185 |
0 |
0 |
0 |
T21 |
8904 |
0 |
0 |
0 |
T22 |
82728 |
16 |
0 |
0 |
T23 |
1216 |
0 |
0 |
0 |
T31 |
0 |
12 |
0 |
0 |
T32 |
0 |
12 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
147706361 |
24212 |
0 |
0 |
T1 |
741157 |
138 |
0 |
0 |
T2 |
94380 |
32 |
0 |
0 |
T3 |
0 |
243 |
0 |
0 |
T4 |
37414 |
6 |
0 |
0 |
T10 |
0 |
12 |
0 |
0 |
T11 |
0 |
348 |
0 |
0 |
T12 |
0 |
82 |
0 |
0 |
T17 |
1570 |
0 |
0 |
0 |
T18 |
2622 |
0 |
0 |
0 |
T19 |
1870 |
0 |
0 |
0 |
T20 |
829 |
0 |
0 |
0 |
T21 |
2318 |
0 |
0 |
0 |
T22 |
96216 |
16 |
0 |
0 |
T23 |
1225 |
0 |
0 |
0 |
T31 |
0 |
12 |
0 |
0 |
T32 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464922437 |
30251 |
0 |
0 |
T1 |
741536 |
138 |
0 |
0 |
T2 |
181205 |
32 |
0 |
0 |
T3 |
0 |
258 |
0 |
0 |
T4 |
25129 |
6 |
0 |
0 |
T10 |
0 |
12 |
0 |
0 |
T11 |
0 |
353 |
0 |
0 |
T12 |
0 |
82 |
0 |
0 |
T17 |
10052 |
0 |
0 |
0 |
T18 |
2622 |
0 |
0 |
0 |
T19 |
1795 |
0 |
0 |
0 |
T20 |
3185 |
0 |
0 |
0 |
T21 |
8904 |
0 |
0 |
0 |
T22 |
82728 |
16 |
0 |
0 |
T23 |
1216 |
0 |
0 |
0 |
T31 |
0 |
24 |
0 |
0 |
T32 |
0 |
12 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
147706361 |
30266 |
0 |
0 |
T1 |
741157 |
138 |
0 |
0 |
T2 |
94380 |
32 |
0 |
0 |
T3 |
0 |
258 |
0 |
0 |
T4 |
37414 |
6 |
0 |
0 |
T10 |
0 |
12 |
0 |
0 |
T11 |
0 |
353 |
0 |
0 |
T12 |
0 |
82 |
0 |
0 |
T17 |
1570 |
0 |
0 |
0 |
T18 |
2622 |
0 |
0 |
0 |
T19 |
1870 |
0 |
0 |
0 |
T20 |
829 |
0 |
0 |
0 |
T21 |
2318 |
0 |
0 |
0 |
T22 |
96216 |
16 |
0 |
0 |
T23 |
1225 |
0 |
0 |
0 |
T31 |
0 |
24 |
0 |
0 |
T32 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
147706361 |
30238 |
0 |
0 |
T1 |
741157 |
138 |
0 |
0 |
T2 |
94380 |
32 |
0 |
0 |
T3 |
0 |
258 |
0 |
0 |
T4 |
37414 |
6 |
0 |
0 |
T10 |
0 |
12 |
0 |
0 |
T11 |
0 |
353 |
0 |
0 |
T12 |
0 |
82 |
0 |
0 |
T17 |
1570 |
0 |
0 |
0 |
T18 |
2622 |
0 |
0 |
0 |
T19 |
1870 |
0 |
0 |
0 |
T20 |
829 |
0 |
0 |
0 |
T21 |
2318 |
0 |
0 |
0 |
T22 |
96216 |
16 |
0 |
0 |
T23 |
1225 |
0 |
0 |
0 |
T31 |
0 |
24 |
0 |
0 |
T32 |
0 |
12 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464922437 |
30253 |
0 |
0 |
T1 |
741536 |
138 |
0 |
0 |
T2 |
181205 |
32 |
0 |
0 |
T3 |
0 |
258 |
0 |
0 |
T4 |
25129 |
6 |
0 |
0 |
T10 |
0 |
12 |
0 |
0 |
T11 |
0 |
353 |
0 |
0 |
T12 |
0 |
82 |
0 |
0 |
T17 |
10052 |
0 |
0 |
0 |
T18 |
2622 |
0 |
0 |
0 |
T19 |
1795 |
0 |
0 |
0 |
T20 |
3185 |
0 |
0 |
0 |
T21 |
8904 |
0 |
0 |
0 |
T22 |
82728 |
16 |
0 |
0 |
T23 |
1216 |
0 |
0 |
0 |
T31 |
0 |
24 |
0 |
0 |
T32 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
231625685 |
24212 |
0 |
0 |
T1 |
370613 |
138 |
0 |
0 |
T2 |
90549 |
32 |
0 |
0 |
T3 |
0 |
243 |
0 |
0 |
T4 |
12504 |
6 |
0 |
0 |
T10 |
0 |
12 |
0 |
0 |
T11 |
0 |
348 |
0 |
0 |
T12 |
0 |
82 |
0 |
0 |
T17 |
5828 |
0 |
0 |
0 |
T18 |
1432 |
0 |
0 |
0 |
T19 |
907 |
0 |
0 |
0 |
T20 |
1701 |
0 |
0 |
0 |
T21 |
4433 |
0 |
0 |
0 |
T22 |
41317 |
16 |
0 |
0 |
T23 |
568 |
0 |
0 |
0 |
T31 |
0 |
12 |
0 |
0 |
T32 |
0 |
12 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
147706361 |
24212 |
0 |
0 |
T1 |
741157 |
138 |
0 |
0 |
T2 |
94380 |
32 |
0 |
0 |
T3 |
0 |
243 |
0 |
0 |
T4 |
37414 |
6 |
0 |
0 |
T10 |
0 |
12 |
0 |
0 |
T11 |
0 |
348 |
0 |
0 |
T12 |
0 |
82 |
0 |
0 |
T17 |
1570 |
0 |
0 |
0 |
T18 |
2622 |
0 |
0 |
0 |
T19 |
1870 |
0 |
0 |
0 |
T20 |
829 |
0 |
0 |
0 |
T21 |
2318 |
0 |
0 |
0 |
T22 |
96216 |
16 |
0 |
0 |
T23 |
1225 |
0 |
0 |
0 |
T31 |
0 |
12 |
0 |
0 |
T32 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
231625685 |
30161 |
0 |
0 |
T1 |
370613 |
138 |
0 |
0 |
T2 |
90549 |
32 |
0 |
0 |
T3 |
0 |
258 |
0 |
0 |
T4 |
12504 |
6 |
0 |
0 |
T10 |
0 |
12 |
0 |
0 |
T11 |
0 |
353 |
0 |
0 |
T12 |
0 |
82 |
0 |
0 |
T17 |
5828 |
0 |
0 |
0 |
T18 |
1432 |
0 |
0 |
0 |
T19 |
907 |
0 |
0 |
0 |
T20 |
1701 |
0 |
0 |
0 |
T21 |
4433 |
0 |
0 |
0 |
T22 |
41317 |
16 |
0 |
0 |
T23 |
568 |
0 |
0 |
0 |
T31 |
0 |
24 |
0 |
0 |
T32 |
0 |
12 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
147706361 |
30191 |
0 |
0 |
T1 |
741157 |
138 |
0 |
0 |
T2 |
94380 |
32 |
0 |
0 |
T3 |
0 |
258 |
0 |
0 |
T4 |
37414 |
6 |
0 |
0 |
T10 |
0 |
12 |
0 |
0 |
T11 |
0 |
353 |
0 |
0 |
T12 |
0 |
82 |
0 |
0 |
T17 |
1570 |
0 |
0 |
0 |
T18 |
2622 |
0 |
0 |
0 |
T19 |
1870 |
0 |
0 |
0 |
T20 |
829 |
0 |
0 |
0 |
T21 |
2318 |
0 |
0 |
0 |
T22 |
96216 |
16 |
0 |
0 |
T23 |
1225 |
0 |
0 |
0 |
T31 |
0 |
24 |
0 |
0 |
T32 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
147706361 |
30154 |
0 |
0 |
T1 |
741157 |
138 |
0 |
0 |
T2 |
94380 |
32 |
0 |
0 |
T3 |
0 |
258 |
0 |
0 |
T4 |
37414 |
6 |
0 |
0 |
T10 |
0 |
12 |
0 |
0 |
T11 |
0 |
353 |
0 |
0 |
T12 |
0 |
82 |
0 |
0 |
T17 |
1570 |
0 |
0 |
0 |
T18 |
2622 |
0 |
0 |
0 |
T19 |
1870 |
0 |
0 |
0 |
T20 |
829 |
0 |
0 |
0 |
T21 |
2318 |
0 |
0 |
0 |
T22 |
96216 |
16 |
0 |
0 |
T23 |
1225 |
0 |
0 |
0 |
T31 |
0 |
24 |
0 |
0 |
T32 |
0 |
12 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
231625685 |
30164 |
0 |
0 |
T1 |
370613 |
138 |
0 |
0 |
T2 |
90549 |
32 |
0 |
0 |
T3 |
0 |
258 |
0 |
0 |
T4 |
12504 |
6 |
0 |
0 |
T10 |
0 |
12 |
0 |
0 |
T11 |
0 |
353 |
0 |
0 |
T12 |
0 |
82 |
0 |
0 |
T17 |
5828 |
0 |
0 |
0 |
T18 |
1432 |
0 |
0 |
0 |
T19 |
907 |
0 |
0 |
0 |
T20 |
1701 |
0 |
0 |
0 |
T21 |
4433 |
0 |
0 |
0 |
T22 |
41317 |
16 |
0 |
0 |
T23 |
568 |
0 |
0 |
0 |
T31 |
0 |
24 |
0 |
0 |
T32 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
115812246 |
24212 |
0 |
0 |
T1 |
185306 |
138 |
0 |
0 |
T2 |
45275 |
32 |
0 |
0 |
T3 |
0 |
243 |
0 |
0 |
T4 |
6252 |
6 |
0 |
0 |
T10 |
0 |
12 |
0 |
0 |
T11 |
0 |
348 |
0 |
0 |
T12 |
0 |
82 |
0 |
0 |
T17 |
2913 |
0 |
0 |
0 |
T18 |
714 |
0 |
0 |
0 |
T19 |
454 |
0 |
0 |
0 |
T20 |
850 |
0 |
0 |
0 |
T21 |
2217 |
0 |
0 |
0 |
T22 |
20659 |
16 |
0 |
0 |
T23 |
284 |
0 |
0 |
0 |
T31 |
0 |
12 |
0 |
0 |
T32 |
0 |
12 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
147706361 |
24212 |
0 |
0 |
T1 |
741157 |
138 |
0 |
0 |
T2 |
94380 |
32 |
0 |
0 |
T3 |
0 |
243 |
0 |
0 |
T4 |
37414 |
6 |
0 |
0 |
T10 |
0 |
12 |
0 |
0 |
T11 |
0 |
348 |
0 |
0 |
T12 |
0 |
82 |
0 |
0 |
T17 |
1570 |
0 |
0 |
0 |
T18 |
2622 |
0 |
0 |
0 |
T19 |
1870 |
0 |
0 |
0 |
T20 |
829 |
0 |
0 |
0 |
T21 |
2318 |
0 |
0 |
0 |
T22 |
96216 |
16 |
0 |
0 |
T23 |
1225 |
0 |
0 |
0 |
T31 |
0 |
12 |
0 |
0 |
T32 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
115812246 |
30257 |
0 |
0 |
T1 |
185306 |
138 |
0 |
0 |
T2 |
45275 |
32 |
0 |
0 |
T3 |
0 |
258 |
0 |
0 |
T4 |
6252 |
6 |
0 |
0 |
T10 |
0 |
12 |
0 |
0 |
T11 |
0 |
353 |
0 |
0 |
T12 |
0 |
82 |
0 |
0 |
T17 |
2913 |
0 |
0 |
0 |
T18 |
714 |
0 |
0 |
0 |
T19 |
454 |
0 |
0 |
0 |
T20 |
850 |
0 |
0 |
0 |
T21 |
2217 |
0 |
0 |
0 |
T22 |
20659 |
16 |
0 |
0 |
T23 |
284 |
0 |
0 |
0 |
T31 |
0 |
24 |
0 |
0 |
T32 |
0 |
12 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
147706361 |
30291 |
0 |
0 |
T1 |
741157 |
138 |
0 |
0 |
T2 |
94380 |
32 |
0 |
0 |
T3 |
0 |
258 |
0 |
0 |
T4 |
37414 |
6 |
0 |
0 |
T10 |
0 |
12 |
0 |
0 |
T11 |
0 |
353 |
0 |
0 |
T12 |
0 |
82 |
0 |
0 |
T17 |
1570 |
0 |
0 |
0 |
T18 |
2622 |
0 |
0 |
0 |
T19 |
1870 |
0 |
0 |
0 |
T20 |
829 |
0 |
0 |
0 |
T21 |
2318 |
0 |
0 |
0 |
T22 |
96216 |
16 |
0 |
0 |
T23 |
1225 |
0 |
0 |
0 |
T31 |
0 |
24 |
0 |
0 |
T32 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
147706361 |
30251 |
0 |
0 |
T1 |
741157 |
138 |
0 |
0 |
T2 |
94380 |
32 |
0 |
0 |
T3 |
0 |
258 |
0 |
0 |
T4 |
37414 |
6 |
0 |
0 |
T10 |
0 |
12 |
0 |
0 |
T11 |
0 |
353 |
0 |
0 |
T12 |
0 |
82 |
0 |
0 |
T17 |
1570 |
0 |
0 |
0 |
T18 |
2622 |
0 |
0 |
0 |
T19 |
1870 |
0 |
0 |
0 |
T20 |
829 |
0 |
0 |
0 |
T21 |
2318 |
0 |
0 |
0 |
T22 |
96216 |
16 |
0 |
0 |
T23 |
1225 |
0 |
0 |
0 |
T31 |
0 |
24 |
0 |
0 |
T32 |
0 |
12 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
115812246 |
30260 |
0 |
0 |
T1 |
185306 |
138 |
0 |
0 |
T2 |
45275 |
32 |
0 |
0 |
T3 |
0 |
258 |
0 |
0 |
T4 |
6252 |
6 |
0 |
0 |
T10 |
0 |
12 |
0 |
0 |
T11 |
0 |
353 |
0 |
0 |
T12 |
0 |
82 |
0 |
0 |
T17 |
2913 |
0 |
0 |
0 |
T18 |
714 |
0 |
0 |
0 |
T19 |
454 |
0 |
0 |
0 |
T20 |
850 |
0 |
0 |
0 |
T21 |
2217 |
0 |
0 |
0 |
T22 |
20659 |
16 |
0 |
0 |
T23 |
284 |
0 |
0 |
0 |
T31 |
0 |
24 |
0 |
0 |
T32 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
495404097 |
24212 |
0 |
0 |
T1 |
808457 |
138 |
0 |
0 |
T2 |
188762 |
32 |
0 |
0 |
T3 |
0 |
243 |
0 |
0 |
T4 |
32176 |
6 |
0 |
0 |
T10 |
0 |
12 |
0 |
0 |
T11 |
0 |
348 |
0 |
0 |
T12 |
0 |
82 |
0 |
0 |
T17 |
10471 |
0 |
0 |
0 |
T18 |
2731 |
0 |
0 |
0 |
T19 |
1870 |
0 |
0 |
0 |
T20 |
3318 |
0 |
0 |
0 |
T21 |
9276 |
0 |
0 |
0 |
T22 |
92178 |
16 |
0 |
0 |
T23 |
1240 |
0 |
0 |
0 |
T31 |
0 |
12 |
0 |
0 |
T32 |
0 |
12 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
147706361 |
24212 |
0 |
0 |
T1 |
741157 |
138 |
0 |
0 |
T2 |
94380 |
32 |
0 |
0 |
T3 |
0 |
243 |
0 |
0 |
T4 |
37414 |
6 |
0 |
0 |
T10 |
0 |
12 |
0 |
0 |
T11 |
0 |
348 |
0 |
0 |
T12 |
0 |
82 |
0 |
0 |
T17 |
1570 |
0 |
0 |
0 |
T18 |
2622 |
0 |
0 |
0 |
T19 |
1870 |
0 |
0 |
0 |
T20 |
829 |
0 |
0 |
0 |
T21 |
2318 |
0 |
0 |
0 |
T22 |
96216 |
16 |
0 |
0 |
T23 |
1225 |
0 |
0 |
0 |
T31 |
0 |
12 |
0 |
0 |
T32 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
495404097 |
30247 |
0 |
0 |
T1 |
808457 |
138 |
0 |
0 |
T2 |
188762 |
32 |
0 |
0 |
T3 |
0 |
258 |
0 |
0 |
T4 |
32176 |
6 |
0 |
0 |
T10 |
0 |
12 |
0 |
0 |
T11 |
0 |
353 |
0 |
0 |
T12 |
0 |
82 |
0 |
0 |
T17 |
10471 |
0 |
0 |
0 |
T18 |
2731 |
0 |
0 |
0 |
T19 |
1870 |
0 |
0 |
0 |
T20 |
3318 |
0 |
0 |
0 |
T21 |
9276 |
0 |
0 |
0 |
T22 |
92178 |
16 |
0 |
0 |
T23 |
1240 |
0 |
0 |
0 |
T31 |
0 |
24 |
0 |
0 |
T32 |
0 |
12 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
147706361 |
30266 |
0 |
0 |
T1 |
741157 |
138 |
0 |
0 |
T2 |
94380 |
32 |
0 |
0 |
T3 |
0 |
258 |
0 |
0 |
T4 |
37414 |
6 |
0 |
0 |
T10 |
0 |
12 |
0 |
0 |
T11 |
0 |
353 |
0 |
0 |
T12 |
0 |
82 |
0 |
0 |
T17 |
1570 |
0 |
0 |
0 |
T18 |
2622 |
0 |
0 |
0 |
T19 |
1870 |
0 |
0 |
0 |
T20 |
829 |
0 |
0 |
0 |
T21 |
2318 |
0 |
0 |
0 |
T22 |
96216 |
16 |
0 |
0 |
T23 |
1225 |
0 |
0 |
0 |
T31 |
0 |
24 |
0 |
0 |
T32 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
147706361 |
30234 |
0 |
0 |
T1 |
741157 |
138 |
0 |
0 |
T2 |
94380 |
32 |
0 |
0 |
T3 |
0 |
258 |
0 |
0 |
T4 |
37414 |
6 |
0 |
0 |
T10 |
0 |
12 |
0 |
0 |
T11 |
0 |
353 |
0 |
0 |
T12 |
0 |
82 |
0 |
0 |
T17 |
1570 |
0 |
0 |
0 |
T18 |
2622 |
0 |
0 |
0 |
T19 |
1870 |
0 |
0 |
0 |
T20 |
829 |
0 |
0 |
0 |
T21 |
2318 |
0 |
0 |
0 |
T22 |
96216 |
16 |
0 |
0 |
T23 |
1225 |
0 |
0 |
0 |
T31 |
0 |
24 |
0 |
0 |
T32 |
0 |
12 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
495404097 |
30253 |
0 |
0 |
T1 |
808457 |
138 |
0 |
0 |
T2 |
188762 |
32 |
0 |
0 |
T3 |
0 |
258 |
0 |
0 |
T4 |
32176 |
6 |
0 |
0 |
T10 |
0 |
12 |
0 |
0 |
T11 |
0 |
353 |
0 |
0 |
T12 |
0 |
82 |
0 |
0 |
T17 |
10471 |
0 |
0 |
0 |
T18 |
2731 |
0 |
0 |
0 |
T19 |
1870 |
0 |
0 |
0 |
T20 |
3318 |
0 |
0 |
0 |
T21 |
9276 |
0 |
0 |
0 |
T22 |
92178 |
16 |
0 |
0 |
T23 |
1240 |
0 |
0 |
0 |
T31 |
0 |
24 |
0 |
0 |
T32 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
237782851 |
23791 |
0 |
0 |
T1 |
390945 |
138 |
0 |
0 |
T2 |
90607 |
32 |
0 |
0 |
T3 |
0 |
243 |
0 |
0 |
T4 |
18325 |
6 |
0 |
0 |
T10 |
0 |
12 |
0 |
0 |
T11 |
0 |
348 |
0 |
0 |
T12 |
0 |
82 |
0 |
0 |
T17 |
5026 |
0 |
0 |
0 |
T18 |
1311 |
0 |
0 |
0 |
T19 |
897 |
0 |
0 |
0 |
T20 |
1592 |
0 |
0 |
0 |
T21 |
4452 |
0 |
0 |
0 |
T22 |
41366 |
16 |
0 |
0 |
T23 |
599 |
0 |
0 |
0 |
T31 |
0 |
6 |
0 |
0 |
T32 |
0 |
12 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
147706361 |
24212 |
0 |
0 |
T1 |
741157 |
138 |
0 |
0 |
T2 |
94380 |
32 |
0 |
0 |
T3 |
0 |
243 |
0 |
0 |
T4 |
37414 |
6 |
0 |
0 |
T10 |
0 |
12 |
0 |
0 |
T11 |
0 |
348 |
0 |
0 |
T12 |
0 |
82 |
0 |
0 |
T17 |
1570 |
0 |
0 |
0 |
T18 |
2622 |
0 |
0 |
0 |
T19 |
1870 |
0 |
0 |
0 |
T20 |
829 |
0 |
0 |
0 |
T21 |
2318 |
0 |
0 |
0 |
T22 |
96216 |
16 |
0 |
0 |
T23 |
1225 |
0 |
0 |
0 |
T31 |
0 |
12 |
0 |
0 |
T32 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
237782851 |
29998 |
0 |
0 |
T1 |
390945 |
138 |
0 |
0 |
T2 |
90607 |
32 |
0 |
0 |
T3 |
0 |
258 |
0 |
0 |
T4 |
18325 |
6 |
0 |
0 |
T10 |
0 |
12 |
0 |
0 |
T11 |
0 |
353 |
0 |
0 |
T12 |
0 |
82 |
0 |
0 |
T17 |
5026 |
0 |
0 |
0 |
T18 |
1311 |
0 |
0 |
0 |
T19 |
897 |
0 |
0 |
0 |
T20 |
1592 |
0 |
0 |
0 |
T21 |
4452 |
0 |
0 |
0 |
T22 |
41366 |
16 |
0 |
0 |
T23 |
599 |
0 |
0 |
0 |
T31 |
0 |
20 |
0 |
0 |
T32 |
0 |
12 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
147706361 |
30177 |
0 |
0 |
T1 |
741157 |
138 |
0 |
0 |
T2 |
94380 |
32 |
0 |
0 |
T3 |
0 |
258 |
0 |
0 |
T4 |
37414 |
6 |
0 |
0 |
T10 |
0 |
12 |
0 |
0 |
T11 |
0 |
353 |
0 |
0 |
T12 |
0 |
82 |
0 |
0 |
T17 |
1570 |
0 |
0 |
0 |
T18 |
2622 |
0 |
0 |
0 |
T19 |
1870 |
0 |
0 |
0 |
T20 |
829 |
0 |
0 |
0 |
T21 |
2318 |
0 |
0 |
0 |
T22 |
96216 |
16 |
0 |
0 |
T23 |
1225 |
0 |
0 |
0 |
T31 |
0 |
24 |
0 |
0 |
T32 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
147706361 |
29878 |
0 |
0 |
T1 |
741157 |
138 |
0 |
0 |
T2 |
94380 |
32 |
0 |
0 |
T3 |
0 |
258 |
0 |
0 |
T4 |
37414 |
6 |
0 |
0 |
T10 |
0 |
12 |
0 |
0 |
T11 |
0 |
353 |
0 |
0 |
T12 |
0 |
82 |
0 |
0 |
T17 |
1570 |
0 |
0 |
0 |
T18 |
2622 |
0 |
0 |
0 |
T19 |
1870 |
0 |
0 |
0 |
T20 |
829 |
0 |
0 |
0 |
T21 |
2318 |
0 |
0 |
0 |
T22 |
96216 |
16 |
0 |
0 |
T23 |
1225 |
0 |
0 |
0 |
T31 |
0 |
20 |
0 |
0 |
T32 |
0 |
12 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
237782851 |
30051 |
0 |
0 |
T1 |
390945 |
138 |
0 |
0 |
T2 |
90607 |
32 |
0 |
0 |
T3 |
0 |
258 |
0 |
0 |
T4 |
18325 |
6 |
0 |
0 |
T10 |
0 |
12 |
0 |
0 |
T11 |
0 |
353 |
0 |
0 |
T12 |
0 |
82 |
0 |
0 |
T17 |
5026 |
0 |
0 |
0 |
T18 |
1311 |
0 |
0 |
0 |
T19 |
897 |
0 |
0 |
0 |
T20 |
1592 |
0 |
0 |
0 |
T21 |
4452 |
0 |
0 |
0 |
T22 |
41366 |
16 |
0 |
0 |
T23 |
599 |
0 |
0 |
0 |
T31 |
0 |
22 |
0 |
0 |
T32 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T57,T60,T59 |
1 | 0 | Covered | T57,T60,T59 |
1 | 1 | Covered | T57,T130,T131 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T57,T60,T59 |
1 | 0 | Covered | T57,T130,T131 |
1 | 1 | Covered | T57,T60,T59 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
147706361 |
40 |
0 |
0 |
T57 |
8521 |
4 |
0 |
0 |
T59 |
4649 |
3 |
0 |
0 |
T60 |
4129 |
1 |
0 |
0 |
T61 |
6561 |
1 |
0 |
0 |
T63 |
16305 |
1 |
0 |
0 |
T64 |
12514 |
1 |
0 |
0 |
T90 |
9706 |
1 |
0 |
0 |
T130 |
4009 |
2 |
0 |
0 |
T132 |
5355 |
1 |
0 |
0 |
T133 |
16352 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464922437 |
40 |
0 |
0 |
T57 |
8179 |
4 |
0 |
0 |
T59 |
17851 |
3 |
0 |
0 |
T60 |
19819 |
1 |
0 |
0 |
T61 |
13122 |
1 |
0 |
0 |
T63 |
15652 |
1 |
0 |
0 |
T64 |
44493 |
1 |
0 |
0 |
T90 |
51765 |
1 |
0 |
0 |
T130 |
20259 |
2 |
0 |
0 |
T132 |
5355 |
1 |
0 |
0 |
T133 |
16352 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T57,T58,T60 |
1 | 0 | Covered | T57,T58,T60 |
1 | 1 | Covered | T58,T61,T130 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T57,T58,T60 |
1 | 0 | Covered | T58,T61,T130 |
1 | 1 | Covered | T57,T58,T60 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
147706361 |
42 |
0 |
0 |
T57 |
8521 |
2 |
0 |
0 |
T58 |
4861 |
3 |
0 |
0 |
T59 |
4649 |
3 |
0 |
0 |
T60 |
4129 |
2 |
0 |
0 |
T61 |
6561 |
2 |
0 |
0 |
T63 |
16305 |
1 |
0 |
0 |
T64 |
12514 |
1 |
0 |
0 |
T128 |
14549 |
1 |
0 |
0 |
T130 |
4009 |
2 |
0 |
0 |
T132 |
5355 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464922437 |
42 |
0 |
0 |
T57 |
8179 |
2 |
0 |
0 |
T58 |
18667 |
3 |
0 |
0 |
T59 |
17851 |
3 |
0 |
0 |
T60 |
19819 |
2 |
0 |
0 |
T61 |
13122 |
2 |
0 |
0 |
T63 |
15652 |
1 |
0 |
0 |
T64 |
44493 |
1 |
0 |
0 |
T128 |
31037 |
1 |
0 |
0 |
T130 |
20259 |
2 |
0 |
0 |
T132 |
5355 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T57,T58,T60 |
1 | 0 | Covered | T57,T58,T60 |
1 | 1 | Covered | T57,T62,T126 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T57,T58,T60 |
1 | 0 | Covered | T57,T62,T126 |
1 | 1 | Covered | T57,T58,T60 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
147706361 |
44 |
0 |
0 |
T57 |
8521 |
4 |
0 |
0 |
T58 |
4861 |
2 |
0 |
0 |
T60 |
4129 |
1 |
0 |
0 |
T62 |
4242 |
3 |
0 |
0 |
T63 |
16305 |
2 |
0 |
0 |
T64 |
12514 |
1 |
0 |
0 |
T65 |
4199 |
1 |
0 |
0 |
T126 |
11136 |
2 |
0 |
0 |
T127 |
4737 |
1 |
0 |
0 |
T128 |
14549 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
231625685 |
44 |
0 |
0 |
T57 |
3300 |
4 |
0 |
0 |
T58 |
8633 |
2 |
0 |
0 |
T60 |
9323 |
1 |
0 |
0 |
T62 |
3691 |
3 |
0 |
0 |
T63 |
6908 |
2 |
0 |
0 |
T64 |
21688 |
1 |
0 |
0 |
T65 |
7847 |
1 |
0 |
0 |
T126 |
4564 |
2 |
0 |
0 |
T127 |
2678 |
1 |
0 |
0 |
T128 |
14291 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T57,T58,T60 |
1 | 0 | Covered | T57,T58,T60 |
1 | 1 | Covered | T57,T65,T62 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T57,T58,T60 |
1 | 0 | Covered | T57,T65,T62 |
1 | 1 | Covered | T57,T58,T60 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
147706361 |
37 |
0 |
0 |
T57 |
8521 |
4 |
0 |
0 |
T58 |
4861 |
1 |
0 |
0 |
T60 |
4129 |
1 |
0 |
0 |
T62 |
4242 |
2 |
0 |
0 |
T63 |
16305 |
2 |
0 |
0 |
T64 |
12514 |
1 |
0 |
0 |
T65 |
4199 |
2 |
0 |
0 |
T126 |
11136 |
1 |
0 |
0 |
T129 |
5111 |
1 |
0 |
0 |
T134 |
4070 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
231625685 |
37 |
0 |
0 |
T57 |
3300 |
4 |
0 |
0 |
T58 |
8633 |
1 |
0 |
0 |
T60 |
9323 |
1 |
0 |
0 |
T62 |
3691 |
2 |
0 |
0 |
T63 |
6908 |
2 |
0 |
0 |
T64 |
21688 |
1 |
0 |
0 |
T65 |
7847 |
2 |
0 |
0 |
T126 |
4564 |
1 |
0 |
0 |
T129 |
21710 |
1 |
0 |
0 |
T134 |
14339 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T57,T59,T61 |
1 | 0 | Covered | T57,T59,T61 |
1 | 1 | Covered | T57,T61,T135 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T57,T59,T61 |
1 | 0 | Covered | T57,T61,T135 |
1 | 1 | Covered | T57,T59,T61 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
147706361 |
40 |
0 |
0 |
T57 |
8521 |
3 |
0 |
0 |
T59 |
4649 |
3 |
0 |
0 |
T61 |
6561 |
4 |
0 |
0 |
T62 |
4242 |
1 |
0 |
0 |
T65 |
4199 |
1 |
0 |
0 |
T90 |
9706 |
1 |
0 |
0 |
T129 |
5111 |
1 |
0 |
0 |
T133 |
16352 |
2 |
0 |
0 |
T134 |
4070 |
2 |
0 |
0 |
T135 |
13021 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
115812246 |
40 |
0 |
0 |
T57 |
1650 |
3 |
0 |
0 |
T59 |
4084 |
3 |
0 |
0 |
T61 |
2821 |
4 |
0 |
0 |
T62 |
1845 |
1 |
0 |
0 |
T65 |
3925 |
1 |
0 |
0 |
T90 |
12630 |
1 |
0 |
0 |
T129 |
10855 |
1 |
0 |
0 |
T133 |
3604 |
2 |
0 |
0 |
T134 |
7167 |
2 |
0 |
0 |
T135 |
2726 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T57,T59,T61 |
1 | 0 | Covered | T57,T59,T61 |
1 | 1 | Covered | T57,T59,T61 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T57,T59,T61 |
1 | 0 | Covered | T57,T59,T61 |
1 | 1 | Covered | T57,T59,T61 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
147706361 |
39 |
0 |
0 |
T57 |
8521 |
2 |
0 |
0 |
T59 |
4649 |
3 |
0 |
0 |
T61 |
6561 |
5 |
0 |
0 |
T62 |
4242 |
1 |
0 |
0 |
T64 |
12514 |
1 |
0 |
0 |
T65 |
4199 |
1 |
0 |
0 |
T90 |
9706 |
1 |
0 |
0 |
T133 |
16352 |
1 |
0 |
0 |
T134 |
4070 |
1 |
0 |
0 |
T135 |
13021 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
115812246 |
39 |
0 |
0 |
T57 |
1650 |
2 |
0 |
0 |
T59 |
4084 |
3 |
0 |
0 |
T61 |
2821 |
5 |
0 |
0 |
T62 |
1845 |
1 |
0 |
0 |
T64 |
10845 |
1 |
0 |
0 |
T65 |
3925 |
1 |
0 |
0 |
T90 |
12630 |
1 |
0 |
0 |
T133 |
3604 |
1 |
0 |
0 |
T134 |
7167 |
1 |
0 |
0 |
T135 |
2726 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T57,T58,T59 |
1 | 0 | Covered | T57,T58,T59 |
1 | 1 | Covered | T57,T134 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T57,T58,T59 |
1 | 0 | Covered | T57,T134 |
1 | 1 | Covered | T57,T58,T59 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
147706361 |
29 |
0 |
0 |
T57 |
8521 |
6 |
0 |
0 |
T58 |
4861 |
1 |
0 |
0 |
T59 |
4649 |
1 |
0 |
0 |
T61 |
6561 |
1 |
0 |
0 |
T64 |
12514 |
2 |
0 |
0 |
T126 |
11136 |
2 |
0 |
0 |
T127 |
4737 |
1 |
0 |
0 |
T133 |
16352 |
1 |
0 |
0 |
T134 |
4070 |
2 |
0 |
0 |
T136 |
10612 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
495404097 |
29 |
0 |
0 |
T57 |
8521 |
6 |
0 |
0 |
T58 |
19446 |
1 |
0 |
0 |
T59 |
18596 |
1 |
0 |
0 |
T61 |
13670 |
1 |
0 |
0 |
T64 |
46349 |
2 |
0 |
0 |
T126 |
11722 |
2 |
0 |
0 |
T127 |
6401 |
1 |
0 |
0 |
T133 |
17034 |
1 |
0 |
0 |
T134 |
31306 |
2 |
0 |
0 |
T136 |
40817 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T57,T58,T59 |
1 | 0 | Covered | T57,T58,T59 |
1 | 1 | Covered | T57,T59,T126 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T57,T58,T59 |
1 | 0 | Covered | T57,T59,T126 |
1 | 1 | Covered | T57,T58,T59 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
147706361 |
35 |
0 |
0 |
T57 |
8521 |
5 |
0 |
0 |
T58 |
4861 |
1 |
0 |
0 |
T59 |
4649 |
3 |
0 |
0 |
T61 |
6561 |
1 |
0 |
0 |
T63 |
16305 |
1 |
0 |
0 |
T65 |
4199 |
1 |
0 |
0 |
T126 |
11136 |
2 |
0 |
0 |
T127 |
4737 |
1 |
0 |
0 |
T133 |
16352 |
1 |
0 |
0 |
T134 |
4070 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
495404097 |
35 |
0 |
0 |
T57 |
8521 |
5 |
0 |
0 |
T58 |
19446 |
1 |
0 |
0 |
T59 |
18596 |
3 |
0 |
0 |
T61 |
13670 |
1 |
0 |
0 |
T63 |
16305 |
1 |
0 |
0 |
T65 |
17499 |
1 |
0 |
0 |
T126 |
11722 |
2 |
0 |
0 |
T127 |
6401 |
1 |
0 |
0 |
T133 |
17034 |
1 |
0 |
0 |
T134 |
31306 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T58,T59,T64 |
1 | 0 | Covered | T58,T59,T64 |
1 | 1 | Covered | T62,T137,T138 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T58,T59,T64 |
1 | 0 | Covered | T62,T137,T138 |
1 | 1 | Covered | T58,T59,T64 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
147706361 |
34 |
0 |
0 |
T58 |
4861 |
3 |
0 |
0 |
T59 |
4649 |
1 |
0 |
0 |
T62 |
4242 |
2 |
0 |
0 |
T64 |
12514 |
1 |
0 |
0 |
T65 |
4199 |
1 |
0 |
0 |
T126 |
11136 |
2 |
0 |
0 |
T132 |
5355 |
2 |
0 |
0 |
T133 |
16352 |
1 |
0 |
0 |
T135 |
13021 |
1 |
0 |
0 |
T139 |
6563 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
237782851 |
34 |
0 |
0 |
T58 |
9334 |
3 |
0 |
0 |
T59 |
8926 |
1 |
0 |
0 |
T62 |
4242 |
2 |
0 |
0 |
T64 |
22247 |
1 |
0 |
0 |
T65 |
8399 |
1 |
0 |
0 |
T126 |
5627 |
2 |
0 |
0 |
T132 |
2677 |
2 |
0 |
0 |
T133 |
8176 |
1 |
0 |
0 |
T135 |
6511 |
1 |
0 |
0 |
T139 |
6300 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T58,T59,T64 |
1 | 0 | Covered | T58,T59,T64 |
1 | 1 | Covered | T58,T65,T137 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T58,T59,T64 |
1 | 0 | Covered | T58,T65,T137 |
1 | 1 | Covered | T58,T59,T64 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
147706361 |
31 |
0 |
0 |
T58 |
4861 |
2 |
0 |
0 |
T59 |
4649 |
1 |
0 |
0 |
T62 |
4242 |
1 |
0 |
0 |
T63 |
16305 |
1 |
0 |
0 |
T64 |
12514 |
1 |
0 |
0 |
T65 |
4199 |
2 |
0 |
0 |
T126 |
11136 |
2 |
0 |
0 |
T130 |
4009 |
1 |
0 |
0 |
T133 |
16352 |
2 |
0 |
0 |
T135 |
13021 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
237782851 |
31 |
0 |
0 |
T58 |
9334 |
2 |
0 |
0 |
T59 |
8926 |
1 |
0 |
0 |
T62 |
4242 |
1 |
0 |
0 |
T63 |
7826 |
1 |
0 |
0 |
T64 |
22247 |
1 |
0 |
0 |
T65 |
8399 |
2 |
0 |
0 |
T126 |
5627 |
2 |
0 |
0 |
T130 |
10130 |
1 |
0 |
0 |
T133 |
8176 |
2 |
0 |
0 |
T135 |
6511 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462284330 |
93096 |
0 |
0 |
T1 |
741536 |
388 |
0 |
0 |
T2 |
181205 |
83 |
0 |
0 |
T3 |
0 |
994 |
0 |
0 |
T4 |
25129 |
23 |
0 |
0 |
T10 |
0 |
29 |
0 |
0 |
T11 |
0 |
1532 |
0 |
0 |
T12 |
0 |
199 |
0 |
0 |
T13 |
0 |
256 |
0 |
0 |
T17 |
10052 |
0 |
0 |
0 |
T18 |
2622 |
0 |
0 |
0 |
T19 |
1795 |
0 |
0 |
0 |
T20 |
3185 |
0 |
0 |
0 |
T21 |
8904 |
0 |
0 |
0 |
T22 |
82728 |
105 |
0 |
0 |
T23 |
1216 |
0 |
0 |
0 |
T32 |
0 |
47 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
15566519 |
91865 |
0 |
0 |
T1 |
2010 |
388 |
0 |
0 |
T2 |
399 |
83 |
0 |
0 |
T3 |
0 |
995 |
0 |
0 |
T4 |
71 |
23 |
0 |
0 |
T10 |
0 |
29 |
0 |
0 |
T11 |
0 |
1532 |
0 |
0 |
T12 |
0 |
199 |
0 |
0 |
T13 |
0 |
256 |
0 |
0 |
T17 |
733 |
0 |
0 |
0 |
T18 |
191 |
0 |
0 |
0 |
T19 |
131 |
0 |
0 |
0 |
T20 |
232 |
0 |
0 |
0 |
T21 |
649 |
0 |
0 |
0 |
T22 |
187 |
105 |
0 |
0 |
T23 |
89 |
0 |
0 |
0 |
T32 |
0 |
47 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
230354170 |
92481 |
0 |
0 |
T1 |
370613 |
388 |
0 |
0 |
T2 |
90549 |
83 |
0 |
0 |
T3 |
0 |
994 |
0 |
0 |
T4 |
12504 |
23 |
0 |
0 |
T10 |
0 |
29 |
0 |
0 |
T11 |
0 |
1528 |
0 |
0 |
T12 |
0 |
199 |
0 |
0 |
T13 |
0 |
256 |
0 |
0 |
T17 |
5828 |
0 |
0 |
0 |
T18 |
1432 |
0 |
0 |
0 |
T19 |
907 |
0 |
0 |
0 |
T20 |
1701 |
0 |
0 |
0 |
T21 |
4433 |
0 |
0 |
0 |
T22 |
41317 |
105 |
0 |
0 |
T23 |
568 |
0 |
0 |
0 |
T32 |
0 |
47 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
15566519 |
91257 |
0 |
0 |
T1 |
2010 |
388 |
0 |
0 |
T2 |
399 |
83 |
0 |
0 |
T3 |
0 |
995 |
0 |
0 |
T4 |
71 |
23 |
0 |
0 |
T10 |
0 |
29 |
0 |
0 |
T11 |
0 |
1528 |
0 |
0 |
T12 |
0 |
199 |
0 |
0 |
T13 |
0 |
256 |
0 |
0 |
T17 |
733 |
0 |
0 |
0 |
T18 |
191 |
0 |
0 |
0 |
T19 |
131 |
0 |
0 |
0 |
T20 |
232 |
0 |
0 |
0 |
T21 |
649 |
0 |
0 |
0 |
T22 |
187 |
105 |
0 |
0 |
T23 |
89 |
0 |
0 |
0 |
T32 |
0 |
47 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
115176481 |
91098 |
0 |
0 |
T1 |
185306 |
388 |
0 |
0 |
T2 |
45275 |
83 |
0 |
0 |
T3 |
0 |
994 |
0 |
0 |
T4 |
6252 |
23 |
0 |
0 |
T10 |
0 |
29 |
0 |
0 |
T11 |
0 |
1518 |
0 |
0 |
T12 |
0 |
199 |
0 |
0 |
T13 |
0 |
256 |
0 |
0 |
T17 |
2913 |
0 |
0 |
0 |
T18 |
714 |
0 |
0 |
0 |
T19 |
454 |
0 |
0 |
0 |
T20 |
850 |
0 |
0 |
0 |
T21 |
2217 |
0 |
0 |
0 |
T22 |
20659 |
105 |
0 |
0 |
T23 |
284 |
0 |
0 |
0 |
T32 |
0 |
47 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
15566519 |
89883 |
0 |
0 |
T1 |
2010 |
388 |
0 |
0 |
T2 |
399 |
83 |
0 |
0 |
T3 |
0 |
995 |
0 |
0 |
T4 |
71 |
23 |
0 |
0 |
T10 |
0 |
29 |
0 |
0 |
T11 |
0 |
1518 |
0 |
0 |
T12 |
0 |
199 |
0 |
0 |
T13 |
0 |
256 |
0 |
0 |
T17 |
733 |
0 |
0 |
0 |
T18 |
191 |
0 |
0 |
0 |
T19 |
131 |
0 |
0 |
0 |
T20 |
232 |
0 |
0 |
0 |
T21 |
649 |
0 |
0 |
0 |
T22 |
187 |
105 |
0 |
0 |
T23 |
89 |
0 |
0 |
0 |
T32 |
0 |
47 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
492655958 |
111806 |
0 |
0 |
T1 |
808457 |
460 |
0 |
0 |
T2 |
188762 |
83 |
0 |
0 |
T3 |
0 |
1300 |
0 |
0 |
T4 |
32176 |
35 |
0 |
0 |
T10 |
0 |
29 |
0 |
0 |
T11 |
0 |
1857 |
0 |
0 |
T12 |
0 |
199 |
0 |
0 |
T13 |
0 |
388 |
0 |
0 |
T17 |
10471 |
0 |
0 |
0 |
T18 |
2731 |
0 |
0 |
0 |
T19 |
1870 |
0 |
0 |
0 |
T20 |
3318 |
0 |
0 |
0 |
T21 |
9276 |
0 |
0 |
0 |
T22 |
92178 |
117 |
0 |
0 |
T23 |
1240 |
0 |
0 |
0 |
T32 |
0 |
95 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
15777280 |
111217 |
0 |
0 |
T1 |
2082 |
460 |
0 |
0 |
T2 |
399 |
83 |
0 |
0 |
T3 |
0 |
1300 |
0 |
0 |
T4 |
83 |
35 |
0 |
0 |
T10 |
0 |
29 |
0 |
0 |
T11 |
0 |
1857 |
0 |
0 |
T12 |
0 |
199 |
0 |
0 |
T13 |
0 |
388 |
0 |
0 |
T17 |
733 |
0 |
0 |
0 |
T18 |
191 |
0 |
0 |
0 |
T19 |
131 |
0 |
0 |
0 |
T20 |
232 |
0 |
0 |
0 |
T21 |
649 |
0 |
0 |
0 |
T22 |
199 |
117 |
0 |
0 |
T23 |
89 |
0 |
0 |
0 |
T32 |
0 |
95 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
236463771 |
110448 |
0 |
0 |
T1 |
390945 |
472 |
0 |
0 |
T2 |
90607 |
83 |
0 |
0 |
T3 |
0 |
1261 |
0 |
0 |
T4 |
18325 |
47 |
0 |
0 |
T10 |
0 |
29 |
0 |
0 |
T11 |
0 |
1816 |
0 |
0 |
T12 |
0 |
199 |
0 |
0 |
T13 |
0 |
388 |
0 |
0 |
T17 |
5026 |
0 |
0 |
0 |
T18 |
1311 |
0 |
0 |
0 |
T19 |
897 |
0 |
0 |
0 |
T20 |
1592 |
0 |
0 |
0 |
T21 |
4452 |
0 |
0 |
0 |
T22 |
41366 |
105 |
0 |
0 |
T23 |
599 |
0 |
0 |
0 |
T32 |
0 |
95 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
15746961 |
110117 |
0 |
0 |
T1 |
2094 |
472 |
0 |
0 |
T2 |
399 |
83 |
0 |
0 |
T3 |
0 |
1261 |
0 |
0 |
T4 |
95 |
47 |
0 |
0 |
T10 |
0 |
29 |
0 |
0 |
T11 |
0 |
1816 |
0 |
0 |
T12 |
0 |
199 |
0 |
0 |
T13 |
0 |
388 |
0 |
0 |
T17 |
733 |
0 |
0 |
0 |
T18 |
191 |
0 |
0 |
0 |
T19 |
131 |
0 |
0 |
0 |
T20 |
232 |
0 |
0 |
0 |
T21 |
649 |
0 |
0 |
0 |
T22 |
187 |
105 |
0 |
0 |
T23 |
89 |
0 |
0 |
0 |
T32 |
0 |
95 |
0 |
0 |