Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	147706361	4779423	0	0
clk_enables_rd_A	147706361	38966	0	0
clk_hints_rd_A	147706361	34256	0	0
extclk_ctrl_rd_A	147706361	41808	0	0
extclk_ctrl_regwen_rd_A	147706361	32546	0	0
jitter_enable_rd_A	147706361	48200	0	0
jitter_regwen_rd_A	147706361	37237	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147706361	4779423	0	0
T3	289870	101150	0	0
T11	0	111444	0	0
T31	43063	0	0	0
T32	37247	0	0	0
T34	1113	0	0	0
T41	0	120678	0	0
T66	0	24602	0	0
T67	0	87046	0	0
T68	0	138397	0	0
T69	0	209661	0	0
T70	0	78000	0	0
T71	0	66745	0	0
T72	0	169016	0	0
T73	1503	0	0	0
T74	2828	0	0	0
T75	1771	0	0	0
T76	2438	0	0	0
T77	2260	0	0	0
T78	3041	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147706361	38966	0	0
T10	48119	0	0	0
T11	321151	0	0	0
T12	0	8	0	0
T15	0	7	0	0
T32	37247	0	0	0
T34	1113	0	0	0
T40	1357	0	0	0
T67	0	3474	0	0
T77	2260	10	0	0
T78	3041	0	0	0
T112	1574	0	0	0
T124	1861	0	0	0
T140	0	6	0	0
T141	0	15	0	0
T142	0	1121	0	0
T143	0	1	0	0
T144	0	5	0	0
T145	0	5861	0	0
T146	1613	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147706361	34256	0	0
T10	48119	0	0	0
T11	321151	0	0	0
T12	0	21	0	0
T15	0	7	0	0
T32	37247	0	0	0
T34	1113	0	0	0
T40	1357	0	0	0
T67	0	3382	0	0
T77	2260	9	0	0
T78	3041	0	0	0
T112	1574	0	0	0
T124	1861	0	0	0
T140	0	6	0	0
T141	0	7	0	0
T142	0	776	0	0
T143	0	9	0	0
T145	0	4844	0	0
T146	1613	0	0	0
T147	0	8	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147706361	41808	0	0
T10	48119	0	0	0
T11	321151	0	0	0
T12	0	155	0	0
T15	0	78	0	0
T31	43063	0	0	0
T32	37247	0	0	0
T34	1113	0	0	0
T40	1357	0	0	0
T76	2438	17	0	0
T77	2260	0	0	0
T78	3041	0	0	0
T99	0	60	0	0
T101	0	17	0	0
T112	1574	9	0	0
T124	0	16	0	0
T148	0	59	0	0
T149	0	28	0	0
T150	0	26	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147706361	32546	0	0
T67	304703	2958	0	0
T68	395461	0	0	0
T102	2839	0	0	0
T142	0	959	0	0
T145	0	5275	0	0
T151	0	14	0	0
T152	0	26	0	0
T153	0	29	0	0
T154	0	44	0	0
T155	0	10	0	0
T156	0	966	0	0
T157	0	45	0	0
T158	1376	0	0	0
T159	2071	0	0	0
T160	24859	0	0	0
T161	2496	0	0	0
T162	1467	0	0	0
T163	1426	0	0	0
T164	951	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147706361	48200	0	0
T10	48119	0	0	0
T11	321151	0	0	0
T12	0	319	0	0
T15	0	113	0	0
T32	37247	0	0	0
T34	1113	0	0	0
T40	1357	0	0	0
T67	0	4852	0	0
T77	2260	108	0	0
T78	3041	0	0	0
T112	1574	0	0	0
T124	1861	0	0	0
T140	0	116	0	0
T141	0	443	0	0
T142	0	1436	0	0
T143	0	56	0	0
T144	0	132	0	0
T146	1613	0	0	0
T165	0	67	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147706361	37237	0	0
T67	304703	3501	0	0
T68	395461	0	0	0
T102	2839	0	0	0
T142	0	924	0	0
T145	0	5943	0	0
T156	0	1066	0	0
T158	1376	0	0	0
T159	2071	0	0	0
T160	24859	0	0	0
T161	2496	0	0	0
T162	1467	0	0	0
T163	1426	0	0	0
T164	951	0	0	0
T166	0	2460	0	0
T167	0	2072	0	0
T168	0	2251	0	0
T169	0	1806	0	0
T170	0	1140	0	0
T171	0	662	0	0