SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.clkmgr_div2_sva_if | 100.00 | 100.00 | 100.00 | 100.00 | |||
tb.dut.clkmgr_div4_sva_if | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.65 | 100.00 | 93.24 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.65 | 100.00 | 93.24 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T24,T27,T17 |
1 | 1 | Covered | T7,T24,T27 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 462284794 | 4158 | 0 | 0 |
g_div2.Div2Whole_A | 462284794 | 4983 | 0 | 0 |
g_div4.Div4Stepped_A | 230354616 | 4057 | 0 | 0 |
g_div4.Div4Whole_A | 230354616 | 4648 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 462284794 | 4158 | 0 | 0 |
T1 | 741536 | 0 | 0 | 0 |
T2 | 181205 | 0 | 0 | 0 |
T3 | 0 | 16 | 0 | 0 |
T7 | 1580 | 1 | 0 | 0 |
T17 | 10052 | 12 | 0 | 0 |
T18 | 2623 | 9 | 0 | 0 |
T19 | 1796 | 1 | 0 | 0 |
T20 | 0 | 2 | 0 | 0 |
T24 | 2078 | 4 | 0 | 0 |
T25 | 6442 | 0 | 0 | 0 |
T26 | 1444 | 0 | 0 | 0 |
T27 | 10426 | 12 | 0 | 0 |
T76 | 0 | 7 | 0 | 0 |
T122 | 0 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 462284794 | 4983 | 0 | 0 |
T1 | 741536 | 0 | 0 | 0 |
T2 | 181205 | 0 | 0 | 0 |
T3 | 0 | 23 | 0 | 0 |
T7 | 1580 | 1 | 0 | 0 |
T17 | 10052 | 12 | 0 | 0 |
T18 | 2623 | 15 | 0 | 0 |
T19 | 1796 | 4 | 0 | 0 |
T20 | 0 | 3 | 0 | 0 |
T24 | 2078 | 7 | 0 | 0 |
T25 | 6442 | 0 | 0 | 0 |
T26 | 1444 | 0 | 0 | 0 |
T27 | 10426 | 13 | 0 | 0 |
T76 | 0 | 10 | 0 | 0 |
T122 | 0 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 230354616 | 4057 | 0 | 0 |
T1 | 370613 | 0 | 0 | 0 |
T2 | 90550 | 0 | 0 | 0 |
T3 | 0 | 16 | 0 | 0 |
T7 | 788 | 1 | 0 | 0 |
T11 | 0 | 38 | 0 | 0 |
T17 | 5829 | 12 | 0 | 0 |
T18 | 1432 | 8 | 0 | 0 |
T19 | 907 | 0 | 0 | 0 |
T20 | 0 | 2 | 0 | 0 |
T24 | 1086 | 4 | 0 | 0 |
T25 | 3175 | 0 | 0 | 0 |
T26 | 696 | 0 | 0 | 0 |
T27 | 5887 | 12 | 0 | 0 |
T76 | 0 | 7 | 0 | 0 |
T122 | 0 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 230354616 | 4648 | 0 | 0 |
T1 | 370613 | 0 | 0 | 0 |
T2 | 90550 | 0 | 0 | 0 |
T3 | 0 | 19 | 0 | 0 |
T7 | 788 | 1 | 0 | 0 |
T17 | 5829 | 11 | 0 | 0 |
T18 | 1432 | 13 | 0 | 0 |
T19 | 907 | 4 | 0 | 0 |
T20 | 0 | 1 | 0 | 0 |
T24 | 1086 | 7 | 0 | 0 |
T25 | 3175 | 0 | 0 | 0 |
T26 | 696 | 0 | 0 | 0 |
T27 | 5887 | 12 | 0 | 0 |
T76 | 0 | 8 | 0 | 0 |
T122 | 0 | 2 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T24,T27,T17 |
1 | 1 | Covered | T7,T24,T27 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 462284794 | 4158 | 0 | 0 |
g_div2.Div2Whole_A | 462284794 | 4983 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 462284794 | 4158 | 0 | 0 |
T1 | 741536 | 0 | 0 | 0 |
T2 | 181205 | 0 | 0 | 0 |
T3 | 0 | 16 | 0 | 0 |
T7 | 1580 | 1 | 0 | 0 |
T17 | 10052 | 12 | 0 | 0 |
T18 | 2623 | 9 | 0 | 0 |
T19 | 1796 | 1 | 0 | 0 |
T20 | 0 | 2 | 0 | 0 |
T24 | 2078 | 4 | 0 | 0 |
T25 | 6442 | 0 | 0 | 0 |
T26 | 1444 | 0 | 0 | 0 |
T27 | 10426 | 12 | 0 | 0 |
T76 | 0 | 7 | 0 | 0 |
T122 | 0 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 462284794 | 4983 | 0 | 0 |
T1 | 741536 | 0 | 0 | 0 |
T2 | 181205 | 0 | 0 | 0 |
T3 | 0 | 23 | 0 | 0 |
T7 | 1580 | 1 | 0 | 0 |
T17 | 10052 | 12 | 0 | 0 |
T18 | 2623 | 15 | 0 | 0 |
T19 | 1796 | 4 | 0 | 0 |
T20 | 0 | 3 | 0 | 0 |
T24 | 2078 | 7 | 0 | 0 |
T25 | 6442 | 0 | 0 | 0 |
T26 | 1444 | 0 | 0 | 0 |
T27 | 10426 | 13 | 0 | 0 |
T76 | 0 | 10 | 0 | 0 |
T122 | 0 | 2 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T24,T27,T17 |
1 | 1 | Covered | T7,T24,T27 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div4.Div4Stepped_A | 230354616 | 4057 | 0 | 0 |
g_div4.Div4Whole_A | 230354616 | 4648 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 230354616 | 4057 | 0 | 0 |
T1 | 370613 | 0 | 0 | 0 |
T2 | 90550 | 0 | 0 | 0 |
T3 | 0 | 16 | 0 | 0 |
T7 | 788 | 1 | 0 | 0 |
T11 | 0 | 38 | 0 | 0 |
T17 | 5829 | 12 | 0 | 0 |
T18 | 1432 | 8 | 0 | 0 |
T19 | 907 | 0 | 0 | 0 |
T20 | 0 | 2 | 0 | 0 |
T24 | 1086 | 4 | 0 | 0 |
T25 | 3175 | 0 | 0 | 0 |
T26 | 696 | 0 | 0 | 0 |
T27 | 5887 | 12 | 0 | 0 |
T76 | 0 | 7 | 0 | 0 |
T122 | 0 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 230354616 | 4648 | 0 | 0 |
T1 | 370613 | 0 | 0 | 0 |
T2 | 90550 | 0 | 0 | 0 |
T3 | 0 | 19 | 0 | 0 |
T7 | 788 | 1 | 0 | 0 |
T17 | 5829 | 11 | 0 | 0 |
T18 | 1432 | 13 | 0 | 0 |
T19 | 907 | 4 | 0 | 0 |
T20 | 0 | 1 | 0 | 0 |
T24 | 1086 | 7 | 0 | 0 |
T25 | 3175 | 0 | 0 | 0 |
T26 | 696 | 0 | 0 | 0 |
T27 | 5887 | 12 | 0 | 0 |
T76 | 0 | 8 | 0 | 0 |
T122 | 0 | 2 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |