Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	440301513	418	0	0
StatusRise_A	440301513	418	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440301513	418	0	0
T3	869610	0	0	0
T23	3675	4	0	0
T39	3267	6	0	0
T40	0	8	0	0
T42	4869	0	0	0
T73	4509	0	0	0
T74	8484	0	0	0
T75	5313	0	0	0
T76	7314	0	0	0
T79	4329	0	0	0
T122	3438	0	0	0
T172	0	11	0	0
T173	0	14	0	0
T174	0	6	0	0
T175	0	1	0	0
T176	0	6	0	0
T177	0	11	0	0
T178	0	9	0	0
T179	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440301513	418	0	0
T3	869610	0	0	0
T23	3675	4	0	0
T39	3267	6	0	0
T40	0	8	0	0
T42	4869	0	0	0
T73	4509	0	0	0
T74	8484	0	0	0
T75	5313	0	0	0
T76	7314	0	0	0
T79	4329	0	0	0
T122	3438	0	0	0
T172	0	11	0	0
T173	0	14	0	0
T174	0	6	0	0
T175	0	1	0	0
T176	0	6	0	0
T177	0	11	0	0
T178	0	9	0	0
T179	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	146767171	144	0	0
StatusRise_A	146767171	144	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146767171	144	0	0
T3	289870	0	0	0
T23	1225	1	0	0
T39	1089	2	0	0
T40	0	2	0	0
T42	1623	0	0	0
T73	1503	0	0	0
T74	2828	0	0	0
T75	1771	0	0	0
T76	2438	0	0	0
T79	1443	0	0	0
T122	1146	0	0	0
T172	0	3	0	0
T173	0	5	0	0
T174	0	2	0	0
T176	0	1	0	0
T177	0	4	0	0
T178	0	2	0	0
T179	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146767171	144	0	0
T3	289870	0	0	0
T23	1225	1	0	0
T39	1089	2	0	0
T40	0	2	0	0
T42	1623	0	0	0
T73	1503	0	0	0
T74	2828	0	0	0
T75	1771	0	0	0
T76	2438	0	0	0
T79	1443	0	0	0
T122	1146	0	0	0
T172	0	3	0	0
T173	0	5	0	0
T174	0	2	0	0
T176	0	1	0	0
T177	0	4	0	0
T178	0	2	0	0
T179	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	146767171	137	0	0
StatusRise_A	146767171	137	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146767171	137	0	0
T3	289870	0	0	0
T23	1225	1	0	0
T39	1089	2	0	0
T40	0	4	0	0
T42	1623	0	0	0
T73	1503	0	0	0
T74	2828	0	0	0
T75	1771	0	0	0
T76	2438	0	0	0
T79	1443	0	0	0
T122	1146	0	0	0
T172	0	3	0	0
T173	0	4	0	0
T174	0	2	0	0
T175	0	1	0	0
T176	0	2	0	0
T177	0	3	0	0
T178	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146767171	137	0	0
T3	289870	0	0	0
T23	1225	1	0	0
T39	1089	2	0	0
T40	0	4	0	0
T42	1623	0	0	0
T73	1503	0	0	0
T74	2828	0	0	0
T75	1771	0	0	0
T76	2438	0	0	0
T79	1443	0	0	0
T122	1146	0	0	0
T172	0	3	0	0
T173	0	4	0	0
T174	0	2	0	0
T175	0	1	0	0
T176	0	2	0	0
T177	0	3	0	0
T178	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	146767171	137	0	0
StatusRise_A	146767171	137	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146767171	137	0	0
T3	289870	0	0	0
T23	1225	2	0	0
T39	1089	2	0	0
T40	0	2	0	0
T42	1623	0	0	0
T73	1503	0	0	0
T74	2828	0	0	0
T75	1771	0	0	0
T76	2438	0	0	0
T79	1443	0	0	0
T122	1146	0	0	0
T172	0	5	0	0
T173	0	5	0	0
T174	0	2	0	0
T176	0	3	0	0
T177	0	4	0	0
T178	0	2	0	0
T179	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146767171	137	0	0
T3	289870	0	0	0
T23	1225	2	0	0
T39	1089	2	0	0
T40	0	2	0	0
T42	1623	0	0	0
T73	1503	0	0	0
T74	2828	0	0	0
T75	1771	0	0	0
T76	2438	0	0	0
T79	1443	0	0	0
T122	1146	0	0	0
T172	0	5	0	0
T173	0	5	0	0
T174	0	2	0	0
T176	0	3	0	0
T177	0	4	0	0
T178	0	2	0	0
T179	0	2	0	0