Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T39
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	48377	0	0
CgEnOn_A	2147483647	38998	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48377	0	0
T1	4922228	74	0	0
T2	1162684	3	0	0
T3	3001854	0	0	0
T5	12281	7	0	0
T6	35731	3	0	0
T7	10128	3	0	0
T17	65703	3	0	0
T21	0	9	0	0
T23	5715	6	0	0
T24	13400	3	0	0
T25	41264	8	0	0
T26	9224	19	0	0
T27	67905	3	0	0
T39	6970	12	0	0
T40	0	20	0	0
T42	150503	0	0	0
T71	0	5	0	0
T73	13805	0	0	0
T74	13604	0	0	0
T75	8135	0	0	0
T76	11598	0	0	0
T79	14172	0	0	0
T122	31391	0	0	0
T172	0	15	0	0
T173	0	20	0	0
T174	0	10	0	0
T175	0	5	0	0
T176	0	10	0	0
T177	0	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38998	0	0
T1	4922228	59	0	0
T2	1162684	0	0	0
T3	3001854	185	0	0
T5	12281	4	0	0
T6	35731	0	0	0
T7	10128	0	0	0
T17	65703	0	0	0
T21	0	9	0	0
T23	5715	9	0	0
T24	13400	0	0	0
T25	41264	5	0	0
T26	9224	16	0	0
T27	67905	0	0	0
T32	0	74	0	0
T39	6970	18	0	0
T40	0	24	0	0
T42	150503	4	0	0
T71	0	5	0	0
T73	13805	3	0	0
T74	13604	0	0	0
T75	8135	0	0	0
T76	11598	0	0	0
T77	0	3	0	0
T79	14172	3	0	0
T122	31391	0	0	0
T172	0	15	0	0
T173	0	20	0	0
T174	0	10	0	0
T175	0	5	0	0
T176	0	10	0	0
T177	0	15	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T39
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	230354170	146	0	0
CgEnOn_A	230354170	146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230354170	146	0	0
T3	127671	0	0	0
T23	568	1	0	0
T39	686	2	0	0
T40	0	4	0	0
T42	15519	0	0	0
T71	0	1	0	0
T73	1383	0	0	0
T74	1388	0	0	0
T75	817	0	0	0
T76	1254	0	0	0
T79	1442	0	0	0
T122	3270	0	0	0
T172	0	3	0	0
T173	0	4	0	0
T174	0	2	0	0
T175	0	1	0	0
T176	0	2	0	0
T177	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230354170	146	0	0
T3	127671	0	0	0
T23	568	1	0	0
T39	686	2	0	0
T40	0	4	0	0
T42	15519	0	0	0
T71	0	1	0	0
T73	1383	0	0	0
T74	1388	0	0	0
T75	817	0	0	0
T76	1254	0	0	0
T79	1442	0	0	0
T122	3270	0	0	0
T172	0	3	0	0
T173	0	4	0	0
T174	0	2	0	0
T175	0	1	0	0
T176	0	2	0	0
T177	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T39
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	115176481	146	0	0
CgEnOn_A	115176481	146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115176481	146	0	0
T3	638355	0	0	0
T23	284	1	0	0
T39	343	2	0	0
T40	0	4	0	0
T42	7760	0	0	0
T71	0	1	0	0
T73	692	0	0	0
T74	694	0	0	0
T75	409	0	0	0
T76	625	0	0	0
T79	721	0	0	0
T122	1635	0	0	0
T172	0	3	0	0
T173	0	4	0	0
T174	0	2	0	0
T175	0	1	0	0
T176	0	2	0	0
T177	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115176481	146	0	0
T3	638355	0	0	0
T23	284	1	0	0
T39	343	2	0	0
T40	0	4	0	0
T42	7760	0	0	0
T71	0	1	0	0
T73	692	0	0	0
T74	694	0	0	0
T75	409	0	0	0
T76	625	0	0	0
T79	721	0	0	0
T122	1635	0	0	0
T172	0	3	0	0
T173	0	4	0	0
T174	0	2	0	0
T175	0	1	0	0
T176	0	2	0	0
T177	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T39
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	115176481	146	0	0
CgEnOn_A	115176481	146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115176481	146	0	0
T3	638355	0	0	0
T23	284	1	0	0
T39	343	2	0	0
T40	0	4	0	0
T42	7760	0	0	0
T71	0	1	0	0
T73	692	0	0	0
T74	694	0	0	0
T75	409	0	0	0
T76	625	0	0	0
T79	721	0	0	0
T122	1635	0	0	0
T172	0	3	0	0
T173	0	4	0	0
T174	0	2	0	0
T175	0	1	0	0
T176	0	2	0	0
T177	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115176481	146	0	0
T3	638355	0	0	0
T23	284	1	0	0
T39	343	2	0	0
T40	0	4	0	0
T42	7760	0	0	0
T71	0	1	0	0
T73	692	0	0	0
T74	694	0	0	0
T75	409	0	0	0
T76	625	0	0	0
T79	721	0	0	0
T122	1635	0	0	0
T172	0	3	0	0
T173	0	4	0	0
T174	0	2	0	0
T175	0	1	0	0
T176	0	2	0	0
T177	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T39
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	115176481	146	0	0
CgEnOn_A	115176481	146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115176481	146	0	0
T3	638355	0	0	0
T23	284	1	0	0
T39	343	2	0	0
T40	0	4	0	0
T42	7760	0	0	0
T71	0	1	0	0
T73	692	0	0	0
T74	694	0	0	0
T75	409	0	0	0
T76	625	0	0	0
T79	721	0	0	0
T122	1635	0	0	0
T172	0	3	0	0
T173	0	4	0	0
T174	0	2	0	0
T175	0	1	0	0
T176	0	2	0	0
T177	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115176481	146	0	0
T3	638355	0	0	0
T23	284	1	0	0
T39	343	2	0	0
T40	0	4	0	0
T42	7760	0	0	0
T71	0	1	0	0
T73	692	0	0	0
T74	694	0	0	0
T75	409	0	0	0
T76	625	0	0	0
T79	721	0	0	0
T122	1635	0	0	0
T172	0	3	0	0
T173	0	4	0	0
T174	0	2	0	0
T175	0	1	0	0
T176	0	2	0	0
T177	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T39
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	462284330	146	0	0
CgEnOn_A	462284330	139	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462284330	146	0	0
T3	256955	0	0	0
T23	1216	1	0	0
T39	1452	2	0	0
T40	0	4	0	0
T42	31173	0	0	0
T71	0	1	0	0
T73	2887	0	0	0
T74	2828	0	0	0
T75	1700	0	0	0
T76	2363	0	0	0
T79	2949	0	0	0
T122	6479	0	0	0
T172	0	3	0	0
T173	0	4	0	0
T174	0	2	0	0
T175	0	1	0	0
T176	0	2	0	0
T177	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462284330	139	0	0
T3	256955	0	0	0
T23	1216	1	0	0
T39	1452	2	0	0
T40	0	4	0	0
T42	31173	0	0	0
T71	0	1	0	0
T73	2887	0	0	0
T74	2828	0	0	0
T75	1700	0	0	0
T76	2363	0	0	0
T79	2949	0	0	0
T122	6479	0	0	0
T172	0	3	0	0
T173	0	4	0	0
T174	0	2	0	0
T175	0	1	0	0
T176	0	2	0	0
T177	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T39
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	492655958	151	0	0
CgEnOn_A	492655958	144	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492655958	151	0	0
T3	283384	1	0	0
T23	1240	1	0	0
T39	1525	2	0	0
T40	0	2	0	0
T42	32472	0	0	0
T69	0	1	0	0
T73	3008	0	0	0
T74	2946	0	0	0
T75	1771	0	0	0
T76	2462	0	0	0
T79	3072	0	0	0
T122	6749	0	0	0
T172	0	3	0	0
T173	0	5	0	0
T174	0	2	0	0
T176	0	1	0	0
T177	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492655958	144	0	0
T3	283384	0	0	0
T23	1240	1	0	0
T39	1525	2	0	0
T40	0	2	0	0
T42	32472	0	0	0
T73	3008	0	0	0
T74	2946	0	0	0
T75	1771	0	0	0
T76	2462	0	0	0
T79	3072	0	0	0
T122	6749	0	0	0
T172	0	3	0	0
T173	0	5	0	0
T174	0	2	0	0
T176	0	1	0	0
T177	0	4	0	0
T178	0	2	0	0
T179	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T39
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	492655958	151	0	0
CgEnOn_A	492655958	144	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492655958	151	0	0
T3	283384	1	0	0
T23	1240	1	0	0
T39	1525	2	0	0
T40	0	2	0	0
T42	32472	0	0	0
T69	0	1	0	0
T73	3008	0	0	0
T74	2946	0	0	0
T75	1771	0	0	0
T76	2462	0	0	0
T79	3072	0	0	0
T122	6749	0	0	0
T172	0	3	0	0
T173	0	5	0	0
T174	0	2	0	0
T176	0	1	0	0
T177	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492655958	144	0	0
T3	283384	0	0	0
T23	1240	1	0	0
T39	1525	2	0	0
T40	0	2	0	0
T42	32472	0	0	0
T73	3008	0	0	0
T74	2946	0	0	0
T75	1771	0	0	0
T76	2462	0	0	0
T79	3072	0	0	0
T122	6749	0	0	0
T172	0	3	0	0
T173	0	5	0	0
T174	0	2	0	0
T176	0	1	0	0
T177	0	4	0	0
T178	0	2	0	0
T179	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T39
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	236463771	139	0	0
CgEnOn_A	236463771	137	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236463771	139	0	0
T3	135395	0	0	0
T23	599	2	0	0
T39	753	2	0	0
T40	0	2	0	0
T42	15587	0	0	0
T73	1443	0	0	0
T74	1414	0	0	0
T75	849	0	0	0
T76	1182	0	0	0
T79	1474	0	0	0
T122	3239	0	0	0
T172	0	5	0	0
T173	0	5	0	0
T174	0	2	0	0
T176	0	3	0	0
T177	0	4	0	0
T178	0	2	0	0
T179	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236463771	137	0	0
T3	135395	0	0	0
T23	599	2	0	0
T39	753	2	0	0
T40	0	2	0	0
T42	15587	0	0	0
T73	1443	0	0	0
T74	1414	0	0	0
T75	849	0	0	0
T76	1182	0	0	0
T79	1474	0	0	0
T122	3239	0	0	0
T172	0	5	0	0
T173	0	5	0	0
T174	0	2	0	0
T176	0	3	0	0
T177	0	4	0	0
T178	0	2	0	0
T179	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T39,T40
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	115176481	7869	0	0
CgEnOn_A	115176481	5541	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115176481	7869	0	0
T1	185306	16	0	0
T2	45275	1	0	0
T5	452	2	0	0
T6	1375	1	0	0
T7	393	1	0	0
T17	2913	1	0	0
T24	542	1	0	0
T25	1587	1	0	0
T26	348	7	0	0
T27	2941	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115176481	5541	0	0
T1	185306	11	0	0
T2	45275	0	0	0
T3	0	51	0	0
T5	452	1	0	0
T6	1375	0	0	0
T7	393	0	0	0
T17	2913	0	0	0
T23	0	1	0	0
T24	542	0	0	0
T25	1587	0	0	0
T26	348	6	0	0
T27	2941	0	0	0
T32	0	24	0	0
T39	0	2	0	0
T40	0	4	0	0
T42	0	1	0	0
T77	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T39,T40
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	230354170	7907	0	0
CgEnOn_A	230354170	5579	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230354170	7907	0	0
T1	370613	19	0	0
T2	90549	1	0	0
T5	904	2	0	0
T6	2749	1	0	0
T7	787	1	0	0
T17	5828	1	0	0
T24	1085	1	0	0
T25	3174	1	0	0
T26	695	6	0	0
T27	5886	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230354170	5579	0	0
T1	370613	14	0	0
T2	90549	0	0	0
T3	0	48	0	0
T5	904	1	0	0
T6	2749	0	0	0
T7	787	0	0	0
T17	5828	0	0	0
T23	0	1	0	0
T24	1085	0	0	0
T25	3174	0	0	0
T26	695	5	0	0
T27	5886	0	0	0
T32	0	26	0	0
T39	0	2	0	0
T42	0	1	0	0
T73	0	1	0	0
T77	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T39,T40
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	462284330	7945	0	0
CgEnOn_A	462284330	5610	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462284330	7945	0	0
T1	741536	18	0	0
T2	181205	1	0	0
T5	1929	2	0	0
T6	5578	1	0	0
T7	1579	1	0	0
T17	10052	1	0	0
T24	2078	1	0	0
T25	6442	1	0	0
T26	1443	6	0	0
T27	10425	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462284330	5610	0	0
T1	741536	13	0	0
T2	181205	0	0	0
T3	0	48	0	0
T5	1929	1	0	0
T6	5578	0	0	0
T7	1579	0	0	0
T17	10052	0	0	0
T23	0	1	0	0
T24	2078	0	0	0
T25	6442	0	0	0
T26	1443	5	0	0
T27	10425	0	0	0
T32	0	24	0	0
T39	0	2	0	0
T42	0	1	0	0
T73	0	1	0	0
T77	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T39,T40
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	236463771	7956	0	0
CgEnOn_A	236463771	5619	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236463771	7956	0	0
T1	390945	17	0	0
T2	90607	1	0	0
T5	964	2	0	0
T6	2789	1	0	0
T7	789	1	0	0
T17	5026	1	0	0
T24	1039	1	0	0
T25	3221	1	0	0
T26	722	6	0	0
T27	5213	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236463771	5619	0	0
T1	390945	12	0	0
T2	90607	0	0	0
T3	0	48	0	0
T5	964	1	0	0
T6	2789	0	0	0
T7	789	0	0	0
T17	5026	0	0	0
T23	0	2	0	0
T24	1039	0	0	0
T25	3221	0	0	0
T26	722	5	0	0
T27	5213	0	0	0
T32	0	24	0	0
T39	0	2	0	0
T42	0	1	0	0
T73	0	1	0	0
T77	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T39
1	0	Covered	T5,T25,T1
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	492655958	3918	0	0
CgEnOn_A	492655958	3911	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492655958	3918	0	0
T1	808457	21	0	0
T2	188762	0	0	0
T3	0	39	0	0
T5	2008	1	0	0
T6	5810	0	0	0
T7	1645	0	0	0
T17	10471	0	0	0
T21	0	9	0	0
T23	0	1	0	0
T24	2164	0	0	0
T25	6710	5	0	0
T26	1504	0	0	0
T27	10860	0	0	0
T39	0	2	0	0
T42	0	1	0	0
T73	0	1	0	0
T79	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492655958	3911	0	0
T1	808457	21	0	0
T2	188762	0	0	0
T3	0	38	0	0
T5	2008	1	0	0
T6	5810	0	0	0
T7	1645	0	0	0
T17	10471	0	0	0
T21	0	9	0	0
T23	0	1	0	0
T24	2164	0	0	0
T25	6710	5	0	0
T26	1504	0	0	0
T27	10860	0	0	0
T39	0	2	0	0
T42	0	1	0	0
T73	0	1	0	0
T79	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T39
1	0	Covered	T5,T6,T25
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	492655958	3849	0	0
CgEnOn_A	492655958	3842	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492655958	3849	0	0
T1	808457	17	0	0
T2	188762	0	0	0
T3	0	43	0	0
T5	2008	1	0	0
T6	5810	2	0	0
T7	1645	0	0	0
T17	10471	0	0	0
T21	0	12	0	0
T23	0	1	0	0
T24	2164	0	0	0
T25	6710	12	0	0
T26	1504	0	0	0
T27	10860	0	0	0
T39	0	2	0	0
T42	0	1	0	0
T79	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492655958	3842	0	0
T1	808457	17	0	0
T2	188762	0	0	0
T3	0	42	0	0
T5	2008	1	0	0
T6	5810	2	0	0
T7	1645	0	0	0
T17	10471	0	0	0
T21	0	12	0	0
T23	0	1	0	0
T24	2164	0	0	0
T25	6710	12	0	0
T26	1504	0	0	0
T27	10860	0	0	0
T39	0	2	0	0
T42	0	1	0	0
T79	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T39
1	0	Covered	T5,T6,T25
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	492655958	3893	0	0
CgEnOn_A	492655958	3886	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492655958	3893	0	0
T1	808457	21	0	0
T2	188762	0	0	0
T3	0	46	0	0
T5	2008	1	0	0
T6	5810	2	0	0
T7	1645	0	0	0
T17	10471	0	0	0
T21	0	8	0	0
T23	0	1	0	0
T24	2164	0	0	0
T25	6710	10	0	0
T26	1504	0	0	0
T27	10860	0	0	0
T39	0	2	0	0
T42	0	1	0	0
T79	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492655958	3886	0	0
T1	808457	21	0	0
T2	188762	0	0	0
T3	0	45	0	0
T5	2008	1	0	0
T6	5810	2	0	0
T7	1645	0	0	0
T17	10471	0	0	0
T21	0	8	0	0
T23	0	1	0	0
T24	2164	0	0	0
T25	6710	10	0	0
T26	1504	0	0	0
T27	10860	0	0	0
T39	0	2	0	0
T42	0	1	0	0
T79	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T39
1	0	Covered	T5,T6,T25
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	492655958	3869	0	0
CgEnOn_A	492655958	3862	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492655958	3869	0	0
T1	808457	16	0	0
T2	188762	0	0	0
T3	0	45	0	0
T5	2008	1	0	0
T6	5810	2	0	0
T7	1645	0	0	0
T17	10471	0	0	0
T21	0	12	0	0
T23	0	1	0	0
T24	2164	0	0	0
T25	6710	7	0	0
T26	1504	0	0	0
T27	10860	0	0	0
T39	0	2	0	0
T42	0	1	0	0
T79	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492655958	3862	0	0
T1	808457	16	0	0
T2	188762	0	0	0
T3	0	44	0	0
T5	2008	1	0	0
T6	5810	2	0	0
T7	1645	0	0	0
T17	10471	0	0	0
T21	0	12	0	0
T23	0	1	0	0
T24	2164	0	0	0
T25	6710	7	0	0
T26	1504	0	0	0
T27	10860	0	0	0
T39	0	2	0	0
T42	0	1	0	0
T79	0	4	0	0