Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Module :
prim_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1009500 |
0 |
0 |
T1 |
968017 |
506 |
0 |
0 |
T2 |
942670 |
474 |
0 |
0 |
T3 |
280252 |
152 |
0 |
0 |
T6 |
0 |
230 |
0 |
0 |
T7 |
0 |
276 |
0 |
0 |
T8 |
0 |
8753 |
0 |
0 |
T9 |
0 |
544 |
0 |
0 |
T13 |
16038 |
0 |
0 |
0 |
T14 |
15815 |
0 |
0 |
0 |
T15 |
16958 |
0 |
0 |
0 |
T16 |
13649 |
0 |
0 |
0 |
T17 |
6585 |
0 |
0 |
0 |
T18 |
15914 |
0 |
0 |
0 |
T19 |
426685 |
244 |
0 |
0 |
T22 |
0 |
190 |
0 |
0 |
T23 |
0 |
114 |
0 |
0 |
T24 |
0 |
70 |
0 |
0 |
T25 |
0 |
878 |
0 |
0 |
T52 |
10168 |
2 |
0 |
0 |
T53 |
31926 |
1 |
0 |
0 |
T54 |
18004 |
2 |
0 |
0 |
T56 |
5029 |
0 |
0 |
0 |
T57 |
2591 |
1 |
0 |
0 |
T58 |
11162 |
4 |
0 |
0 |
T59 |
22858 |
2 |
0 |
0 |
T117 |
11220 |
3 |
0 |
0 |
T118 |
13320 |
1 |
0 |
0 |
T119 |
11706 |
1 |
0 |
0 |
T120 |
5409 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1006859 |
0 |
0 |
T1 |
241557 |
506 |
0 |
0 |
T2 |
212709 |
474 |
0 |
0 |
T3 |
99652 |
152 |
0 |
0 |
T6 |
0 |
230 |
0 |
0 |
T7 |
0 |
276 |
0 |
0 |
T8 |
0 |
8759 |
0 |
0 |
T9 |
0 |
544 |
0 |
0 |
T13 |
5123 |
0 |
0 |
0 |
T14 |
6613 |
0 |
0 |
0 |
T15 |
10114 |
0 |
0 |
0 |
T16 |
7400 |
0 |
0 |
0 |
T17 |
3870 |
0 |
0 |
0 |
T18 |
7492 |
0 |
0 |
0 |
T19 |
227545 |
244 |
0 |
0 |
T22 |
0 |
190 |
0 |
0 |
T23 |
0 |
114 |
0 |
0 |
T24 |
0 |
70 |
0 |
0 |
T25 |
0 |
878 |
0 |
0 |
T52 |
80098 |
2 |
0 |
0 |
T53 |
13592 |
1 |
0 |
0 |
T54 |
32540 |
2 |
0 |
0 |
T56 |
2171 |
0 |
0 |
0 |
T57 |
20203 |
1 |
0 |
0 |
T58 |
21124 |
4 |
0 |
0 |
T59 |
10182 |
2 |
0 |
0 |
T117 |
88156 |
3 |
0 |
0 |
T118 |
12356 |
1 |
0 |
0 |
T119 |
25954 |
1 |
0 |
0 |
T120 |
10484 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
536805478 |
26572 |
0 |
0 |
T1 |
239530 |
42 |
0 |
0 |
T2 |
236707 |
32 |
0 |
0 |
T3 |
65153 |
12 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
0 |
20 |
0 |
0 |
T13 |
3991 |
0 |
0 |
0 |
T14 |
3706 |
0 |
0 |
0 |
T15 |
3527 |
0 |
0 |
0 |
T16 |
2940 |
0 |
0 |
0 |
T17 |
1401 |
0 |
0 |
0 |
T18 |
2865 |
0 |
0 |
0 |
T19 |
88503 |
16 |
0 |
0 |
T22 |
0 |
38 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T24 |
0 |
14 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160294252 |
26572 |
0 |
0 |
T1 |
59883 |
42 |
0 |
0 |
T2 |
39452 |
32 |
0 |
0 |
T3 |
33256 |
12 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
0 |
20 |
0 |
0 |
T13 |
997 |
0 |
0 |
0 |
T14 |
1853 |
0 |
0 |
0 |
T15 |
3674 |
0 |
0 |
0 |
T16 |
2543 |
0 |
0 |
0 |
T17 |
1401 |
0 |
0 |
0 |
T18 |
2207 |
0 |
0 |
0 |
T19 |
91272 |
16 |
0 |
0 |
T22 |
0 |
38 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T24 |
0 |
14 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
536805478 |
32459 |
0 |
0 |
T1 |
239530 |
42 |
0 |
0 |
T2 |
236707 |
32 |
0 |
0 |
T3 |
65153 |
12 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
0 |
20 |
0 |
0 |
T13 |
3991 |
0 |
0 |
0 |
T14 |
3706 |
0 |
0 |
0 |
T15 |
3527 |
0 |
0 |
0 |
T16 |
2940 |
0 |
0 |
0 |
T17 |
1401 |
0 |
0 |
0 |
T18 |
2865 |
0 |
0 |
0 |
T19 |
88503 |
16 |
0 |
0 |
T22 |
0 |
76 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160294252 |
32475 |
0 |
0 |
T1 |
59883 |
42 |
0 |
0 |
T2 |
39452 |
32 |
0 |
0 |
T3 |
33256 |
12 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
0 |
20 |
0 |
0 |
T13 |
997 |
0 |
0 |
0 |
T14 |
1853 |
0 |
0 |
0 |
T15 |
3674 |
0 |
0 |
0 |
T16 |
2543 |
0 |
0 |
0 |
T17 |
1401 |
0 |
0 |
0 |
T18 |
2207 |
0 |
0 |
0 |
T19 |
91272 |
16 |
0 |
0 |
T22 |
0 |
76 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160294252 |
32451 |
0 |
0 |
T1 |
59883 |
42 |
0 |
0 |
T2 |
39452 |
32 |
0 |
0 |
T3 |
33256 |
12 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
0 |
20 |
0 |
0 |
T13 |
997 |
0 |
0 |
0 |
T14 |
1853 |
0 |
0 |
0 |
T15 |
3674 |
0 |
0 |
0 |
T16 |
2543 |
0 |
0 |
0 |
T17 |
1401 |
0 |
0 |
0 |
T18 |
2207 |
0 |
0 |
0 |
T19 |
91272 |
16 |
0 |
0 |
T22 |
0 |
76 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
536805478 |
32463 |
0 |
0 |
T1 |
239530 |
42 |
0 |
0 |
T2 |
236707 |
32 |
0 |
0 |
T3 |
65153 |
12 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
0 |
20 |
0 |
0 |
T13 |
3991 |
0 |
0 |
0 |
T14 |
3706 |
0 |
0 |
0 |
T15 |
3527 |
0 |
0 |
0 |
T16 |
2940 |
0 |
0 |
0 |
T17 |
1401 |
0 |
0 |
0 |
T18 |
2865 |
0 |
0 |
0 |
T19 |
88503 |
16 |
0 |
0 |
T22 |
0 |
76 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
267643652 |
26572 |
0 |
0 |
T1 |
119739 |
42 |
0 |
0 |
T2 |
119981 |
32 |
0 |
0 |
T3 |
32564 |
12 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
0 |
20 |
0 |
0 |
T13 |
1969 |
0 |
0 |
0 |
T14 |
1827 |
0 |
0 |
0 |
T15 |
1738 |
0 |
0 |
0 |
T16 |
1458 |
0 |
0 |
0 |
T17 |
664 |
0 |
0 |
0 |
T18 |
2246 |
0 |
0 |
0 |
T19 |
44205 |
16 |
0 |
0 |
T22 |
0 |
38 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T24 |
0 |
14 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160294252 |
26572 |
0 |
0 |
T1 |
59883 |
42 |
0 |
0 |
T2 |
39452 |
32 |
0 |
0 |
T3 |
33256 |
12 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
0 |
20 |
0 |
0 |
T13 |
997 |
0 |
0 |
0 |
T14 |
1853 |
0 |
0 |
0 |
T15 |
3674 |
0 |
0 |
0 |
T16 |
2543 |
0 |
0 |
0 |
T17 |
1401 |
0 |
0 |
0 |
T18 |
2207 |
0 |
0 |
0 |
T19 |
91272 |
16 |
0 |
0 |
T22 |
0 |
38 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T24 |
0 |
14 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
267643652 |
32215 |
0 |
0 |
T1 |
119739 |
42 |
0 |
0 |
T2 |
119981 |
32 |
0 |
0 |
T3 |
32564 |
12 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
0 |
20 |
0 |
0 |
T13 |
1969 |
0 |
0 |
0 |
T14 |
1827 |
0 |
0 |
0 |
T15 |
1738 |
0 |
0 |
0 |
T16 |
1458 |
0 |
0 |
0 |
T17 |
664 |
0 |
0 |
0 |
T18 |
2246 |
0 |
0 |
0 |
T19 |
44205 |
16 |
0 |
0 |
T22 |
0 |
76 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160294252 |
32234 |
0 |
0 |
T1 |
59883 |
42 |
0 |
0 |
T2 |
39452 |
32 |
0 |
0 |
T3 |
33256 |
12 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
0 |
20 |
0 |
0 |
T13 |
997 |
0 |
0 |
0 |
T14 |
1853 |
0 |
0 |
0 |
T15 |
3674 |
0 |
0 |
0 |
T16 |
2543 |
0 |
0 |
0 |
T17 |
1401 |
0 |
0 |
0 |
T18 |
2207 |
0 |
0 |
0 |
T19 |
91272 |
16 |
0 |
0 |
T22 |
0 |
76 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160294252 |
32202 |
0 |
0 |
T1 |
59883 |
42 |
0 |
0 |
T2 |
39452 |
32 |
0 |
0 |
T3 |
33256 |
12 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
0 |
20 |
0 |
0 |
T13 |
997 |
0 |
0 |
0 |
T14 |
1853 |
0 |
0 |
0 |
T15 |
3674 |
0 |
0 |
0 |
T16 |
2543 |
0 |
0 |
0 |
T17 |
1401 |
0 |
0 |
0 |
T18 |
2207 |
0 |
0 |
0 |
T19 |
91272 |
16 |
0 |
0 |
T22 |
0 |
76 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
267643652 |
32219 |
0 |
0 |
T1 |
119739 |
42 |
0 |
0 |
T2 |
119981 |
32 |
0 |
0 |
T3 |
32564 |
12 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
0 |
20 |
0 |
0 |
T13 |
1969 |
0 |
0 |
0 |
T14 |
1827 |
0 |
0 |
0 |
T15 |
1738 |
0 |
0 |
0 |
T16 |
1458 |
0 |
0 |
0 |
T17 |
664 |
0 |
0 |
0 |
T18 |
2246 |
0 |
0 |
0 |
T19 |
44205 |
16 |
0 |
0 |
T22 |
0 |
76 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
133821235 |
26572 |
0 |
0 |
T1 |
59869 |
42 |
0 |
0 |
T2 |
59989 |
32 |
0 |
0 |
T3 |
16282 |
12 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
0 |
20 |
0 |
0 |
T13 |
985 |
0 |
0 |
0 |
T14 |
914 |
0 |
0 |
0 |
T15 |
869 |
0 |
0 |
0 |
T16 |
729 |
0 |
0 |
0 |
T17 |
332 |
0 |
0 |
0 |
T18 |
1120 |
0 |
0 |
0 |
T19 |
22102 |
16 |
0 |
0 |
T22 |
0 |
38 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T24 |
0 |
14 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160294252 |
26572 |
0 |
0 |
T1 |
59883 |
42 |
0 |
0 |
T2 |
39452 |
32 |
0 |
0 |
T3 |
33256 |
12 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
0 |
20 |
0 |
0 |
T13 |
997 |
0 |
0 |
0 |
T14 |
1853 |
0 |
0 |
0 |
T15 |
3674 |
0 |
0 |
0 |
T16 |
2543 |
0 |
0 |
0 |
T17 |
1401 |
0 |
0 |
0 |
T18 |
2207 |
0 |
0 |
0 |
T19 |
91272 |
16 |
0 |
0 |
T22 |
0 |
38 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T24 |
0 |
14 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
133821235 |
32186 |
0 |
0 |
T1 |
59869 |
42 |
0 |
0 |
T2 |
59989 |
32 |
0 |
0 |
T3 |
16282 |
12 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
0 |
20 |
0 |
0 |
T13 |
985 |
0 |
0 |
0 |
T14 |
914 |
0 |
0 |
0 |
T15 |
869 |
0 |
0 |
0 |
T16 |
729 |
0 |
0 |
0 |
T17 |
332 |
0 |
0 |
0 |
T18 |
1120 |
0 |
0 |
0 |
T19 |
22102 |
16 |
0 |
0 |
T22 |
0 |
76 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160294252 |
32219 |
0 |
0 |
T1 |
59883 |
42 |
0 |
0 |
T2 |
39452 |
32 |
0 |
0 |
T3 |
33256 |
12 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
0 |
20 |
0 |
0 |
T13 |
997 |
0 |
0 |
0 |
T14 |
1853 |
0 |
0 |
0 |
T15 |
3674 |
0 |
0 |
0 |
T16 |
2543 |
0 |
0 |
0 |
T17 |
1401 |
0 |
0 |
0 |
T18 |
2207 |
0 |
0 |
0 |
T19 |
91272 |
16 |
0 |
0 |
T22 |
0 |
76 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160294252 |
32182 |
0 |
0 |
T1 |
59883 |
42 |
0 |
0 |
T2 |
39452 |
32 |
0 |
0 |
T3 |
33256 |
12 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
0 |
20 |
0 |
0 |
T13 |
997 |
0 |
0 |
0 |
T14 |
1853 |
0 |
0 |
0 |
T15 |
3674 |
0 |
0 |
0 |
T16 |
2543 |
0 |
0 |
0 |
T17 |
1401 |
0 |
0 |
0 |
T18 |
2207 |
0 |
0 |
0 |
T19 |
91272 |
16 |
0 |
0 |
T22 |
0 |
76 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
133821235 |
32191 |
0 |
0 |
T1 |
59869 |
42 |
0 |
0 |
T2 |
59989 |
32 |
0 |
0 |
T3 |
16282 |
12 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
0 |
20 |
0 |
0 |
T13 |
985 |
0 |
0 |
0 |
T14 |
914 |
0 |
0 |
0 |
T15 |
869 |
0 |
0 |
0 |
T16 |
729 |
0 |
0 |
0 |
T17 |
332 |
0 |
0 |
0 |
T18 |
1120 |
0 |
0 |
0 |
T19 |
22102 |
16 |
0 |
0 |
T22 |
0 |
76 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
571402078 |
26572 |
0 |
0 |
T1 |
249518 |
42 |
0 |
0 |
T2 |
246579 |
32 |
0 |
0 |
T3 |
67869 |
12 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
0 |
20 |
0 |
0 |
T13 |
4158 |
0 |
0 |
0 |
T14 |
3861 |
0 |
0 |
0 |
T15 |
3674 |
0 |
0 |
0 |
T16 |
3063 |
0 |
0 |
0 |
T17 |
1459 |
0 |
0 |
0 |
T18 |
2984 |
0 |
0 |
0 |
T19 |
92193 |
16 |
0 |
0 |
T22 |
0 |
38 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T24 |
0 |
14 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160294252 |
26572 |
0 |
0 |
T1 |
59883 |
42 |
0 |
0 |
T2 |
39452 |
32 |
0 |
0 |
T3 |
33256 |
12 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
0 |
20 |
0 |
0 |
T13 |
997 |
0 |
0 |
0 |
T14 |
1853 |
0 |
0 |
0 |
T15 |
3674 |
0 |
0 |
0 |
T16 |
2543 |
0 |
0 |
0 |
T17 |
1401 |
0 |
0 |
0 |
T18 |
2207 |
0 |
0 |
0 |
T19 |
91272 |
16 |
0 |
0 |
T22 |
0 |
38 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T24 |
0 |
14 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
571402078 |
32153 |
0 |
0 |
T1 |
249518 |
42 |
0 |
0 |
T2 |
246579 |
32 |
0 |
0 |
T3 |
67869 |
12 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
0 |
20 |
0 |
0 |
T13 |
4158 |
0 |
0 |
0 |
T14 |
3861 |
0 |
0 |
0 |
T15 |
3674 |
0 |
0 |
0 |
T16 |
3063 |
0 |
0 |
0 |
T17 |
1459 |
0 |
0 |
0 |
T18 |
2984 |
0 |
0 |
0 |
T19 |
92193 |
16 |
0 |
0 |
T22 |
0 |
76 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160294252 |
32169 |
0 |
0 |
T1 |
59883 |
42 |
0 |
0 |
T2 |
39452 |
32 |
0 |
0 |
T3 |
33256 |
12 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
0 |
20 |
0 |
0 |
T13 |
997 |
0 |
0 |
0 |
T14 |
1853 |
0 |
0 |
0 |
T15 |
3674 |
0 |
0 |
0 |
T16 |
2543 |
0 |
0 |
0 |
T17 |
1401 |
0 |
0 |
0 |
T18 |
2207 |
0 |
0 |
0 |
T19 |
91272 |
16 |
0 |
0 |
T22 |
0 |
76 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160294252 |
32134 |
0 |
0 |
T1 |
59883 |
42 |
0 |
0 |
T2 |
39452 |
32 |
0 |
0 |
T3 |
33256 |
12 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
0 |
20 |
0 |
0 |
T13 |
997 |
0 |
0 |
0 |
T14 |
1853 |
0 |
0 |
0 |
T15 |
3674 |
0 |
0 |
0 |
T16 |
2543 |
0 |
0 |
0 |
T17 |
1401 |
0 |
0 |
0 |
T18 |
2207 |
0 |
0 |
0 |
T19 |
91272 |
16 |
0 |
0 |
T22 |
0 |
76 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
571402078 |
32155 |
0 |
0 |
T1 |
249518 |
42 |
0 |
0 |
T2 |
246579 |
32 |
0 |
0 |
T3 |
67869 |
12 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
0 |
20 |
0 |
0 |
T13 |
4158 |
0 |
0 |
0 |
T14 |
3861 |
0 |
0 |
0 |
T15 |
3674 |
0 |
0 |
0 |
T16 |
3063 |
0 |
0 |
0 |
T17 |
1459 |
0 |
0 |
0 |
T18 |
2984 |
0 |
0 |
0 |
T19 |
92193 |
16 |
0 |
0 |
T22 |
0 |
76 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
274144053 |
26173 |
0 |
0 |
T1 |
119770 |
42 |
0 |
0 |
T2 |
118359 |
32 |
0 |
0 |
T3 |
32578 |
12 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
0 |
20 |
0 |
0 |
T13 |
1995 |
0 |
0 |
0 |
T14 |
1853 |
0 |
0 |
0 |
T15 |
1763 |
0 |
0 |
0 |
T16 |
1470 |
0 |
0 |
0 |
T17 |
701 |
0 |
0 |
0 |
T18 |
1432 |
0 |
0 |
0 |
T19 |
44253 |
16 |
0 |
0 |
T22 |
0 |
31 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T24 |
0 |
7 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160294252 |
26572 |
0 |
0 |
T1 |
59883 |
42 |
0 |
0 |
T2 |
39452 |
32 |
0 |
0 |
T3 |
33256 |
12 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
0 |
20 |
0 |
0 |
T13 |
997 |
0 |
0 |
0 |
T14 |
1853 |
0 |
0 |
0 |
T15 |
3674 |
0 |
0 |
0 |
T16 |
2543 |
0 |
0 |
0 |
T17 |
1401 |
0 |
0 |
0 |
T18 |
2207 |
0 |
0 |
0 |
T19 |
91272 |
16 |
0 |
0 |
T22 |
0 |
38 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T24 |
0 |
14 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
274144053 |
32231 |
0 |
0 |
T1 |
119770 |
42 |
0 |
0 |
T2 |
118359 |
32 |
0 |
0 |
T3 |
32578 |
12 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
0 |
20 |
0 |
0 |
T13 |
1995 |
0 |
0 |
0 |
T14 |
1853 |
0 |
0 |
0 |
T15 |
1763 |
0 |
0 |
0 |
T16 |
1470 |
0 |
0 |
0 |
T17 |
701 |
0 |
0 |
0 |
T18 |
1432 |
0 |
0 |
0 |
T19 |
44253 |
16 |
0 |
0 |
T22 |
0 |
76 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160294252 |
32389 |
0 |
0 |
T1 |
59883 |
42 |
0 |
0 |
T2 |
39452 |
32 |
0 |
0 |
T3 |
33256 |
12 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
0 |
20 |
0 |
0 |
T13 |
997 |
0 |
0 |
0 |
T14 |
1853 |
0 |
0 |
0 |
T15 |
3674 |
0 |
0 |
0 |
T16 |
2543 |
0 |
0 |
0 |
T17 |
1401 |
0 |
0 |
0 |
T18 |
2207 |
0 |
0 |
0 |
T19 |
91272 |
16 |
0 |
0 |
T22 |
0 |
76 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160294252 |
32080 |
0 |
0 |
T1 |
59883 |
42 |
0 |
0 |
T2 |
39452 |
32 |
0 |
0 |
T3 |
33256 |
12 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
0 |
20 |
0 |
0 |
T13 |
997 |
0 |
0 |
0 |
T14 |
1853 |
0 |
0 |
0 |
T15 |
3674 |
0 |
0 |
0 |
T16 |
2543 |
0 |
0 |
0 |
T17 |
1401 |
0 |
0 |
0 |
T18 |
2207 |
0 |
0 |
0 |
T19 |
91272 |
16 |
0 |
0 |
T22 |
0 |
57 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T24 |
0 |
21 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
274144053 |
32267 |
0 |
0 |
T1 |
119770 |
42 |
0 |
0 |
T2 |
118359 |
32 |
0 |
0 |
T3 |
32578 |
12 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
0 |
20 |
0 |
0 |
T13 |
1995 |
0 |
0 |
0 |
T14 |
1853 |
0 |
0 |
0 |
T15 |
1763 |
0 |
0 |
0 |
T16 |
1470 |
0 |
0 |
0 |
T17 |
701 |
0 |
0 |
0 |
T18 |
1432 |
0 |
0 |
0 |
T19 |
44253 |
16 |
0 |
0 |
T22 |
0 |
76 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T24 |
0 |
28 |
0 |
0 |
T25 |
0 |
30 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T52,T54,T56 |
1 | 0 | Covered | T52,T54,T56 |
1 | 1 | Covered | T54,T56,T121 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T52,T54,T56 |
1 | 0 | Covered | T54,T56,T121 |
1 | 1 | Covered | T52,T54,T56 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160294252 |
39 |
0 |
0 |
T52 |
5084 |
1 |
0 |
0 |
T54 |
9002 |
3 |
0 |
0 |
T56 |
5029 |
2 |
0 |
0 |
T58 |
5581 |
2 |
0 |
0 |
T59 |
11429 |
2 |
0 |
0 |
T117 |
5610 |
1 |
0 |
0 |
T121 |
2657 |
3 |
0 |
0 |
T122 |
4513 |
1 |
0 |
0 |
T123 |
7228 |
1 |
0 |
0 |
T124 |
9552 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
536805478 |
39 |
0 |
0 |
T52 |
81347 |
1 |
0 |
0 |
T54 |
34568 |
3 |
0 |
0 |
T56 |
5029 |
2 |
0 |
0 |
T58 |
22325 |
2 |
0 |
0 |
T59 |
11429 |
2 |
0 |
0 |
T117 |
89763 |
1 |
0 |
0 |
T121 |
10627 |
3 |
0 |
0 |
T122 |
8843 |
1 |
0 |
0 |
T123 |
7008 |
1 |
0 |
0 |
T124 |
9552 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T52,T54,T56 |
1 | 0 | Covered | T52,T54,T56 |
1 | 1 | Covered | T52,T54,T56 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T52,T54,T56 |
1 | 0 | Covered | T52,T54,T56 |
1 | 1 | Covered | T52,T54,T56 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160294252 |
44 |
0 |
0 |
T52 |
5084 |
2 |
0 |
0 |
T54 |
9002 |
2 |
0 |
0 |
T55 |
2830 |
2 |
0 |
0 |
T56 |
5029 |
2 |
0 |
0 |
T57 |
2591 |
1 |
0 |
0 |
T58 |
5581 |
1 |
0 |
0 |
T59 |
11429 |
3 |
0 |
0 |
T121 |
2657 |
1 |
0 |
0 |
T122 |
4513 |
1 |
0 |
0 |
T123 |
7228 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
536805478 |
44 |
0 |
0 |
T52 |
81347 |
2 |
0 |
0 |
T54 |
34568 |
2 |
0 |
0 |
T55 |
15984 |
2 |
0 |
0 |
T56 |
5029 |
2 |
0 |
0 |
T57 |
41467 |
1 |
0 |
0 |
T58 |
22325 |
1 |
0 |
0 |
T59 |
11429 |
3 |
0 |
0 |
T121 |
10627 |
1 |
0 |
0 |
T122 |
8843 |
1 |
0 |
0 |
T123 |
7008 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T52,T53,T54 |
1 | 0 | Covered | T52,T53,T54 |
1 | 1 | Covered | T54,T58,T117 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T52,T53,T54 |
1 | 0 | Covered | T54,T58,T117 |
1 | 1 | Covered | T52,T53,T54 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160294252 |
31 |
0 |
0 |
T52 |
5084 |
2 |
0 |
0 |
T53 |
15963 |
1 |
0 |
0 |
T54 |
9002 |
2 |
0 |
0 |
T57 |
2591 |
1 |
0 |
0 |
T58 |
5581 |
4 |
0 |
0 |
T59 |
11429 |
2 |
0 |
0 |
T117 |
5610 |
3 |
0 |
0 |
T118 |
6660 |
1 |
0 |
0 |
T119 |
5853 |
1 |
0 |
0 |
T120 |
5409 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
267643652 |
31 |
0 |
0 |
T52 |
40049 |
2 |
0 |
0 |
T53 |
6796 |
1 |
0 |
0 |
T54 |
16270 |
2 |
0 |
0 |
T57 |
20203 |
1 |
0 |
0 |
T58 |
10562 |
4 |
0 |
0 |
T59 |
5091 |
2 |
0 |
0 |
T117 |
44078 |
3 |
0 |
0 |
T118 |
6178 |
1 |
0 |
0 |
T119 |
12977 |
1 |
0 |
0 |
T120 |
10484 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T52,T53,T54 |
1 | 0 | Covered | T52,T53,T54 |
1 | 1 | Covered | T117,T125,T126 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T52,T53,T54 |
1 | 0 | Covered | T117,T125,T126 |
1 | 1 | Covered | T52,T53,T54 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160294252 |
31 |
0 |
0 |
T52 |
5084 |
1 |
0 |
0 |
T53 |
15963 |
1 |
0 |
0 |
T54 |
9002 |
1 |
0 |
0 |
T56 |
5029 |
1 |
0 |
0 |
T58 |
5581 |
1 |
0 |
0 |
T59 |
11429 |
2 |
0 |
0 |
T117 |
5610 |
5 |
0 |
0 |
T118 |
6660 |
1 |
0 |
0 |
T119 |
5853 |
1 |
0 |
0 |
T127 |
6559 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
267643652 |
31 |
0 |
0 |
T52 |
40049 |
1 |
0 |
0 |
T53 |
6796 |
1 |
0 |
0 |
T54 |
16270 |
1 |
0 |
0 |
T56 |
2171 |
1 |
0 |
0 |
T58 |
10562 |
1 |
0 |
0 |
T59 |
5091 |
2 |
0 |
0 |
T117 |
44078 |
5 |
0 |
0 |
T118 |
6178 |
1 |
0 |
0 |
T119 |
12977 |
1 |
0 |
0 |
T127 |
2689 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T52,T53,T54 |
1 | 0 | Covered | T52,T53,T54 |
1 | 1 | Covered | T53,T54,T128 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T52,T53,T54 |
1 | 0 | Covered | T53,T54,T128 |
1 | 1 | Covered | T52,T53,T54 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160294252 |
23 |
0 |
0 |
T52 |
5084 |
1 |
0 |
0 |
T53 |
15963 |
3 |
0 |
0 |
T54 |
9002 |
3 |
0 |
0 |
T83 |
11675 |
2 |
0 |
0 |
T121 |
2657 |
1 |
0 |
0 |
T122 |
4513 |
1 |
0 |
0 |
T128 |
2650 |
3 |
0 |
0 |
T129 |
4993 |
1 |
0 |
0 |
T130 |
2923 |
1 |
0 |
0 |
T131 |
4751 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
133821235 |
23 |
0 |
0 |
T52 |
20024 |
1 |
0 |
0 |
T53 |
3396 |
3 |
0 |
0 |
T54 |
8136 |
3 |
0 |
0 |
T83 |
2312 |
2 |
0 |
0 |
T121 |
2468 |
1 |
0 |
0 |
T122 |
1968 |
1 |
0 |
0 |
T128 |
2113 |
3 |
0 |
0 |
T129 |
1076 |
1 |
0 |
0 |
T130 |
8512 |
1 |
0 |
0 |
T131 |
2193 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T52,T53,T54 |
1 | 0 | Covered | T52,T53,T54 |
1 | 1 | Covered | T128,T132 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T52,T53,T54 |
1 | 0 | Covered | T128,T132 |
1 | 1 | Covered | T52,T53,T54 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160294252 |
24 |
0 |
0 |
T52 |
5084 |
1 |
0 |
0 |
T53 |
15963 |
1 |
0 |
0 |
T54 |
9002 |
1 |
0 |
0 |
T55 |
2830 |
1 |
0 |
0 |
T58 |
5581 |
1 |
0 |
0 |
T59 |
11429 |
1 |
0 |
0 |
T83 |
11675 |
1 |
0 |
0 |
T121 |
2657 |
1 |
0 |
0 |
T122 |
4513 |
1 |
0 |
0 |
T129 |
4993 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
133821235 |
24 |
0 |
0 |
T52 |
20024 |
1 |
0 |
0 |
T53 |
3396 |
1 |
0 |
0 |
T54 |
8136 |
1 |
0 |
0 |
T55 |
3803 |
1 |
0 |
0 |
T58 |
5283 |
1 |
0 |
0 |
T59 |
2548 |
1 |
0 |
0 |
T83 |
2312 |
1 |
0 |
0 |
T121 |
2468 |
1 |
0 |
0 |
T122 |
1968 |
1 |
0 |
0 |
T129 |
1076 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T52,T53,T54 |
1 | 0 | Covered | T52,T53,T54 |
1 | 1 | Covered | T59,T133 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T52,T53,T54 |
1 | 0 | Covered | T59,T133 |
1 | 1 | Covered | T52,T53,T54 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160294252 |
29 |
0 |
0 |
T52 |
5084 |
1 |
0 |
0 |
T53 |
15963 |
1 |
0 |
0 |
T54 |
9002 |
2 |
0 |
0 |
T56 |
5029 |
1 |
0 |
0 |
T57 |
2591 |
1 |
0 |
0 |
T59 |
11429 |
4 |
0 |
0 |
T83 |
11675 |
1 |
0 |
0 |
T117 |
5610 |
1 |
0 |
0 |
T119 |
5853 |
1 |
0 |
0 |
T129 |
4993 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
571402078 |
29 |
0 |
0 |
T52 |
84739 |
1 |
0 |
0 |
T53 |
16455 |
1 |
0 |
0 |
T54 |
36010 |
2 |
0 |
0 |
T56 |
5239 |
1 |
0 |
0 |
T57 |
43196 |
1 |
0 |
0 |
T59 |
11906 |
4 |
0 |
0 |
T83 |
11675 |
1 |
0 |
0 |
T117 |
93508 |
1 |
0 |
0 |
T119 |
27872 |
1 |
0 |
0 |
T129 |
5202 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T54,T56,T59 |
1 | 0 | Covered | T54,T56,T59 |
1 | 1 | Covered | T56,T125 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T54,T56,T59 |
1 | 0 | Covered | T56,T125 |
1 | 1 | Covered | T54,T56,T59 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160294252 |
30 |
0 |
0 |
T54 |
9002 |
2 |
0 |
0 |
T56 |
5029 |
3 |
0 |
0 |
T59 |
11429 |
2 |
0 |
0 |
T83 |
11675 |
1 |
0 |
0 |
T117 |
5610 |
1 |
0 |
0 |
T119 |
5853 |
3 |
0 |
0 |
T125 |
9420 |
3 |
0 |
0 |
T128 |
2650 |
2 |
0 |
0 |
T129 |
4993 |
2 |
0 |
0 |
T134 |
6782 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
571402078 |
30 |
0 |
0 |
T54 |
36010 |
2 |
0 |
0 |
T56 |
5239 |
3 |
0 |
0 |
T59 |
11906 |
2 |
0 |
0 |
T83 |
11675 |
1 |
0 |
0 |
T117 |
93508 |
1 |
0 |
0 |
T119 |
27872 |
3 |
0 |
0 |
T125 |
9813 |
3 |
0 |
0 |
T128 |
9816 |
2 |
0 |
0 |
T129 |
5202 |
2 |
0 |
0 |
T134 |
13563 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T52,T53,T54 |
1 | 0 | Covered | T52,T53,T54 |
1 | 1 | Covered | T54,T58,T57 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T52,T53,T54 |
1 | 0 | Covered | T54,T58,T57 |
1 | 1 | Covered | T52,T53,T54 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160294252 |
32 |
0 |
0 |
T52 |
5084 |
2 |
0 |
0 |
T53 |
15963 |
1 |
0 |
0 |
T54 |
9002 |
2 |
0 |
0 |
T55 |
2830 |
1 |
0 |
0 |
T57 |
2591 |
3 |
0 |
0 |
T58 |
5581 |
2 |
0 |
0 |
T59 |
11429 |
1 |
0 |
0 |
T83 |
11675 |
3 |
0 |
0 |
T118 |
6660 |
1 |
0 |
0 |
T129 |
4993 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
274144053 |
32 |
0 |
0 |
T52 |
40676 |
2 |
0 |
0 |
T53 |
7899 |
1 |
0 |
0 |
T54 |
17285 |
2 |
0 |
0 |
T55 |
7992 |
1 |
0 |
0 |
T57 |
20734 |
3 |
0 |
0 |
T58 |
11163 |
2 |
0 |
0 |
T59 |
5715 |
1 |
0 |
0 |
T83 |
5604 |
3 |
0 |
0 |
T118 |
6660 |
1 |
0 |
0 |
T129 |
2497 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T54,T55,T58 |
1 | 0 | Covered | T54,T55,T58 |
1 | 1 | Covered | T58,T129,T133 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T54,T55,T58 |
1 | 0 | Covered | T58,T129,T133 |
1 | 1 | Covered | T54,T55,T58 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160294252 |
30 |
0 |
0 |
T54 |
9002 |
1 |
0 |
0 |
T55 |
2830 |
1 |
0 |
0 |
T58 |
5581 |
2 |
0 |
0 |
T59 |
11429 |
1 |
0 |
0 |
T83 |
11675 |
3 |
0 |
0 |
T117 |
5610 |
2 |
0 |
0 |
T118 |
6660 |
1 |
0 |
0 |
T121 |
2657 |
1 |
0 |
0 |
T127 |
6559 |
1 |
0 |
0 |
T129 |
4993 |
4 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
274144053 |
30 |
0 |
0 |
T54 |
17285 |
1 |
0 |
0 |
T55 |
7992 |
1 |
0 |
0 |
T58 |
11163 |
2 |
0 |
0 |
T59 |
5715 |
1 |
0 |
0 |
T83 |
5604 |
3 |
0 |
0 |
T117 |
44884 |
2 |
0 |
0 |
T118 |
6660 |
1 |
0 |
0 |
T121 |
5314 |
1 |
0 |
0 |
T127 |
3180 |
1 |
0 |
0 |
T129 |
2497 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
534026253 |
104509 |
0 |
0 |
T1 |
239530 |
95 |
0 |
0 |
T2 |
236707 |
101 |
0 |
0 |
T3 |
65153 |
29 |
0 |
0 |
T6 |
0 |
41 |
0 |
0 |
T7 |
0 |
54 |
0 |
0 |
T8 |
0 |
2045 |
0 |
0 |
T9 |
0 |
127 |
0 |
0 |
T13 |
3991 |
0 |
0 |
0 |
T14 |
3706 |
0 |
0 |
0 |
T15 |
3527 |
0 |
0 |
0 |
T16 |
2940 |
0 |
0 |
0 |
T17 |
1401 |
0 |
0 |
0 |
T18 |
2865 |
0 |
0 |
0 |
T19 |
88503 |
49 |
0 |
0 |
T23 |
0 |
15 |
0 |
0 |
T25 |
0 |
194 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19676524 |
103489 |
0 |
0 |
T1 |
513 |
95 |
0 |
0 |
T2 |
3456 |
101 |
0 |
0 |
T3 |
144 |
29 |
0 |
0 |
T6 |
0 |
41 |
0 |
0 |
T7 |
0 |
54 |
0 |
0 |
T8 |
0 |
2047 |
0 |
0 |
T9 |
0 |
127 |
0 |
0 |
T13 |
290 |
0 |
0 |
0 |
T14 |
270 |
0 |
0 |
0 |
T15 |
257 |
0 |
0 |
0 |
T16 |
214 |
0 |
0 |
0 |
T17 |
101 |
0 |
0 |
0 |
T18 |
208 |
0 |
0 |
0 |
T19 |
199 |
49 |
0 |
0 |
T23 |
0 |
15 |
0 |
0 |
T25 |
0 |
194 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
266300058 |
103115 |
0 |
0 |
T1 |
119739 |
95 |
0 |
0 |
T2 |
119981 |
101 |
0 |
0 |
T3 |
32564 |
29 |
0 |
0 |
T6 |
0 |
41 |
0 |
0 |
T7 |
0 |
54 |
0 |
0 |
T8 |
0 |
2034 |
0 |
0 |
T9 |
0 |
127 |
0 |
0 |
T13 |
1969 |
0 |
0 |
0 |
T14 |
1827 |
0 |
0 |
0 |
T15 |
1738 |
0 |
0 |
0 |
T16 |
1458 |
0 |
0 |
0 |
T17 |
664 |
0 |
0 |
0 |
T18 |
2246 |
0 |
0 |
0 |
T19 |
44205 |
49 |
0 |
0 |
T23 |
0 |
15 |
0 |
0 |
T25 |
0 |
194 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19676524 |
102100 |
0 |
0 |
T1 |
513 |
95 |
0 |
0 |
T2 |
3456 |
101 |
0 |
0 |
T3 |
144 |
29 |
0 |
0 |
T6 |
0 |
41 |
0 |
0 |
T7 |
0 |
54 |
0 |
0 |
T8 |
0 |
2036 |
0 |
0 |
T9 |
0 |
127 |
0 |
0 |
T13 |
290 |
0 |
0 |
0 |
T14 |
270 |
0 |
0 |
0 |
T15 |
257 |
0 |
0 |
0 |
T16 |
214 |
0 |
0 |
0 |
T17 |
101 |
0 |
0 |
0 |
T18 |
208 |
0 |
0 |
0 |
T19 |
199 |
49 |
0 |
0 |
T23 |
0 |
15 |
0 |
0 |
T25 |
0 |
194 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
133149421 |
101449 |
0 |
0 |
T1 |
59869 |
95 |
0 |
0 |
T2 |
59989 |
89 |
0 |
0 |
T3 |
16282 |
29 |
0 |
0 |
T6 |
0 |
41 |
0 |
0 |
T7 |
0 |
54 |
0 |
0 |
T8 |
0 |
2024 |
0 |
0 |
T9 |
0 |
127 |
0 |
0 |
T13 |
985 |
0 |
0 |
0 |
T14 |
914 |
0 |
0 |
0 |
T15 |
869 |
0 |
0 |
0 |
T16 |
729 |
0 |
0 |
0 |
T17 |
332 |
0 |
0 |
0 |
T18 |
1120 |
0 |
0 |
0 |
T19 |
22102 |
49 |
0 |
0 |
T23 |
0 |
15 |
0 |
0 |
T25 |
0 |
194 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19676524 |
100442 |
0 |
0 |
T1 |
513 |
95 |
0 |
0 |
T2 |
3456 |
89 |
0 |
0 |
T3 |
144 |
29 |
0 |
0 |
T6 |
0 |
41 |
0 |
0 |
T7 |
0 |
54 |
0 |
0 |
T8 |
0 |
2026 |
0 |
0 |
T9 |
0 |
127 |
0 |
0 |
T13 |
290 |
0 |
0 |
0 |
T14 |
270 |
0 |
0 |
0 |
T15 |
257 |
0 |
0 |
0 |
T16 |
214 |
0 |
0 |
0 |
T17 |
101 |
0 |
0 |
0 |
T18 |
208 |
0 |
0 |
0 |
T19 |
199 |
49 |
0 |
0 |
T23 |
0 |
15 |
0 |
0 |
T25 |
0 |
194 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
568506940 |
123844 |
0 |
0 |
T1 |
249518 |
95 |
0 |
0 |
T2 |
246579 |
87 |
0 |
0 |
T3 |
67869 |
29 |
0 |
0 |
T6 |
0 |
65 |
0 |
0 |
T7 |
0 |
54 |
0 |
0 |
T8 |
0 |
2650 |
0 |
0 |
T9 |
0 |
163 |
0 |
0 |
T13 |
4158 |
0 |
0 |
0 |
T14 |
3861 |
0 |
0 |
0 |
T15 |
3674 |
0 |
0 |
0 |
T16 |
3063 |
0 |
0 |
0 |
T17 |
1459 |
0 |
0 |
0 |
T18 |
2984 |
0 |
0 |
0 |
T19 |
92193 |
49 |
0 |
0 |
T23 |
0 |
51 |
0 |
0 |
T25 |
0 |
206 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
20052732 |
123421 |
0 |
0 |
T1 |
513 |
95 |
0 |
0 |
T2 |
3456 |
87 |
0 |
0 |
T3 |
144 |
29 |
0 |
0 |
T6 |
0 |
65 |
0 |
0 |
T7 |
0 |
54 |
0 |
0 |
T8 |
0 |
2650 |
0 |
0 |
T9 |
0 |
163 |
0 |
0 |
T13 |
290 |
0 |
0 |
0 |
T14 |
270 |
0 |
0 |
0 |
T15 |
257 |
0 |
0 |
0 |
T16 |
214 |
0 |
0 |
0 |
T17 |
101 |
0 |
0 |
0 |
T18 |
208 |
0 |
0 |
0 |
T19 |
199 |
49 |
0 |
0 |
T23 |
0 |
51 |
0 |
0 |
T25 |
0 |
206 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
272754415 |
121516 |
0 |
0 |
T1 |
119770 |
95 |
0 |
0 |
T2 |
118359 |
84 |
0 |
0 |
T3 |
32578 |
29 |
0 |
0 |
T6 |
0 |
77 |
0 |
0 |
T7 |
0 |
54 |
0 |
0 |
T8 |
0 |
2544 |
0 |
0 |
T9 |
0 |
175 |
0 |
0 |
T13 |
1995 |
0 |
0 |
0 |
T14 |
1853 |
0 |
0 |
0 |
T15 |
1763 |
0 |
0 |
0 |
T16 |
1470 |
0 |
0 |
0 |
T17 |
701 |
0 |
0 |
0 |
T18 |
1432 |
0 |
0 |
0 |
T19 |
44253 |
49 |
0 |
0 |
T23 |
0 |
50 |
0 |
0 |
T25 |
0 |
182 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
20054455 |
121453 |
0 |
0 |
T1 |
513 |
95 |
0 |
0 |
T2 |
3456 |
84 |
0 |
0 |
T3 |
144 |
29 |
0 |
0 |
T6 |
0 |
77 |
0 |
0 |
T7 |
0 |
54 |
0 |
0 |
T8 |
0 |
2544 |
0 |
0 |
T9 |
0 |
175 |
0 |
0 |
T13 |
290 |
0 |
0 |
0 |
T14 |
270 |
0 |
0 |
0 |
T15 |
257 |
0 |
0 |
0 |
T16 |
214 |
0 |
0 |
0 |
T17 |
101 |
0 |
0 |
0 |
T18 |
208 |
0 |
0 |
0 |
T19 |
199 |
49 |
0 |
0 |
T23 |
0 |
50 |
0 |
0 |
T25 |
0 |
182 |
0 |
0 |