Module Definition
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Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.66 96.24 80.88 91.53 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 83.59 94.90 76.09 88.37 75.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.66 96.24 80.88 91.53 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 83.59 94.90 76.09 88.37 75.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.66 96.24 80.88 91.53 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 83.59 94.90 76.09 88.37 75.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.66 96.24 80.88 91.53 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 83.59 94.90 76.09 88.37 75.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.66 96.24 80.88 91.53 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 83.59 94.90 76.09 88.37 75.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.92 100.00 91.67 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.39 100.00 93.55 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.92 100.00 91.67 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.39 100.00 93.55 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.92 100.00 91.67 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.39 100.00 93.55 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.92 100.00 91.67 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.39 100.00 93.55 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.92 100.00 91.67 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.39 100.00 93.55 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Module : prim_reg_cdc
TotalCoveredPercent
Conditions151386.67
Logical151386.67
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT22,T24,T27
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T1
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT4,T5,T1
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T1
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T4,T5,T1


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T1
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T4,T5,T1


Assert Coverage for Module : prim_reg_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1602942520 1446657 0 0
DstReqKnown_A 2147483647 2147483647 0 0
SrcAckBusyChk_A 1602942520 293493 0 0
SrcBusyKnown_A 1602942520 1576847710 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1602942520 1446657 0 0
T1 598830 1421 0 0
T2 394520 992 0 0
T3 332560 597 0 0
T6 0 495 0 0
T7 0 638 0 0
T13 9970 0 0 0
T14 18530 0 0 0
T15 36740 0 0 0
T16 25430 0 0 0
T17 14010 0 0 0
T18 22070 0 0 0
T19 912720 1390 0 0
T22 0 1494 0 0
T23 0 216 0 0
T24 0 696 0 0
T25 0 1056 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 1576852 1576044 0 0
T2 1563230 1560716 0 0
T4 32010 31064 0 0
T5 8308 7246 0 0
T13 26196 25570 0 0
T14 24322 23602 0 0
T15 23142 21970 0 0
T16 19320 18560 0 0
T17 9114 8006 0 0
T18 21294 20734 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1602942520 293493 0 0
T1 598830 420 0 0
T2 394520 320 0 0
T3 332560 120 0 0
T6 0 140 0 0
T7 0 200 0 0
T13 9970 0 0 0
T14 18530 0 0 0
T15 36740 0 0 0
T16 25430 0 0 0
T17 14010 0 0 0
T18 22070 0 0 0
T19 912720 160 0 0
T22 0 542 0 0
T23 0 60 0 0
T24 0 196 0 0
T25 0 300 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1602942520 1576847710 0 0
T1 598830 598500 0 0
T2 394520 393780 0 0
T4 9950 9620 0 0
T5 12940 11150 0 0
T13 9970 9700 0 0
T14 18530 17930 0 0
T15 36740 34760 0 0
T16 25430 24380 0 0
T17 14010 12110 0 0
T18 22070 21350 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
TotalCoveredPercent
Conditions141285.71
Logical141285.71
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T1
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT4,T5,T1
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T1
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T4,T5,T1


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T1
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 160294252 92182 0 0
DstReqKnown_A 536805478 532333614 0 0
SrcAckBusyChk_A 160294252 26572 0 0
SrcBusyKnown_A 160294252 157684771 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160294252 92182 0 0
T1 59883 105 0 0
T2 39452 82 0 0
T3 33256 42 0 0
T6 0 36 0 0
T7 0 54 0 0
T13 997 0 0 0
T14 1853 0 0 0
T15 3674 0 0 0
T16 2543 0 0 0
T17 1401 0 0 0
T18 2207 0 0 0
T19 91272 88 0 0
T22 0 94 0 0
T23 0 16 0 0
T24 0 34 0 0
T25 0 79 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 536805478 532333614 0 0
T1 239530 239395 0 0
T2 236707 236258 0 0
T4 4780 4618 0 0
T5 1268 1092 0 0
T13 3991 3884 0 0
T14 3706 3585 0 0
T15 3527 3337 0 0
T16 2940 2819 0 0
T17 1401 1211 0 0
T18 2865 2771 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160294252 26572 0 0
T1 59883 42 0 0
T2 39452 32 0 0
T3 33256 12 0 0
T6 0 14 0 0
T7 0 20 0 0
T13 997 0 0 0
T14 1853 0 0 0
T15 3674 0 0 0
T16 2543 0 0 0
T17 1401 0 0 0
T18 2207 0 0 0
T19 91272 16 0 0
T22 0 38 0 0
T23 0 6 0 0
T24 0 14 0 0
T25 0 30 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160294252 157684771 0 0
T1 59883 59850 0 0
T2 39452 39378 0 0
T4 995 962 0 0
T5 1294 1115 0 0
T13 997 970 0 0
T14 1853 1793 0 0
T15 3674 3476 0 0
T16 2543 2438 0 0
T17 1401 1211 0 0
T18 2207 2135 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
TotalCoveredPercent
Conditions141285.71
Logical141285.71
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T1
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT4,T5,T1
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T1
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T4,T5,T1


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T1
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 160294252 129595 0 0
DstReqKnown_A 267643652 266511169 0 0
SrcAckBusyChk_A 160294252 26572 0 0
SrcBusyKnown_A 160294252 157684771 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160294252 129595 0 0
T1 59883 147 0 0
T2 39452 100 0 0
T3 33256 61 0 0
T6 0 50 0 0
T7 0 64 0 0
T13 997 0 0 0
T14 1853 0 0 0
T15 3674 0 0 0
T16 2543 0 0 0
T17 1401 0 0 0
T18 2207 0 0 0
T19 91272 137 0 0
T22 0 94 0 0
T23 0 22 0 0
T24 0 49 0 0
T25 0 109 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 267643652 266511169 0 0
T1 119739 119698 0 0
T2 119981 119905 0 0
T4 2570 2529 0 0
T5 621 566 0 0
T13 1969 1942 0 0
T14 1827 1792 0 0
T15 1738 1669 0 0
T16 1458 1410 0 0
T17 664 616 0 0
T18 2246 2218 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160294252 26572 0 0
T1 59883 42 0 0
T2 39452 32 0 0
T3 33256 12 0 0
T6 0 14 0 0
T7 0 20 0 0
T13 997 0 0 0
T14 1853 0 0 0
T15 3674 0 0 0
T16 2543 0 0 0
T17 1401 0 0 0
T18 2207 0 0 0
T19 91272 16 0 0
T22 0 38 0 0
T23 0 6 0 0
T24 0 14 0 0
T25 0 30 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160294252 157684771 0 0
T1 59883 59850 0 0
T2 39452 39378 0 0
T4 995 962 0 0
T5 1294 1115 0 0
T13 997 970 0 0
T14 1853 1793 0 0
T15 3674 3476 0 0
T16 2543 2438 0 0
T17 1401 1211 0 0
T18 2207 2135 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
TotalCoveredPercent
Conditions141285.71
Logical141285.71
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T1
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT4,T5,T1
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T1
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T4,T5,T1


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T1
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 160294252 204954 0 0
DstReqKnown_A 133821235 133255088 0 0
SrcAckBusyChk_A 160294252 26572 0 0
SrcBusyKnown_A 160294252 157684771 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160294252 204954 0 0
T1 59883 209 0 0
T2 39452 132 0 0
T3 33256 98 0 0
T6 0 73 0 0
T7 0 85 0 0
T13 997 0 0 0
T14 1853 0 0 0
T15 3674 0 0 0
T16 2543 0 0 0
T17 1401 0 0 0
T18 2207 0 0 0
T19 91272 237 0 0
T22 0 130 0 0
T23 0 32 0 0
T24 0 71 0 0
T25 0 153 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 133821235 133255088 0 0
T1 59869 59848 0 0
T2 59989 59951 0 0
T4 1285 1264 0 0
T5 311 283 0 0
T13 985 971 0 0
T14 914 897 0 0
T15 869 834 0 0
T16 729 705 0 0
T17 332 308 0 0
T18 1120 1106 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160294252 26572 0 0
T1 59883 42 0 0
T2 39452 32 0 0
T3 33256 12 0 0
T6 0 14 0 0
T7 0 20 0 0
T13 997 0 0 0
T14 1853 0 0 0
T15 3674 0 0 0
T16 2543 0 0 0
T17 1401 0 0 0
T18 2207 0 0 0
T19 91272 16 0 0
T22 0 38 0 0
T23 0 6 0 0
T24 0 14 0 0
T25 0 30 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160294252 157684771 0 0
T1 59883 59850 0 0
T2 39452 39378 0 0
T4 995 962 0 0
T5 1294 1115 0 0
T13 997 970 0 0
T14 1853 1793 0 0
T15 3674 3476 0 0
T16 2543 2438 0 0
T17 1401 1211 0 0
T18 2207 2135 0 0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
TotalCoveredPercent
Conditions141285.71
Logical141285.71
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T1
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT4,T5,T1
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T1
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T4,T5,T1


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T1
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 160294252 90457 0 0
DstReqKnown_A 571402078 566659110 0 0
SrcAckBusyChk_A 160294252 26572 0 0
SrcBusyKnown_A 160294252 157684771 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160294252 90457 0 0
T1 59883 105 0 0
T2 39452 82 0 0
T3 33256 42 0 0
T6 0 36 0 0
T7 0 54 0 0
T13 997 0 0 0
T14 1853 0 0 0
T15 3674 0 0 0
T16 2543 0 0 0
T17 1401 0 0 0
T18 2207 0 0 0
T19 91272 86 0 0
T22 0 94 0 0
T23 0 16 0 0
T24 0 34 0 0
T25 0 76 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 571402078 566659110 0 0
T1 249518 249378 0 0
T2 246579 246109 0 0
T4 4980 4811 0 0
T5 1321 1137 0 0
T13 4158 4046 0 0
T14 3861 3734 0 0
T15 3674 3476 0 0
T16 3063 2937 0 0
T17 1459 1262 0 0
T18 2984 2887 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160294252 26572 0 0
T1 59883 42 0 0
T2 39452 32 0 0
T3 33256 12 0 0
T6 0 14 0 0
T7 0 20 0 0
T13 997 0 0 0
T14 1853 0 0 0
T15 3674 0 0 0
T16 2543 0 0 0
T17 1401 0 0 0
T18 2207 0 0 0
T19 91272 16 0 0
T22 0 38 0 0
T23 0 6 0 0
T24 0 14 0 0
T25 0 30 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160294252 157684771 0 0
T1 59883 59850 0 0
T2 39452 39378 0 0
T4 995 962 0 0
T5 1294 1115 0 0
T13 997 970 0 0
T14 1853 1793 0 0
T15 3674 3476 0 0
T16 2543 2438 0 0
T17 1401 1211 0 0
T18 2207 2135 0 0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
TotalCoveredPercent
Conditions141285.71
Logical141285.71
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T1
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT4,T5,T1
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T1
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T4,T5,T1


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T1
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 160294252 127762 0 0
DstReqKnown_A 274144053 271861942 0 0
SrcAckBusyChk_A 160294252 26086 0 0
SrcBusyKnown_A 160294252 157684771 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160294252 127762 0 0
T1 59883 147 0 0
T2 39452 100 0 0
T3 33256 60 0 0
T6 0 50 0 0
T7 0 65 0 0
T13 997 0 0 0
T14 1853 0 0 0
T15 3674 0 0 0
T16 2543 0 0 0
T17 1401 0 0 0
T18 2207 0 0 0
T19 91272 144 0 0
T22 0 65 0 0
T23 0 22 0 0
T24 0 32 0 0
T25 0 109 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 274144053 271861942 0 0
T1 119770 119703 0 0
T2 118359 118135 0 0
T4 2390 2310 0 0
T5 633 545 0 0
T13 1995 1942 0 0
T14 1853 1793 0 0
T15 1763 1669 0 0
T16 1470 1409 0 0
T17 701 606 0 0
T18 1432 1385 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160294252 26086 0 0
T1 59883 42 0 0
T2 39452 32 0 0
T3 33256 12 0 0
T6 0 14 0 0
T7 0 20 0 0
T13 997 0 0 0
T14 1853 0 0 0
T15 3674 0 0 0
T16 2543 0 0 0
T17 1401 0 0 0
T18 2207 0 0 0
T19 91272 16 0 0
T22 0 19 0 0
T23 0 6 0 0
T24 0 7 0 0
T25 0 30 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160294252 157684771 0 0
T1 59883 59850 0 0
T2 39452 39378 0 0
T4 995 962 0 0
T5 1294 1115 0 0
T13 997 970 0 0
T14 1853 1793 0 0
T15 3674 3476 0 0
T16 2543 2438 0 0
T17 1401 1211 0 0
T18 2207 2135 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
TotalCoveredPercent
Conditions121191.67
Logical121191.67
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT22,T24,T27
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T1
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT4,T5,T1
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T1
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T4,T5,T1


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T1
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 160294252 114364 0 0
DstReqKnown_A 536805478 532333614 0 0
SrcAckBusyChk_A 160294252 32451 0 0
SrcBusyKnown_A 160294252 157684771 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160294252 114364 0 0
T1 59883 104 0 0
T2 39452 82 0 0
T3 33256 41 0 0
T6 0 37 0 0
T7 0 53 0 0
T13 997 0 0 0
T14 1853 0 0 0
T15 3674 0 0 0
T16 2543 0 0 0
T17 1401 0 0 0
T18 2207 0 0 0
T19 91272 88 0 0
T22 0 190 0 0
T23 0 16 0 0
T24 0 72 0 0
T25 0 80 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 536805478 532333614 0 0
T1 239530 239395 0 0
T2 236707 236258 0 0
T4 4780 4618 0 0
T5 1268 1092 0 0
T13 3991 3884 0 0
T14 3706 3585 0 0
T15 3527 3337 0 0
T16 2940 2819 0 0
T17 1401 1211 0 0
T18 2865 2771 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160294252 32451 0 0
T1 59883 42 0 0
T2 39452 32 0 0
T3 33256 12 0 0
T6 0 14 0 0
T7 0 20 0 0
T13 997 0 0 0
T14 1853 0 0 0
T15 3674 0 0 0
T16 2543 0 0 0
T17 1401 0 0 0
T18 2207 0 0 0
T19 91272 16 0 0
T22 0 76 0 0
T23 0 6 0 0
T24 0 28 0 0
T25 0 30 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160294252 157684771 0 0
T1 59883 59850 0 0
T2 39452 39378 0 0
T4 995 962 0 0
T5 1294 1115 0 0
T13 997 970 0 0
T14 1853 1793 0 0
T15 3674 3476 0 0
T16 2543 2438 0 0
T17 1401 1211 0 0
T18 2207 2135 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
TotalCoveredPercent
Conditions121191.67
Logical121191.67
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT22,T24,T27
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T1
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT4,T5,T1
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T1
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T4,T5,T1


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T1
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 160294252 160523 0 0
DstReqKnown_A 267643652 266511169 0 0
SrcAckBusyChk_A 160294252 32205 0 0
SrcBusyKnown_A 160294252 157684771 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160294252 160523 0 0
T1 59883 146 0 0
T2 39452 100 0 0
T3 33256 60 0 0
T6 0 51 0 0
T7 0 65 0 0
T13 997 0 0 0
T14 1853 0 0 0
T15 3674 0 0 0
T16 2543 0 0 0
T17 1401 0 0 0
T18 2207 0 0 0
T19 91272 141 0 0
T22 0 190 0 0
T23 0 22 0 0
T24 0 99 0 0
T25 0 109 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 267643652 266511169 0 0
T1 119739 119698 0 0
T2 119981 119905 0 0
T4 2570 2529 0 0
T5 621 566 0 0
T13 1969 1942 0 0
T14 1827 1792 0 0
T15 1738 1669 0 0
T16 1458 1410 0 0
T17 664 616 0 0
T18 2246 2218 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160294252 32205 0 0
T1 59883 42 0 0
T2 39452 32 0 0
T3 33256 12 0 0
T6 0 14 0 0
T7 0 20 0 0
T13 997 0 0 0
T14 1853 0 0 0
T15 3674 0 0 0
T16 2543 0 0 0
T17 1401 0 0 0
T18 2207 0 0 0
T19 91272 16 0 0
T22 0 76 0 0
T23 0 6 0 0
T24 0 28 0 0
T25 0 30 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160294252 157684771 0 0
T1 59883 59850 0 0
T2 39452 39378 0 0
T4 995 962 0 0
T5 1294 1115 0 0
T13 997 970 0 0
T14 1853 1793 0 0
T15 3674 3476 0 0
T16 2543 2438 0 0
T17 1401 1211 0 0
T18 2207 2135 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
TotalCoveredPercent
Conditions121191.67
Logical121191.67
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT22,T24,T27
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T1
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT4,T5,T1
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T1
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T4,T5,T1


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T1
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 160294252 254799 0 0
DstReqKnown_A 133821235 133255088 0 0
SrcAckBusyChk_A 160294252 32183 0 0
SrcBusyKnown_A 160294252 157684771 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160294252 254799 0 0
T1 59883 208 0 0
T2 39452 132 0 0
T3 33256 94 0 0
T6 0 74 0 0
T7 0 84 0 0
T13 997 0 0 0
T14 1853 0 0 0
T15 3674 0 0 0
T16 2543 0 0 0
T17 1401 0 0 0
T18 2207 0 0 0
T19 91272 244 0 0
T22 0 257 0 0
T23 0 32 0 0
T24 0 140 0 0
T25 0 156 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 133821235 133255088 0 0
T1 59869 59848 0 0
T2 59989 59951 0 0
T4 1285 1264 0 0
T5 311 283 0 0
T13 985 971 0 0
T14 914 897 0 0
T15 869 834 0 0
T16 729 705 0 0
T17 332 308 0 0
T18 1120 1106 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160294252 32183 0 0
T1 59883 42 0 0
T2 39452 32 0 0
T3 33256 12 0 0
T6 0 14 0 0
T7 0 20 0 0
T13 997 0 0 0
T14 1853 0 0 0
T15 3674 0 0 0
T16 2543 0 0 0
T17 1401 0 0 0
T18 2207 0 0 0
T19 91272 16 0 0
T22 0 76 0 0
T23 0 6 0 0
T24 0 28 0 0
T25 0 30 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160294252 157684771 0 0
T1 59883 59850 0 0
T2 39452 39378 0 0
T4 995 962 0 0
T5 1294 1115 0 0
T13 997 970 0 0
T14 1853 1793 0 0
T15 3674 3476 0 0
T16 2543 2438 0 0
T17 1401 1211 0 0
T18 2207 2135 0 0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
TotalCoveredPercent
Conditions121191.67
Logical121191.67
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT22,T24,T27
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T1
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT4,T5,T1
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T1
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T4,T5,T1


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T1
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 160294252 111215 0 0
DstReqKnown_A 571402078 566659110 0 0
SrcAckBusyChk_A 160294252 32136 0 0
SrcBusyKnown_A 160294252 157684771 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160294252 111215 0 0
T1 59883 104 0 0
T2 39452 82 0 0
T3 33256 41 0 0
T6 0 37 0 0
T7 0 53 0 0
T13 997 0 0 0
T14 1853 0 0 0
T15 3674 0 0 0
T16 2543 0 0 0
T17 1401 0 0 0
T18 2207 0 0 0
T19 91272 86 0 0
T22 0 190 0 0
T23 0 16 0 0
T24 0 69 0 0
T25 0 76 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 571402078 566659110 0 0
T1 249518 249378 0 0
T2 246579 246109 0 0
T4 4980 4811 0 0
T5 1321 1137 0 0
T13 4158 4046 0 0
T14 3861 3734 0 0
T15 3674 3476 0 0
T16 3063 2937 0 0
T17 1459 1262 0 0
T18 2984 2887 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160294252 32136 0 0
T1 59883 42 0 0
T2 39452 32 0 0
T3 33256 12 0 0
T6 0 14 0 0
T7 0 20 0 0
T13 997 0 0 0
T14 1853 0 0 0
T15 3674 0 0 0
T16 2543 0 0 0
T17 1401 0 0 0
T18 2207 0 0 0
T19 91272 16 0 0
T22 0 76 0 0
T23 0 6 0 0
T24 0 28 0 0
T25 0 30 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160294252 157684771 0 0
T1 59883 59850 0 0
T2 39452 39378 0 0
T4 995 962 0 0
T5 1294 1115 0 0
T13 997 970 0 0
T14 1853 1793 0 0
T15 3674 3476 0 0
T16 2543 2438 0 0
T17 1401 1211 0 0
T18 2207 2135 0 0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
TotalCoveredPercent
Conditions121191.67
Logical121191.67
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT22,T24,T27
10CoveredT1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T1
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT4,T5,T1
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T1
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T4,T5,T1


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T1
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 160294252 160806 0 0
DstReqKnown_A 274144053 271861942 0 0
SrcAckBusyChk_A 160294252 32144 0 0
SrcBusyKnown_A 160294252 157684771 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160294252 160806 0 0
T1 59883 146 0 0
T2 39452 100 0 0
T3 33256 58 0 0
T6 0 51 0 0
T7 0 61 0 0
T13 997 0 0 0
T14 1853 0 0 0
T15 3674 0 0 0
T16 2543 0 0 0
T17 1401 0 0 0
T18 2207 0 0 0
T19 91272 139 0 0
T22 0 190 0 0
T23 0 22 0 0
T24 0 96 0 0
T25 0 109 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 274144053 271861942 0 0
T1 119770 119703 0 0
T2 118359 118135 0 0
T4 2390 2310 0 0
T5 633 545 0 0
T13 1995 1942 0 0
T14 1853 1793 0 0
T15 1763 1669 0 0
T16 1470 1409 0 0
T17 701 606 0 0
T18 1432 1385 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160294252 32144 0 0
T1 59883 42 0 0
T2 39452 32 0 0
T3 33256 12 0 0
T6 0 14 0 0
T7 0 20 0 0
T13 997 0 0 0
T14 1853 0 0 0
T15 3674 0 0 0
T16 2543 0 0 0
T17 1401 0 0 0
T18 2207 0 0 0
T19 91272 16 0 0
T22 0 67 0 0
T23 0 6 0 0
T24 0 21 0 0
T25 0 30 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160294252 157684771 0 0
T1 59883 59850 0 0
T2 39452 39378 0 0
T4 995 962 0 0
T5 1294 1115 0 0
T13 997 970 0 0
T14 1853 1793 0 0
T15 3674 3476 0 0
T16 2543 2438 0 0
T17 1401 1211 0 0
T18 2207 2135 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%