Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Module :
prim_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
934052 |
0 |
0 |
T1 |
823075 |
382 |
0 |
0 |
T2 |
2520908 |
11259 |
0 |
0 |
T3 |
0 |
10395 |
0 |
0 |
T4 |
212078 |
90 |
0 |
0 |
T10 |
0 |
564 |
0 |
0 |
T11 |
0 |
5771 |
0 |
0 |
T12 |
0 |
392 |
0 |
0 |
T17 |
13217 |
0 |
0 |
0 |
T18 |
58746 |
0 |
0 |
0 |
T19 |
11756 |
0 |
0 |
0 |
T20 |
38504 |
0 |
0 |
0 |
T21 |
21538 |
0 |
0 |
0 |
T22 |
9417 |
0 |
0 |
0 |
T23 |
19324 |
0 |
0 |
0 |
T24 |
0 |
190 |
0 |
0 |
T25 |
0 |
20 |
0 |
0 |
T28 |
0 |
199 |
0 |
0 |
T29 |
0 |
151 |
0 |
0 |
T30 |
0 |
352 |
0 |
0 |
T31 |
0 |
140 |
0 |
0 |
T60 |
16412 |
3 |
0 |
0 |
T62 |
21768 |
2 |
0 |
0 |
T64 |
16088 |
1 |
0 |
0 |
T65 |
32454 |
1 |
0 |
0 |
T66 |
4184 |
0 |
0 |
0 |
T67 |
14078 |
1 |
0 |
0 |
T68 |
5070 |
0 |
0 |
0 |
T69 |
8532 |
0 |
0 |
0 |
T75 |
0 |
400 |
0 |
0 |
T76 |
0 |
272 |
0 |
0 |
T77 |
0 |
1 |
0 |
0 |
T117 |
22114 |
0 |
0 |
0 |
T118 |
8206 |
0 |
0 |
0 |
T119 |
5730 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
929496 |
0 |
0 |
T1 |
432844 |
382 |
0 |
0 |
T2 |
2470975 |
10550 |
0 |
0 |
T3 |
0 |
10186 |
0 |
0 |
T4 |
70391 |
90 |
0 |
0 |
T10 |
0 |
564 |
0 |
0 |
T11 |
0 |
5771 |
0 |
0 |
T12 |
0 |
392 |
0 |
0 |
T17 |
5590 |
0 |
0 |
0 |
T18 |
14799 |
0 |
0 |
0 |
T19 |
6724 |
0 |
0 |
0 |
T20 |
11749 |
0 |
0 |
0 |
T21 |
6947 |
0 |
0 |
0 |
T22 |
3750 |
0 |
0 |
0 |
T23 |
8026 |
0 |
0 |
0 |
T24 |
0 |
190 |
0 |
0 |
T25 |
0 |
20 |
0 |
0 |
T28 |
0 |
199 |
0 |
0 |
T29 |
0 |
151 |
0 |
0 |
T30 |
0 |
352 |
0 |
0 |
T31 |
0 |
140 |
0 |
0 |
T60 |
7112 |
3 |
0 |
0 |
T62 |
19266 |
2 |
0 |
0 |
T64 |
49930 |
1 |
0 |
0 |
T65 |
14494 |
1 |
0 |
0 |
T66 |
19208 |
0 |
0 |
0 |
T67 |
6418 |
1 |
0 |
0 |
T68 |
23169 |
0 |
0 |
0 |
T69 |
3745 |
0 |
0 |
0 |
T75 |
0 |
400 |
0 |
0 |
T76 |
0 |
272 |
0 |
0 |
T77 |
0 |
1 |
0 |
0 |
T117 |
9160 |
0 |
0 |
0 |
T118 |
7142 |
0 |
0 |
0 |
T119 |
2474 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
422368728 |
24849 |
0 |
0 |
T1 |
171746 |
30 |
0 |
0 |
T2 |
112372 |
569 |
0 |
0 |
T3 |
0 |
527 |
0 |
0 |
T4 |
62037 |
18 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T17 |
3019 |
0 |
0 |
0 |
T18 |
15137 |
0 |
0 |
0 |
T19 |
2367 |
0 |
0 |
0 |
T20 |
8973 |
0 |
0 |
0 |
T21 |
5146 |
0 |
0 |
0 |
T22 |
2255 |
0 |
0 |
0 |
T23 |
4295 |
0 |
0 |
0 |
T24 |
0 |
38 |
0 |
0 |
T28 |
0 |
38 |
0 |
0 |
T29 |
0 |
30 |
0 |
0 |
T30 |
0 |
16 |
0 |
0 |
T31 |
0 |
28 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153651632 |
24849 |
0 |
0 |
T1 |
171746 |
30 |
0 |
0 |
T2 |
323953 |
569 |
0 |
0 |
T3 |
0 |
527 |
0 |
0 |
T4 |
26496 |
18 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T17 |
1572 |
0 |
0 |
0 |
T18 |
1419 |
0 |
0 |
0 |
T19 |
2367 |
0 |
0 |
0 |
T20 |
1963 |
0 |
0 |
0 |
T21 |
1339 |
0 |
0 |
0 |
T22 |
999 |
0 |
0 |
0 |
T23 |
2192 |
0 |
0 |
0 |
T24 |
0 |
38 |
0 |
0 |
T28 |
0 |
38 |
0 |
0 |
T29 |
0 |
30 |
0 |
0 |
T30 |
0 |
16 |
0 |
0 |
T31 |
0 |
28 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
422368728 |
30640 |
0 |
0 |
T1 |
171746 |
30 |
0 |
0 |
T2 |
112372 |
579 |
0 |
0 |
T3 |
0 |
538 |
0 |
0 |
T4 |
62037 |
36 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T17 |
3019 |
0 |
0 |
0 |
T18 |
15137 |
0 |
0 |
0 |
T19 |
2367 |
0 |
0 |
0 |
T20 |
8973 |
0 |
0 |
0 |
T21 |
5146 |
0 |
0 |
0 |
T22 |
2255 |
0 |
0 |
0 |
T23 |
4295 |
0 |
0 |
0 |
T24 |
0 |
76 |
0 |
0 |
T28 |
0 |
76 |
0 |
0 |
T29 |
0 |
60 |
0 |
0 |
T30 |
0 |
16 |
0 |
0 |
T31 |
0 |
56 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153651632 |
30657 |
0 |
0 |
T1 |
171746 |
30 |
0 |
0 |
T2 |
323953 |
579 |
0 |
0 |
T3 |
0 |
538 |
0 |
0 |
T4 |
26496 |
36 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T17 |
1572 |
0 |
0 |
0 |
T18 |
1419 |
0 |
0 |
0 |
T19 |
2367 |
0 |
0 |
0 |
T20 |
1963 |
0 |
0 |
0 |
T21 |
1339 |
0 |
0 |
0 |
T22 |
999 |
0 |
0 |
0 |
T23 |
2192 |
0 |
0 |
0 |
T24 |
0 |
76 |
0 |
0 |
T28 |
0 |
76 |
0 |
0 |
T29 |
0 |
60 |
0 |
0 |
T30 |
0 |
16 |
0 |
0 |
T31 |
0 |
56 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153651632 |
30627 |
0 |
0 |
T1 |
171746 |
30 |
0 |
0 |
T2 |
323953 |
579 |
0 |
0 |
T3 |
0 |
538 |
0 |
0 |
T4 |
26496 |
36 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T17 |
1572 |
0 |
0 |
0 |
T18 |
1419 |
0 |
0 |
0 |
T19 |
2367 |
0 |
0 |
0 |
T20 |
1963 |
0 |
0 |
0 |
T21 |
1339 |
0 |
0 |
0 |
T22 |
999 |
0 |
0 |
0 |
T23 |
2192 |
0 |
0 |
0 |
T24 |
0 |
76 |
0 |
0 |
T28 |
0 |
76 |
0 |
0 |
T29 |
0 |
60 |
0 |
0 |
T30 |
0 |
16 |
0 |
0 |
T31 |
0 |
56 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
422368728 |
30642 |
0 |
0 |
T1 |
171746 |
30 |
0 |
0 |
T2 |
112372 |
579 |
0 |
0 |
T3 |
0 |
538 |
0 |
0 |
T4 |
62037 |
36 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T17 |
3019 |
0 |
0 |
0 |
T18 |
15137 |
0 |
0 |
0 |
T19 |
2367 |
0 |
0 |
0 |
T20 |
8973 |
0 |
0 |
0 |
T21 |
5146 |
0 |
0 |
0 |
T22 |
2255 |
0 |
0 |
0 |
T23 |
4295 |
0 |
0 |
0 |
T24 |
0 |
76 |
0 |
0 |
T28 |
0 |
76 |
0 |
0 |
T29 |
0 |
60 |
0 |
0 |
T30 |
0 |
16 |
0 |
0 |
T31 |
0 |
56 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
210371220 |
24849 |
0 |
0 |
T1 |
85908 |
30 |
0 |
0 |
T2 |
561675 |
569 |
0 |
0 |
T3 |
0 |
527 |
0 |
0 |
T4 |
16835 |
18 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T17 |
1566 |
0 |
0 |
0 |
T18 |
7549 |
0 |
0 |
0 |
T19 |
1302 |
0 |
0 |
0 |
T20 |
5207 |
0 |
0 |
0 |
T21 |
2769 |
0 |
0 |
0 |
T22 |
1088 |
0 |
0 |
0 |
T23 |
2390 |
0 |
0 |
0 |
T24 |
0 |
38 |
0 |
0 |
T28 |
0 |
38 |
0 |
0 |
T29 |
0 |
30 |
0 |
0 |
T30 |
0 |
16 |
0 |
0 |
T31 |
0 |
28 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153651632 |
24849 |
0 |
0 |
T1 |
171746 |
30 |
0 |
0 |
T2 |
323953 |
569 |
0 |
0 |
T3 |
0 |
527 |
0 |
0 |
T4 |
26496 |
18 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T17 |
1572 |
0 |
0 |
0 |
T18 |
1419 |
0 |
0 |
0 |
T19 |
2367 |
0 |
0 |
0 |
T20 |
1963 |
0 |
0 |
0 |
T21 |
1339 |
0 |
0 |
0 |
T22 |
999 |
0 |
0 |
0 |
T23 |
2192 |
0 |
0 |
0 |
T24 |
0 |
38 |
0 |
0 |
T28 |
0 |
38 |
0 |
0 |
T29 |
0 |
30 |
0 |
0 |
T30 |
0 |
16 |
0 |
0 |
T31 |
0 |
28 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
210371220 |
30641 |
0 |
0 |
T1 |
85908 |
30 |
0 |
0 |
T2 |
561675 |
579 |
0 |
0 |
T3 |
0 |
538 |
0 |
0 |
T4 |
16835 |
36 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T17 |
1566 |
0 |
0 |
0 |
T18 |
7549 |
0 |
0 |
0 |
T19 |
1302 |
0 |
0 |
0 |
T20 |
5207 |
0 |
0 |
0 |
T21 |
2769 |
0 |
0 |
0 |
T22 |
1088 |
0 |
0 |
0 |
T23 |
2390 |
0 |
0 |
0 |
T24 |
0 |
76 |
0 |
0 |
T28 |
0 |
76 |
0 |
0 |
T29 |
0 |
60 |
0 |
0 |
T30 |
0 |
16 |
0 |
0 |
T31 |
0 |
56 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153651632 |
30661 |
0 |
0 |
T1 |
171746 |
30 |
0 |
0 |
T2 |
323953 |
579 |
0 |
0 |
T3 |
0 |
538 |
0 |
0 |
T4 |
26496 |
36 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T17 |
1572 |
0 |
0 |
0 |
T18 |
1419 |
0 |
0 |
0 |
T19 |
2367 |
0 |
0 |
0 |
T20 |
1963 |
0 |
0 |
0 |
T21 |
1339 |
0 |
0 |
0 |
T22 |
999 |
0 |
0 |
0 |
T23 |
2192 |
0 |
0 |
0 |
T24 |
0 |
76 |
0 |
0 |
T28 |
0 |
76 |
0 |
0 |
T29 |
0 |
60 |
0 |
0 |
T30 |
0 |
16 |
0 |
0 |
T31 |
0 |
56 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153651632 |
30638 |
0 |
0 |
T1 |
171746 |
30 |
0 |
0 |
T2 |
323953 |
579 |
0 |
0 |
T3 |
0 |
538 |
0 |
0 |
T4 |
26496 |
36 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T17 |
1572 |
0 |
0 |
0 |
T18 |
1419 |
0 |
0 |
0 |
T19 |
2367 |
0 |
0 |
0 |
T20 |
1963 |
0 |
0 |
0 |
T21 |
1339 |
0 |
0 |
0 |
T22 |
999 |
0 |
0 |
0 |
T23 |
2192 |
0 |
0 |
0 |
T24 |
0 |
76 |
0 |
0 |
T28 |
0 |
76 |
0 |
0 |
T29 |
0 |
60 |
0 |
0 |
T30 |
0 |
16 |
0 |
0 |
T31 |
0 |
56 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
210371220 |
30643 |
0 |
0 |
T1 |
85908 |
30 |
0 |
0 |
T2 |
561675 |
579 |
0 |
0 |
T3 |
0 |
538 |
0 |
0 |
T4 |
16835 |
36 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T17 |
1566 |
0 |
0 |
0 |
T18 |
7549 |
0 |
0 |
0 |
T19 |
1302 |
0 |
0 |
0 |
T20 |
5207 |
0 |
0 |
0 |
T21 |
2769 |
0 |
0 |
0 |
T22 |
1088 |
0 |
0 |
0 |
T23 |
2390 |
0 |
0 |
0 |
T24 |
0 |
76 |
0 |
0 |
T28 |
0 |
76 |
0 |
0 |
T29 |
0 |
60 |
0 |
0 |
T30 |
0 |
16 |
0 |
0 |
T31 |
0 |
56 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
105185012 |
24849 |
0 |
0 |
T1 |
42951 |
30 |
0 |
0 |
T2 |
280836 |
569 |
0 |
0 |
T3 |
0 |
527 |
0 |
0 |
T4 |
8417 |
18 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T17 |
782 |
0 |
0 |
0 |
T18 |
3775 |
0 |
0 |
0 |
T19 |
650 |
0 |
0 |
0 |
T20 |
2601 |
0 |
0 |
0 |
T21 |
1385 |
0 |
0 |
0 |
T22 |
544 |
0 |
0 |
0 |
T23 |
1194 |
0 |
0 |
0 |
T24 |
0 |
38 |
0 |
0 |
T28 |
0 |
38 |
0 |
0 |
T29 |
0 |
30 |
0 |
0 |
T30 |
0 |
16 |
0 |
0 |
T31 |
0 |
28 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153651632 |
24849 |
0 |
0 |
T1 |
171746 |
30 |
0 |
0 |
T2 |
323953 |
569 |
0 |
0 |
T3 |
0 |
527 |
0 |
0 |
T4 |
26496 |
18 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T17 |
1572 |
0 |
0 |
0 |
T18 |
1419 |
0 |
0 |
0 |
T19 |
2367 |
0 |
0 |
0 |
T20 |
1963 |
0 |
0 |
0 |
T21 |
1339 |
0 |
0 |
0 |
T22 |
999 |
0 |
0 |
0 |
T23 |
2192 |
0 |
0 |
0 |
T24 |
0 |
38 |
0 |
0 |
T28 |
0 |
38 |
0 |
0 |
T29 |
0 |
30 |
0 |
0 |
T30 |
0 |
16 |
0 |
0 |
T31 |
0 |
28 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
105185012 |
30722 |
0 |
0 |
T1 |
42951 |
30 |
0 |
0 |
T2 |
280836 |
579 |
0 |
0 |
T3 |
0 |
538 |
0 |
0 |
T4 |
8417 |
36 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T17 |
782 |
0 |
0 |
0 |
T18 |
3775 |
0 |
0 |
0 |
T19 |
650 |
0 |
0 |
0 |
T20 |
2601 |
0 |
0 |
0 |
T21 |
1385 |
0 |
0 |
0 |
T22 |
544 |
0 |
0 |
0 |
T23 |
1194 |
0 |
0 |
0 |
T24 |
0 |
76 |
0 |
0 |
T28 |
0 |
76 |
0 |
0 |
T29 |
0 |
60 |
0 |
0 |
T30 |
0 |
16 |
0 |
0 |
T31 |
0 |
56 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153651632 |
30756 |
0 |
0 |
T1 |
171746 |
30 |
0 |
0 |
T2 |
323953 |
579 |
0 |
0 |
T3 |
0 |
538 |
0 |
0 |
T4 |
26496 |
36 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T17 |
1572 |
0 |
0 |
0 |
T18 |
1419 |
0 |
0 |
0 |
T19 |
2367 |
0 |
0 |
0 |
T20 |
1963 |
0 |
0 |
0 |
T21 |
1339 |
0 |
0 |
0 |
T22 |
999 |
0 |
0 |
0 |
T23 |
2192 |
0 |
0 |
0 |
T24 |
0 |
76 |
0 |
0 |
T28 |
0 |
76 |
0 |
0 |
T29 |
0 |
60 |
0 |
0 |
T30 |
0 |
16 |
0 |
0 |
T31 |
0 |
56 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153651632 |
30717 |
0 |
0 |
T1 |
171746 |
30 |
0 |
0 |
T2 |
323953 |
579 |
0 |
0 |
T3 |
0 |
538 |
0 |
0 |
T4 |
26496 |
36 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T17 |
1572 |
0 |
0 |
0 |
T18 |
1419 |
0 |
0 |
0 |
T19 |
2367 |
0 |
0 |
0 |
T20 |
1963 |
0 |
0 |
0 |
T21 |
1339 |
0 |
0 |
0 |
T22 |
999 |
0 |
0 |
0 |
T23 |
2192 |
0 |
0 |
0 |
T24 |
0 |
76 |
0 |
0 |
T28 |
0 |
76 |
0 |
0 |
T29 |
0 |
60 |
0 |
0 |
T30 |
0 |
16 |
0 |
0 |
T31 |
0 |
56 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
105185012 |
30727 |
0 |
0 |
T1 |
42951 |
30 |
0 |
0 |
T2 |
280836 |
579 |
0 |
0 |
T3 |
0 |
538 |
0 |
0 |
T4 |
8417 |
36 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T17 |
782 |
0 |
0 |
0 |
T18 |
3775 |
0 |
0 |
0 |
T19 |
650 |
0 |
0 |
0 |
T20 |
2601 |
0 |
0 |
0 |
T21 |
1385 |
0 |
0 |
0 |
T22 |
544 |
0 |
0 |
0 |
T23 |
1194 |
0 |
0 |
0 |
T24 |
0 |
76 |
0 |
0 |
T28 |
0 |
76 |
0 |
0 |
T29 |
0 |
60 |
0 |
0 |
T30 |
0 |
16 |
0 |
0 |
T31 |
0 |
56 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451064317 |
24849 |
0 |
0 |
T1 |
178908 |
30 |
0 |
0 |
T2 |
118722 |
569 |
0 |
0 |
T3 |
0 |
527 |
0 |
0 |
T4 |
64623 |
18 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T17 |
3146 |
0 |
0 |
0 |
T18 |
15768 |
0 |
0 |
0 |
T19 |
2466 |
0 |
0 |
0 |
T20 |
9346 |
0 |
0 |
0 |
T21 |
5361 |
0 |
0 |
0 |
T22 |
2355 |
0 |
0 |
0 |
T23 |
4473 |
0 |
0 |
0 |
T24 |
0 |
38 |
0 |
0 |
T28 |
0 |
38 |
0 |
0 |
T29 |
0 |
30 |
0 |
0 |
T30 |
0 |
16 |
0 |
0 |
T31 |
0 |
28 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153651632 |
24849 |
0 |
0 |
T1 |
171746 |
30 |
0 |
0 |
T2 |
323953 |
569 |
0 |
0 |
T3 |
0 |
527 |
0 |
0 |
T4 |
26496 |
18 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T17 |
1572 |
0 |
0 |
0 |
T18 |
1419 |
0 |
0 |
0 |
T19 |
2367 |
0 |
0 |
0 |
T20 |
1963 |
0 |
0 |
0 |
T21 |
1339 |
0 |
0 |
0 |
T22 |
999 |
0 |
0 |
0 |
T23 |
2192 |
0 |
0 |
0 |
T24 |
0 |
38 |
0 |
0 |
T28 |
0 |
38 |
0 |
0 |
T29 |
0 |
30 |
0 |
0 |
T30 |
0 |
16 |
0 |
0 |
T31 |
0 |
28 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451064317 |
30659 |
0 |
0 |
T1 |
178908 |
30 |
0 |
0 |
T2 |
118722 |
579 |
0 |
0 |
T3 |
0 |
538 |
0 |
0 |
T4 |
64623 |
36 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T17 |
3146 |
0 |
0 |
0 |
T18 |
15768 |
0 |
0 |
0 |
T19 |
2466 |
0 |
0 |
0 |
T20 |
9346 |
0 |
0 |
0 |
T21 |
5361 |
0 |
0 |
0 |
T22 |
2355 |
0 |
0 |
0 |
T23 |
4473 |
0 |
0 |
0 |
T24 |
0 |
76 |
0 |
0 |
T28 |
0 |
76 |
0 |
0 |
T29 |
0 |
60 |
0 |
0 |
T30 |
0 |
16 |
0 |
0 |
T31 |
0 |
56 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153651632 |
30680 |
0 |
0 |
T1 |
171746 |
30 |
0 |
0 |
T2 |
323953 |
579 |
0 |
0 |
T3 |
0 |
538 |
0 |
0 |
T4 |
26496 |
36 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T17 |
1572 |
0 |
0 |
0 |
T18 |
1419 |
0 |
0 |
0 |
T19 |
2367 |
0 |
0 |
0 |
T20 |
1963 |
0 |
0 |
0 |
T21 |
1339 |
0 |
0 |
0 |
T22 |
999 |
0 |
0 |
0 |
T23 |
2192 |
0 |
0 |
0 |
T24 |
0 |
76 |
0 |
0 |
T28 |
0 |
76 |
0 |
0 |
T29 |
0 |
60 |
0 |
0 |
T30 |
0 |
16 |
0 |
0 |
T31 |
0 |
56 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153651632 |
30645 |
0 |
0 |
T1 |
171746 |
30 |
0 |
0 |
T2 |
323953 |
579 |
0 |
0 |
T3 |
0 |
538 |
0 |
0 |
T4 |
26496 |
36 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T17 |
1572 |
0 |
0 |
0 |
T18 |
1419 |
0 |
0 |
0 |
T19 |
2367 |
0 |
0 |
0 |
T20 |
1963 |
0 |
0 |
0 |
T21 |
1339 |
0 |
0 |
0 |
T22 |
999 |
0 |
0 |
0 |
T23 |
2192 |
0 |
0 |
0 |
T24 |
0 |
76 |
0 |
0 |
T28 |
0 |
76 |
0 |
0 |
T29 |
0 |
60 |
0 |
0 |
T30 |
0 |
16 |
0 |
0 |
T31 |
0 |
56 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451064317 |
30662 |
0 |
0 |
T1 |
178908 |
30 |
0 |
0 |
T2 |
118722 |
579 |
0 |
0 |
T3 |
0 |
538 |
0 |
0 |
T4 |
64623 |
36 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T17 |
3146 |
0 |
0 |
0 |
T18 |
15768 |
0 |
0 |
0 |
T19 |
2466 |
0 |
0 |
0 |
T20 |
9346 |
0 |
0 |
0 |
T21 |
5361 |
0 |
0 |
0 |
T22 |
2355 |
0 |
0 |
0 |
T23 |
4473 |
0 |
0 |
0 |
T24 |
0 |
76 |
0 |
0 |
T28 |
0 |
76 |
0 |
0 |
T29 |
0 |
60 |
0 |
0 |
T30 |
0 |
16 |
0 |
0 |
T31 |
0 |
56 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T24 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
216314437 |
24416 |
0 |
0 |
T1 |
85877 |
30 |
0 |
0 |
T2 |
568726 |
569 |
0 |
0 |
T3 |
0 |
527 |
0 |
0 |
T4 |
31020 |
9 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T17 |
1510 |
0 |
0 |
0 |
T18 |
7569 |
0 |
0 |
0 |
T19 |
1183 |
0 |
0 |
0 |
T20 |
4486 |
0 |
0 |
0 |
T21 |
2573 |
0 |
0 |
0 |
T22 |
1112 |
0 |
0 |
0 |
T23 |
2147 |
0 |
0 |
0 |
T24 |
0 |
22 |
0 |
0 |
T28 |
0 |
30 |
0 |
0 |
T29 |
0 |
26 |
0 |
0 |
T30 |
0 |
16 |
0 |
0 |
T31 |
0 |
14 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153651632 |
24849 |
0 |
0 |
T1 |
171746 |
30 |
0 |
0 |
T2 |
323953 |
569 |
0 |
0 |
T3 |
0 |
527 |
0 |
0 |
T4 |
26496 |
18 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T17 |
1572 |
0 |
0 |
0 |
T18 |
1419 |
0 |
0 |
0 |
T19 |
2367 |
0 |
0 |
0 |
T20 |
1963 |
0 |
0 |
0 |
T21 |
1339 |
0 |
0 |
0 |
T22 |
999 |
0 |
0 |
0 |
T23 |
2192 |
0 |
0 |
0 |
T24 |
0 |
38 |
0 |
0 |
T28 |
0 |
38 |
0 |
0 |
T29 |
0 |
30 |
0 |
0 |
T30 |
0 |
16 |
0 |
0 |
T31 |
0 |
28 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
216314437 |
30476 |
0 |
0 |
T1 |
85877 |
30 |
0 |
0 |
T2 |
568726 |
579 |
0 |
0 |
T3 |
0 |
538 |
0 |
0 |
T4 |
31020 |
29 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T17 |
1510 |
0 |
0 |
0 |
T18 |
7569 |
0 |
0 |
0 |
T19 |
1183 |
0 |
0 |
0 |
T20 |
4486 |
0 |
0 |
0 |
T21 |
2573 |
0 |
0 |
0 |
T22 |
1112 |
0 |
0 |
0 |
T23 |
2147 |
0 |
0 |
0 |
T24 |
0 |
76 |
0 |
0 |
T28 |
0 |
76 |
0 |
0 |
T29 |
0 |
60 |
0 |
0 |
T30 |
0 |
16 |
0 |
0 |
T31 |
0 |
53 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153651632 |
30663 |
0 |
0 |
T1 |
171746 |
30 |
0 |
0 |
T2 |
323953 |
579 |
0 |
0 |
T3 |
0 |
538 |
0 |
0 |
T4 |
26496 |
36 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T17 |
1572 |
0 |
0 |
0 |
T18 |
1419 |
0 |
0 |
0 |
T19 |
2367 |
0 |
0 |
0 |
T20 |
1963 |
0 |
0 |
0 |
T21 |
1339 |
0 |
0 |
0 |
T22 |
999 |
0 |
0 |
0 |
T23 |
2192 |
0 |
0 |
0 |
T24 |
0 |
76 |
0 |
0 |
T28 |
0 |
76 |
0 |
0 |
T29 |
0 |
60 |
0 |
0 |
T30 |
0 |
16 |
0 |
0 |
T31 |
0 |
56 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153651632 |
30358 |
0 |
0 |
T1 |
171746 |
30 |
0 |
0 |
T2 |
323953 |
579 |
0 |
0 |
T3 |
0 |
538 |
0 |
0 |
T4 |
26496 |
27 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T17 |
1572 |
0 |
0 |
0 |
T18 |
1419 |
0 |
0 |
0 |
T19 |
2367 |
0 |
0 |
0 |
T20 |
1963 |
0 |
0 |
0 |
T21 |
1339 |
0 |
0 |
0 |
T22 |
999 |
0 |
0 |
0 |
T23 |
2192 |
0 |
0 |
0 |
T24 |
0 |
75 |
0 |
0 |
T28 |
0 |
73 |
0 |
0 |
T29 |
0 |
59 |
0 |
0 |
T30 |
0 |
16 |
0 |
0 |
T31 |
0 |
50 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
216314437 |
30518 |
0 |
0 |
T1 |
85877 |
30 |
0 |
0 |
T2 |
568726 |
579 |
0 |
0 |
T3 |
0 |
538 |
0 |
0 |
T4 |
31020 |
32 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T17 |
1510 |
0 |
0 |
0 |
T18 |
7569 |
0 |
0 |
0 |
T19 |
1183 |
0 |
0 |
0 |
T20 |
4486 |
0 |
0 |
0 |
T21 |
2573 |
0 |
0 |
0 |
T22 |
1112 |
0 |
0 |
0 |
T23 |
2147 |
0 |
0 |
0 |
T24 |
0 |
76 |
0 |
0 |
T28 |
0 |
76 |
0 |
0 |
T29 |
0 |
60 |
0 |
0 |
T30 |
0 |
16 |
0 |
0 |
T31 |
0 |
55 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T60,T63,T62 |
1 | 0 | Covered | T60,T63,T62 |
1 | 1 | Covered | T60,T64,T120 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T60,T63,T62 |
1 | 0 | Covered | T60,T64,T120 |
1 | 1 | Covered | T60,T63,T62 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153651632 |
32 |
0 |
0 |
T60 |
8206 |
2 |
0 |
0 |
T62 |
10884 |
1 |
0 |
0 |
T63 |
8371 |
1 |
0 |
0 |
T64 |
8044 |
3 |
0 |
0 |
T68 |
5070 |
1 |
0 |
0 |
T118 |
4103 |
1 |
0 |
0 |
T119 |
5730 |
3 |
0 |
0 |
T120 |
5812 |
2 |
0 |
0 |
T121 |
13498 |
1 |
0 |
0 |
T122 |
6577 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
422368728 |
32 |
0 |
0 |
T60 |
8206 |
2 |
0 |
0 |
T62 |
20897 |
1 |
0 |
0 |
T63 |
8117 |
1 |
0 |
0 |
T64 |
51483 |
3 |
0 |
0 |
T68 |
48666 |
1 |
0 |
0 |
T118 |
8205 |
1 |
0 |
0 |
T119 |
5730 |
3 |
0 |
0 |
T120 |
5935 |
2 |
0 |
0 |
T121 |
35994 |
1 |
0 |
0 |
T122 |
26309 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T60,T63,T65 |
1 | 0 | Covered | T60,T63,T65 |
1 | 1 | Covered | T60,T64,T120 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T60,T63,T65 |
1 | 0 | Covered | T60,T64,T120 |
1 | 1 | Covered | T60,T63,T65 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153651632 |
30 |
0 |
0 |
T60 |
8206 |
3 |
0 |
0 |
T63 |
8371 |
1 |
0 |
0 |
T64 |
8044 |
2 |
0 |
0 |
T65 |
16227 |
1 |
0 |
0 |
T117 |
11057 |
1 |
0 |
0 |
T118 |
4103 |
1 |
0 |
0 |
T119 |
5730 |
3 |
0 |
0 |
T120 |
5812 |
2 |
0 |
0 |
T121 |
13498 |
1 |
0 |
0 |
T122 |
6577 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
422368728 |
30 |
0 |
0 |
T60 |
8206 |
3 |
0 |
0 |
T63 |
8117 |
1 |
0 |
0 |
T64 |
51483 |
2 |
0 |
0 |
T65 |
15894 |
1 |
0 |
0 |
T117 |
11057 |
1 |
0 |
0 |
T118 |
8205 |
1 |
0 |
0 |
T119 |
5730 |
3 |
0 |
0 |
T120 |
5935 |
2 |
0 |
0 |
T121 |
35994 |
1 |
0 |
0 |
T122 |
26309 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T60,T67,T62 |
1 | 0 | Covered | T60,T67,T62 |
1 | 1 | Covered | T60,T62,T66 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T60,T67,T62 |
1 | 0 | Covered | T60,T62,T66 |
1 | 1 | Covered | T60,T67,T62 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153651632 |
41 |
0 |
0 |
T60 |
8206 |
3 |
0 |
0 |
T62 |
10884 |
2 |
0 |
0 |
T64 |
8044 |
1 |
0 |
0 |
T65 |
16227 |
1 |
0 |
0 |
T66 |
2092 |
2 |
0 |
0 |
T67 |
7039 |
1 |
0 |
0 |
T68 |
5070 |
1 |
0 |
0 |
T69 |
8532 |
1 |
0 |
0 |
T117 |
11057 |
2 |
0 |
0 |
T118 |
4103 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
210371220 |
41 |
0 |
0 |
T60 |
3556 |
3 |
0 |
0 |
T62 |
9633 |
2 |
0 |
0 |
T64 |
24965 |
1 |
0 |
0 |
T65 |
7247 |
1 |
0 |
0 |
T66 |
9604 |
2 |
0 |
0 |
T67 |
3209 |
1 |
0 |
0 |
T68 |
23169 |
1 |
0 |
0 |
T69 |
3745 |
1 |
0 |
0 |
T117 |
4580 |
2 |
0 |
0 |
T118 |
3571 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T60,T67,T62 |
1 | 0 | Covered | T60,T67,T62 |
1 | 1 | Covered | T60,T66,T123 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T60,T67,T62 |
1 | 0 | Covered | T60,T66,T123 |
1 | 1 | Covered | T60,T67,T62 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153651632 |
35 |
0 |
0 |
T60 |
8206 |
3 |
0 |
0 |
T62 |
10884 |
1 |
0 |
0 |
T64 |
8044 |
1 |
0 |
0 |
T65 |
16227 |
1 |
0 |
0 |
T66 |
2092 |
2 |
0 |
0 |
T67 |
7039 |
1 |
0 |
0 |
T117 |
11057 |
3 |
0 |
0 |
T118 |
4103 |
1 |
0 |
0 |
T119 |
5730 |
1 |
0 |
0 |
T124 |
5779 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
210371220 |
35 |
0 |
0 |
T60 |
3556 |
3 |
0 |
0 |
T62 |
9633 |
1 |
0 |
0 |
T64 |
24965 |
1 |
0 |
0 |
T65 |
7247 |
1 |
0 |
0 |
T66 |
9604 |
2 |
0 |
0 |
T67 |
3209 |
1 |
0 |
0 |
T117 |
4580 |
3 |
0 |
0 |
T118 |
3571 |
1 |
0 |
0 |
T119 |
2474 |
1 |
0 |
0 |
T124 |
5267 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T63,T62,T64 |
1 | 0 | Covered | T63,T62,T64 |
1 | 1 | Covered | T66,T120,T119 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T63,T62,T64 |
1 | 0 | Covered | T66,T120,T119 |
1 | 1 | Covered | T63,T62,T64 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153651632 |
35 |
0 |
0 |
T62 |
10884 |
2 |
0 |
0 |
T63 |
8371 |
1 |
0 |
0 |
T64 |
8044 |
2 |
0 |
0 |
T66 |
2092 |
2 |
0 |
0 |
T119 |
5730 |
3 |
0 |
0 |
T120 |
5812 |
2 |
0 |
0 |
T121 |
13498 |
1 |
0 |
0 |
T122 |
6577 |
1 |
0 |
0 |
T125 |
5830 |
1 |
0 |
0 |
T126 |
3518 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
105185012 |
35 |
0 |
0 |
T62 |
4817 |
2 |
0 |
0 |
T63 |
1811 |
1 |
0 |
0 |
T64 |
12484 |
2 |
0 |
0 |
T66 |
4803 |
2 |
0 |
0 |
T119 |
1238 |
3 |
0 |
0 |
T120 |
1230 |
2 |
0 |
0 |
T121 |
8579 |
1 |
0 |
0 |
T122 |
6109 |
1 |
0 |
0 |
T125 |
1166 |
1 |
0 |
0 |
T126 |
3331 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T61,T62,T64 |
1 | 0 | Covered | T61,T62,T64 |
1 | 1 | Covered | T64,T119,T127 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T61,T62,T64 |
1 | 0 | Covered | T64,T119,T127 |
1 | 1 | Covered | T61,T62,T64 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153651632 |
29 |
0 |
0 |
T61 |
4784 |
1 |
0 |
0 |
T62 |
10884 |
1 |
0 |
0 |
T64 |
8044 |
2 |
0 |
0 |
T66 |
2092 |
1 |
0 |
0 |
T119 |
5730 |
2 |
0 |
0 |
T120 |
5812 |
1 |
0 |
0 |
T121 |
13498 |
1 |
0 |
0 |
T122 |
6577 |
1 |
0 |
0 |
T125 |
5830 |
2 |
0 |
0 |
T128 |
4953 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
105185012 |
29 |
0 |
0 |
T61 |
4241 |
1 |
0 |
0 |
T62 |
4817 |
1 |
0 |
0 |
T64 |
12484 |
2 |
0 |
0 |
T66 |
4803 |
1 |
0 |
0 |
T119 |
1238 |
2 |
0 |
0 |
T120 |
1230 |
1 |
0 |
0 |
T121 |
8579 |
1 |
0 |
0 |
T122 |
6109 |
1 |
0 |
0 |
T125 |
1166 |
2 |
0 |
0 |
T128 |
1043 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T60,T62,T65 |
1 | 0 | Covered | T60,T62,T65 |
1 | 1 | Covered | T60,T64,T68 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T60,T62,T65 |
1 | 0 | Covered | T60,T64,T68 |
1 | 1 | Covered | T60,T62,T65 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153651632 |
39 |
0 |
0 |
T60 |
8206 |
2 |
0 |
0 |
T62 |
10884 |
2 |
0 |
0 |
T64 |
8044 |
4 |
0 |
0 |
T65 |
16227 |
1 |
0 |
0 |
T66 |
2092 |
1 |
0 |
0 |
T68 |
5070 |
4 |
0 |
0 |
T69 |
8532 |
1 |
0 |
0 |
T118 |
4103 |
1 |
0 |
0 |
T121 |
13498 |
1 |
0 |
0 |
T125 |
5830 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451064317 |
39 |
0 |
0 |
T60 |
8548 |
2 |
0 |
0 |
T62 |
21769 |
2 |
0 |
0 |
T64 |
53630 |
4 |
0 |
0 |
T65 |
16558 |
1 |
0 |
0 |
T66 |
20932 |
1 |
0 |
0 |
T68 |
50696 |
4 |
0 |
0 |
T69 |
8796 |
1 |
0 |
0 |
T118 |
8548 |
1 |
0 |
0 |
T121 |
37496 |
1 |
0 |
0 |
T125 |
5830 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T60,T62,T64 |
1 | 0 | Covered | T60,T62,T64 |
1 | 1 | Covered | T64,T127,T129 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T60,T62,T64 |
1 | 0 | Covered | T64,T127,T129 |
1 | 1 | Covered | T60,T62,T64 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153651632 |
31 |
0 |
0 |
T60 |
8206 |
1 |
0 |
0 |
T62 |
10884 |
2 |
0 |
0 |
T64 |
8044 |
3 |
0 |
0 |
T66 |
2092 |
1 |
0 |
0 |
T68 |
5070 |
2 |
0 |
0 |
T69 |
8532 |
1 |
0 |
0 |
T118 |
4103 |
2 |
0 |
0 |
T121 |
13498 |
1 |
0 |
0 |
T126 |
3518 |
1 |
0 |
0 |
T130 |
10200 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451064317 |
31 |
0 |
0 |
T60 |
8548 |
1 |
0 |
0 |
T62 |
21769 |
2 |
0 |
0 |
T64 |
53630 |
3 |
0 |
0 |
T66 |
20932 |
1 |
0 |
0 |
T68 |
50696 |
2 |
0 |
0 |
T69 |
8796 |
1 |
0 |
0 |
T118 |
8548 |
2 |
0 |
0 |
T121 |
37496 |
1 |
0 |
0 |
T126 |
14658 |
1 |
0 |
0 |
T130 |
10515 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T62,T65,T64 |
1 | 0 | Covered | T62,T65,T64 |
1 | 1 | Covered | T62,T65,T117 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T62,T65,T64 |
1 | 0 | Covered | T62,T65,T117 |
1 | 1 | Covered | T62,T65,T64 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153651632 |
37 |
0 |
0 |
T62 |
10884 |
2 |
0 |
0 |
T64 |
8044 |
1 |
0 |
0 |
T65 |
16227 |
3 |
0 |
0 |
T68 |
5070 |
1 |
0 |
0 |
T69 |
8532 |
1 |
0 |
0 |
T117 |
11057 |
3 |
0 |
0 |
T118 |
4103 |
2 |
0 |
0 |
T120 |
5812 |
1 |
0 |
0 |
T125 |
5830 |
3 |
0 |
0 |
T131 |
5149 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
216314437 |
37 |
0 |
0 |
T62 |
10449 |
2 |
0 |
0 |
T64 |
25742 |
1 |
0 |
0 |
T65 |
7947 |
3 |
0 |
0 |
T68 |
24335 |
1 |
0 |
0 |
T69 |
4222 |
1 |
0 |
0 |
T117 |
5529 |
3 |
0 |
0 |
T118 |
4103 |
2 |
0 |
0 |
T120 |
2968 |
1 |
0 |
0 |
T125 |
2798 |
3 |
0 |
0 |
T131 |
5044 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T62,T65,T64 |
1 | 0 | Covered | T62,T65,T64 |
1 | 1 | Covered | T62,T65,T117 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T62,T65,T64 |
1 | 0 | Covered | T62,T65,T117 |
1 | 1 | Covered | T62,T65,T64 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153651632 |
40 |
0 |
0 |
T62 |
10884 |
2 |
0 |
0 |
T64 |
8044 |
1 |
0 |
0 |
T65 |
16227 |
3 |
0 |
0 |
T68 |
5070 |
2 |
0 |
0 |
T117 |
11057 |
3 |
0 |
0 |
T118 |
4103 |
2 |
0 |
0 |
T120 |
5812 |
1 |
0 |
0 |
T125 |
5830 |
3 |
0 |
0 |
T130 |
10200 |
2 |
0 |
0 |
T131 |
5149 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
216314437 |
40 |
0 |
0 |
T62 |
10449 |
2 |
0 |
0 |
T64 |
25742 |
1 |
0 |
0 |
T65 |
7947 |
3 |
0 |
0 |
T68 |
24335 |
2 |
0 |
0 |
T117 |
5529 |
3 |
0 |
0 |
T118 |
4103 |
2 |
0 |
0 |
T120 |
2968 |
1 |
0 |
0 |
T125 |
2798 |
3 |
0 |
0 |
T130 |
5047 |
2 |
0 |
0 |
T131 |
5044 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
419407684 |
94115 |
0 |
0 |
T1 |
171746 |
73 |
0 |
0 |
T2 |
112372 |
2338 |
0 |
0 |
T3 |
0 |
2072 |
0 |
0 |
T4 |
62037 |
0 |
0 |
0 |
T10 |
0 |
111 |
0 |
0 |
T11 |
0 |
1341 |
0 |
0 |
T17 |
3019 |
0 |
0 |
0 |
T18 |
15137 |
0 |
0 |
0 |
T19 |
2367 |
0 |
0 |
0 |
T20 |
8973 |
0 |
0 |
0 |
T21 |
5146 |
0 |
0 |
0 |
T22 |
2255 |
0 |
0 |
0 |
T23 |
4295 |
0 |
0 |
0 |
T28 |
0 |
4 |
0 |
0 |
T30 |
0 |
58 |
0 |
0 |
T75 |
0 |
85 |
0 |
0 |
T76 |
0 |
59 |
0 |
0 |
T77 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16121675 |
92543 |
0 |
0 |
T1 |
861 |
73 |
0 |
0 |
T2 |
312357 |
2098 |
0 |
0 |
T3 |
0 |
2072 |
0 |
0 |
T4 |
141 |
0 |
0 |
0 |
T10 |
0 |
111 |
0 |
0 |
T11 |
0 |
1341 |
0 |
0 |
T17 |
220 |
0 |
0 |
0 |
T18 |
1103 |
0 |
0 |
0 |
T19 |
172 |
0 |
0 |
0 |
T20 |
654 |
0 |
0 |
0 |
T21 |
375 |
0 |
0 |
0 |
T22 |
166 |
0 |
0 |
0 |
T23 |
313 |
0 |
0 |
0 |
T28 |
0 |
4 |
0 |
0 |
T30 |
0 |
58 |
0 |
0 |
T75 |
0 |
85 |
0 |
0 |
T76 |
0 |
59 |
0 |
0 |
T77 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
208935804 |
93349 |
0 |
0 |
T1 |
85908 |
73 |
0 |
0 |
T2 |
561675 |
2325 |
0 |
0 |
T3 |
0 |
2069 |
0 |
0 |
T4 |
16835 |
0 |
0 |
0 |
T10 |
0 |
111 |
0 |
0 |
T11 |
0 |
1341 |
0 |
0 |
T17 |
1566 |
0 |
0 |
0 |
T18 |
7549 |
0 |
0 |
0 |
T19 |
1302 |
0 |
0 |
0 |
T20 |
5207 |
0 |
0 |
0 |
T21 |
2769 |
0 |
0 |
0 |
T22 |
1088 |
0 |
0 |
0 |
T23 |
2390 |
0 |
0 |
0 |
T28 |
0 |
2 |
0 |
0 |
T29 |
0 |
1 |
0 |
0 |
T30 |
0 |
58 |
0 |
0 |
T75 |
0 |
85 |
0 |
0 |
T76 |
0 |
59 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16121675 |
91789 |
0 |
0 |
T1 |
861 |
73 |
0 |
0 |
T2 |
312357 |
2089 |
0 |
0 |
T3 |
0 |
2069 |
0 |
0 |
T4 |
141 |
0 |
0 |
0 |
T10 |
0 |
111 |
0 |
0 |
T11 |
0 |
1341 |
0 |
0 |
T17 |
220 |
0 |
0 |
0 |
T18 |
1103 |
0 |
0 |
0 |
T19 |
172 |
0 |
0 |
0 |
T20 |
654 |
0 |
0 |
0 |
T21 |
375 |
0 |
0 |
0 |
T22 |
166 |
0 |
0 |
0 |
T23 |
313 |
0 |
0 |
0 |
T28 |
0 |
2 |
0 |
0 |
T29 |
0 |
1 |
0 |
0 |
T30 |
0 |
58 |
0 |
0 |
T75 |
0 |
85 |
0 |
0 |
T76 |
0 |
59 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
104467283 |
92325 |
0 |
0 |
T1 |
42951 |
73 |
0 |
0 |
T2 |
280836 |
2307 |
0 |
0 |
T3 |
0 |
2062 |
0 |
0 |
T4 |
8417 |
0 |
0 |
0 |
T10 |
0 |
111 |
0 |
0 |
T11 |
0 |
1341 |
0 |
0 |
T12 |
0 |
196 |
0 |
0 |
T17 |
782 |
0 |
0 |
0 |
T18 |
3775 |
0 |
0 |
0 |
T19 |
650 |
0 |
0 |
0 |
T20 |
2601 |
0 |
0 |
0 |
T21 |
1385 |
0 |
0 |
0 |
T22 |
544 |
0 |
0 |
0 |
T23 |
1194 |
0 |
0 |
0 |
T28 |
0 |
3 |
0 |
0 |
T30 |
0 |
58 |
0 |
0 |
T75 |
0 |
85 |
0 |
0 |
T76 |
0 |
59 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16121675 |
90789 |
0 |
0 |
T1 |
861 |
73 |
0 |
0 |
T2 |
312357 |
2074 |
0 |
0 |
T3 |
0 |
2063 |
0 |
0 |
T4 |
141 |
0 |
0 |
0 |
T10 |
0 |
111 |
0 |
0 |
T11 |
0 |
1341 |
0 |
0 |
T12 |
0 |
196 |
0 |
0 |
T17 |
220 |
0 |
0 |
0 |
T18 |
1103 |
0 |
0 |
0 |
T19 |
172 |
0 |
0 |
0 |
T20 |
654 |
0 |
0 |
0 |
T21 |
375 |
0 |
0 |
0 |
T22 |
166 |
0 |
0 |
0 |
T23 |
313 |
0 |
0 |
0 |
T28 |
0 |
3 |
0 |
0 |
T30 |
0 |
58 |
0 |
0 |
T75 |
0 |
85 |
0 |
0 |
T76 |
0 |
59 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447979787 |
113151 |
0 |
0 |
T1 |
178908 |
73 |
0 |
0 |
T2 |
118722 |
2562 |
0 |
0 |
T3 |
0 |
2589 |
0 |
0 |
T4 |
64623 |
0 |
0 |
0 |
T10 |
0 |
111 |
0 |
0 |
T11 |
0 |
1748 |
0 |
0 |
T12 |
0 |
196 |
0 |
0 |
T17 |
3146 |
0 |
0 |
0 |
T18 |
15768 |
0 |
0 |
0 |
T19 |
2466 |
0 |
0 |
0 |
T20 |
9346 |
0 |
0 |
0 |
T21 |
5361 |
0 |
0 |
0 |
T22 |
2355 |
0 |
0 |
0 |
T23 |
4473 |
0 |
0 |
0 |
T25 |
0 |
20 |
0 |
0 |
T30 |
0 |
130 |
0 |
0 |
T75 |
0 |
145 |
0 |
0 |
T76 |
0 |
95 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16200038 |
112924 |
0 |
0 |
T1 |
861 |
73 |
0 |
0 |
T2 |
324323 |
2562 |
0 |
0 |
T3 |
0 |
2379 |
0 |
0 |
T4 |
141 |
0 |
0 |
0 |
T10 |
0 |
111 |
0 |
0 |
T11 |
0 |
1748 |
0 |
0 |
T12 |
0 |
196 |
0 |
0 |
T17 |
220 |
0 |
0 |
0 |
T18 |
1103 |
0 |
0 |
0 |
T19 |
172 |
0 |
0 |
0 |
T20 |
654 |
0 |
0 |
0 |
T21 |
375 |
0 |
0 |
0 |
T22 |
166 |
0 |
0 |
0 |
T23 |
313 |
0 |
0 |
0 |
T25 |
0 |
20 |
0 |
0 |
T30 |
0 |
130 |
0 |
0 |
T75 |
0 |
145 |
0 |
0 |
T76 |
0 |
95 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
214833881 |
110828 |
0 |
0 |
T1 |
85877 |
73 |
0 |
0 |
T2 |
568726 |
2477 |
0 |
0 |
T3 |
0 |
2515 |
0 |
0 |
T4 |
31020 |
0 |
0 |
0 |
T10 |
0 |
111 |
0 |
0 |
T11 |
0 |
1612 |
0 |
0 |
T12 |
0 |
196 |
0 |
0 |
T17 |
1510 |
0 |
0 |
0 |
T18 |
7569 |
0 |
0 |
0 |
T19 |
1183 |
0 |
0 |
0 |
T20 |
4486 |
0 |
0 |
0 |
T21 |
2573 |
0 |
0 |
0 |
T22 |
1112 |
0 |
0 |
0 |
T23 |
2147 |
0 |
0 |
0 |
T25 |
0 |
19 |
0 |
0 |
T30 |
0 |
106 |
0 |
0 |
T75 |
0 |
108 |
0 |
0 |
T76 |
0 |
71 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16035818 |
110248 |
0 |
0 |
T1 |
861 |
73 |
0 |
0 |
T2 |
324275 |
2477 |
0 |
0 |
T3 |
0 |
2515 |
0 |
0 |
T4 |
141 |
0 |
0 |
0 |
T10 |
0 |
111 |
0 |
0 |
T11 |
0 |
1612 |
0 |
0 |
T12 |
0 |
196 |
0 |
0 |
T17 |
220 |
0 |
0 |
0 |
T18 |
1103 |
0 |
0 |
0 |
T19 |
172 |
0 |
0 |
0 |
T20 |
654 |
0 |
0 |
0 |
T21 |
375 |
0 |
0 |
0 |
T22 |
166 |
0 |
0 |
0 |
T23 |
313 |
0 |
0 |
0 |
T25 |
0 |
19 |
0 |
0 |
T30 |
0 |
106 |
0 |
0 |
T75 |
0 |
108 |
0 |
0 |
T76 |
0 |
71 |
0 |
0 |