Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T24
1	0	Covered	T1,T2,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1536516320	1424890	0	0
DstReqKnown_A	2147483647	2147483647	0	0
SrcAckBusyChk_A	1536516320	276806	0	0
SrcBusyKnown_A	1536516320	1511068380	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1536516320	1424890	0	0
T1	1717460	2434	0	0
T2	3239530	21049	0	0
T3	0	15485	0	0
T4	264960	1152	0	0
T10	0	2002	0	0
T17	15720	0	0	0
T18	14190	0	0	0
T19	23670	0	0	0
T20	19630	0	0	0
T21	13390	0	0	0
T22	9990	0	0	0
T23	21920	0	0	0
T24	0	4560	0	0
T28	0	1662	0	0
T29	0	1682	0	0
T30	0	1211	0	0
T31	0	2083	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1130780	1127552	0	0
T2	3284662	3277236	0	0
T4	365864	37820	0	0
T5	24850	24042	0	0
T6	13970	13294	0	0
T7	20106	19346	0	0
T17	20046	18600	0	0
T18	99596	98856	0	0
T19	15936	15376	0	0
T20	61226	60666	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1536516320	276806	0	0
T1	1717460	300	0	0
T2	3239530	5740	0	0
T3	0	5325	0	0
T4	264960	252	0	0
T10	0	400	0	0
T17	15720	0	0	0
T18	14190	0	0	0
T19	23670	0	0	0
T20	19630	0	0	0
T21	13390	0	0	0
T22	9990	0	0	0
T23	21920	0	0	0
T24	0	554	0	0
T28	0	557	0	0
T29	0	440	0	0
T30	0	160	0	0
T31	0	403	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1536516320	1511068380	0	0
T1	1717460	1711740	0	0
T2	3239530	3228760	0	0
T4	264960	24540	0	0
T5	39060	37670	0	0
T6	8140	7680	0	0
T7	25810	24790	0	0
T17	15720	14450	0	0
T18	14190	14080	0	0
T19	23670	22730	0	0
T20	19630	19430	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T2,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153651632	88512	0	0
DstReqKnown_A	422368728	417961797	0	0
SrcAckBusyChk_A	153651632	24849	0	0
SrcBusyKnown_A	153651632	151106838	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	88512	0	0
T1	171746	175	0	0
T2	323953	1580	0	0
T3	0	1339	0	0
T4	26496	59	0	0
T10	0	143	0	0
T17	1572	0	0	0
T18	1419	0	0	0
T19	2367	0	0	0
T20	1963	0	0	0
T21	1339	0	0	0
T22	999	0	0	0
T23	2192	0	0	0
T24	0	214	0	0
T28	0	97	0	0
T29	0	90	0	0
T30	0	74	0	0
T31	0	99	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422368728	417961797	0	0
T1	171746	171174	0	0
T2	112372	112031	0	0
T4	62037	5746	0	0
T5	3787	3652	0	0
T6	2111	1990	0	0
T7	3060	2939	0	0
T17	3019	2775	0	0
T18	15137	15016	0	0
T19	2367	2273	0	0
T20	8973	8879	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	24849	0	0
T1	171746	30	0	0
T2	323953	569	0	0
T3	0	527	0	0
T4	26496	18	0	0
T10	0	40	0	0
T17	1572	0	0	0
T18	1419	0	0	0
T19	2367	0	0	0
T20	1963	0	0	0
T21	1339	0	0	0
T22	999	0	0	0
T23	2192	0	0	0
T24	0	38	0	0
T28	0	38	0	0
T29	0	30	0	0
T30	0	16	0	0
T31	0	28	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	151106838	0	0
T1	171746	171174	0	0
T2	323953	322876	0	0
T4	26496	2454	0	0
T5	3906	3767	0	0
T6	814	768	0	0
T7	2581	2479	0	0
T17	1572	1445	0	0
T18	1419	1408	0	0
T19	2367	2273	0	0
T20	1963	1943	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T2,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153651632	126647	0	0
DstReqKnown_A	210371220	209259553	0	0
SrcAckBusyChk_A	153651632	24849	0	0
SrcBusyKnown_A	153651632	151106838	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	126647	0	0
T1	171746	254	0	0
T2	323953	2122	0	0
T3	0	1493	0	0
T4	26496	85	0	0
T10	0	201	0	0
T17	1572	0	0	0
T18	1419	0	0	0
T19	2367	0	0	0
T20	1963	0	0	0
T21	1339	0	0	0
T22	999	0	0	0
T23	2192	0	0	0
T24	0	310	0	0
T28	0	118	0	0
T29	0	119	0	0
T30	0	118	0	0
T31	0	145	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210371220	209259553	0	0
T1	85908	85803	0	0
T2	561675	560970	0	0
T4	16835	2874	0	0
T5	1867	1826	0	0
T6	1080	1059	0	0
T7	1518	1470	0	0
T17	1566	1497	0	0
T18	7549	7508	0	0
T19	1302	1274	0	0
T20	5207	5179	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	24849	0	0
T1	171746	30	0	0
T2	323953	569	0	0
T3	0	527	0	0
T4	26496	18	0	0
T10	0	40	0	0
T17	1572	0	0	0
T18	1419	0	0	0
T19	2367	0	0	0
T20	1963	0	0	0
T21	1339	0	0	0
T22	999	0	0	0
T23	2192	0	0	0
T24	0	38	0	0
T28	0	38	0	0
T29	0	30	0	0
T30	0	16	0	0
T31	0	28	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	151106838	0	0
T1	171746	171174	0	0
T2	323953	322876	0	0
T4	26496	2454	0	0
T5	3906	3767	0	0
T6	814	768	0	0
T7	2581	2479	0	0
T17	1572	1445	0	0
T18	1419	1408	0	0
T19	2367	2273	0	0
T20	1963	1943	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T2,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153651632	202848	0	0
DstReqKnown_A	105185012	104629307	0	0
SrcAckBusyChk_A	153651632	24849	0	0
SrcBusyKnown_A	153651632	151106838	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	202848	0	0
T1	171746	419	0	0
T2	323953	3090	0	0
T3	0	2025	0	0
T4	26496	128	0	0
T10	0	318	0	0
T17	1572	0	0	0
T18	1419	0	0	0
T19	2367	0	0	0
T20	1963	0	0	0
T21	1339	0	0	0
T22	999	0	0	0
T23	2192	0	0	0
T24	0	535	0	0
T28	0	156	0	0
T29	0	168	0	0
T30	0	212	0	0
T31	0	230	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105185012	104629307	0	0
T1	42951	42899	0	0
T2	280836	280484	0	0
T4	8417	1436	0	0
T5	934	913	0	0
T6	540	530	0	0
T7	759	735	0	0
T17	782	748	0	0
T18	3775	3754	0	0
T19	650	636	0	0
T20	2601	2587	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	24849	0	0
T1	171746	30	0	0
T2	323953	569	0	0
T3	0	527	0	0
T4	26496	18	0	0
T10	0	40	0	0
T17	1572	0	0	0
T18	1419	0	0	0
T19	2367	0	0	0
T20	1963	0	0	0
T21	1339	0	0	0
T22	999	0	0	0
T23	2192	0	0	0
T24	0	38	0	0
T28	0	38	0	0
T29	0	30	0	0
T30	0	16	0	0
T31	0	28	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	151106838	0	0
T1	171746	171174	0	0
T2	323953	322876	0	0
T4	26496	2454	0	0
T5	3906	3767	0	0
T6	814	768	0	0
T7	2581	2479	0	0
T17	1572	1445	0	0
T18	1419	1408	0	0
T19	2367	2273	0	0
T20	1963	1943	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T2,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153651632	87225	0	0
DstReqKnown_A	451064317	446413811	0	0
SrcAckBusyChk_A	153651632	24849	0	0
SrcBusyKnown_A	153651632	151106838	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	87225	0	0
T1	171746	143	0	0
T2	323953	1513	0	0
T3	0	1339	0	0
T4	26496	60	0	0
T10	0	138	0	0
T17	1572	0	0	0
T18	1419	0	0	0
T19	2367	0	0	0
T20	1963	0	0	0
T21	1339	0	0	0
T22	999	0	0	0
T23	2192	0	0	0
T24	0	172	0	0
T28	0	97	0	0
T29	0	84	0	0
T30	0	88	0	0
T31	0	97	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	451064317	446413811	0	0
T1	178908	178309	0	0
T2	118722	118323	0	0
T4	64623	5983	0	0
T5	3944	3804	0	0
T6	2199	2073	0	0
T7	3186	3060	0	0
T17	3146	2892	0	0
T18	15768	15642	0	0
T19	2466	2368	0	0
T20	9346	9249	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	24849	0	0
T1	171746	30	0	0
T2	323953	569	0	0
T3	0	527	0	0
T4	26496	18	0	0
T10	0	40	0	0
T17	1572	0	0	0
T18	1419	0	0	0
T19	2367	0	0	0
T20	1963	0	0	0
T21	1339	0	0	0
T22	999	0	0	0
T23	2192	0	0	0
T24	0	38	0	0
T28	0	38	0	0
T29	0	30	0	0
T30	0	16	0	0
T31	0	28	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	151106838	0	0
T1	171746	171174	0	0
T2	323953	322876	0	0
T4	26496	2454	0	0
T5	3906	3767	0	0
T6	814	768	0	0
T7	2581	2479	0	0
T17	1572	1445	0	0
T18	1419	1408	0	0
T19	2367	2273	0	0
T20	1963	1943	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T2,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153651632	125281	0	0
DstReqKnown_A	216314437	214079799	0	0
SrcAckBusyChk_A	153651632	24379	0	0
SrcBusyKnown_A	153651632	151106838	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	125281	0	0
T1	171746	229	0	0
T2	323953	2138	0	0
T3	0	1467	0	0
T4	26496	49	0	0
T10	0	202	0	0
T17	1572	0	0	0
T18	1419	0	0	0
T19	2367	0	0	0
T20	1963	0	0	0
T21	1339	0	0	0
T22	999	0	0	0
T23	2192	0	0	0
T24	0	232	0	0
T28	0	95	0	0
T29	0	102	0	0
T30	0	116	0	0
T31	0	88	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216314437	214079799	0	0
T1	85877	85591	0	0
T2	568726	566810	0	0
T4	31020	2871	0	0
T5	1893	1826	0	0
T6	1055	995	0	0
T7	1530	1469	0	0
T17	1510	1388	0	0
T18	7569	7508	0	0
T19	1183	1137	0	0
T20	4486	4439	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	24379	0	0
T1	171746	30	0	0
T2	323953	569	0	0
T3	0	527	0	0
T4	26496	9	0	0
T10	0	40	0	0
T17	1572	0	0	0
T18	1419	0	0	0
T19	2367	0	0	0
T20	1963	0	0	0
T21	1339	0	0	0
T22	999	0	0	0
T23	2192	0	0	0
T24	0	22	0	0
T28	0	26	0	0
T29	0	21	0	0
T30	0	16	0	0
T31	0	14	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	151106838	0	0
T1	171746	171174	0	0
T2	323953	322876	0	0
T4	26496	2454	0	0
T5	3906	3767	0	0
T6	814	768	0	0
T7	2581	2479	0	0
T17	1572	1445	0	0
T18	1419	1408	0	0
T19	2367	2273	0	0
T20	1963	1943	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T24
1	0	Covered	T1,T2,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T2,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153651632	110318	0	0
DstReqKnown_A	422368728	417961797	0	0
SrcAckBusyChk_A	153651632	30630	0	0
SrcBusyKnown_A	153651632	151106838	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	110318	0	0
T1	171746	172	0	0
T2	323953	1585	0	0
T3	0	1362	0	0
T4	26496	113	0	0
T10	0	141	0	0
T17	1572	0	0	0
T18	1419	0	0	0
T19	2367	0	0	0
T20	1963	0	0	0
T21	1339	0	0	0
T22	999	0	0	0
T23	2192	0	0	0
T24	0	446	0	0
T28	0	185	0	0
T29	0	167	0	0
T30	0	74	0	0
T31	0	199	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422368728	417961797	0	0
T1	171746	171174	0	0
T2	112372	112031	0	0
T4	62037	5746	0	0
T5	3787	3652	0	0
T6	2111	1990	0	0
T7	3060	2939	0	0
T17	3019	2775	0	0
T18	15137	15016	0	0
T19	2367	2273	0	0
T20	8973	8879	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	30630	0	0
T1	171746	30	0	0
T2	323953	579	0	0
T3	0	538	0	0
T4	26496	36	0	0
T10	0	40	0	0
T17	1572	0	0	0
T18	1419	0	0	0
T19	2367	0	0	0
T20	1963	0	0	0
T21	1339	0	0	0
T22	999	0	0	0
T23	2192	0	0	0
T24	0	76	0	0
T28	0	76	0	0
T29	0	60	0	0
T30	0	16	0	0
T31	0	56	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	151106838	0	0
T1	171746	171174	0	0
T2	323953	322876	0	0
T4	26496	2454	0	0
T5	3906	3767	0	0
T6	814	768	0	0
T7	2581	2479	0	0
T17	1572	1445	0	0
T18	1419	1408	0	0
T19	2367	2273	0	0
T20	1963	1943	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T24
1	0	Covered	T1,T2,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T2,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153651632	158553	0	0
DstReqKnown_A	210371220	209259553	0	0
SrcAckBusyChk_A	153651632	30639	0	0
SrcBusyKnown_A	153651632	151106838	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	158553	0	0
T1	171746	247	0	0
T2	323953	2172	0	0
T3	0	1512	0	0
T4	26496	157	0	0
T10	0	198	0	0
T17	1572	0	0	0
T18	1419	0	0	0
T19	2367	0	0	0
T20	1963	0	0	0
T21	1339	0	0	0
T22	999	0	0	0
T23	2192	0	0	0
T24	0	632	0	0
T28	0	218	0	0
T29	0	230	0	0
T30	0	119	0	0
T31	0	284	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210371220	209259553	0	0
T1	85908	85803	0	0
T2	561675	560970	0	0
T4	16835	2874	0	0
T5	1867	1826	0	0
T6	1080	1059	0	0
T7	1518	1470	0	0
T17	1566	1497	0	0
T18	7549	7508	0	0
T19	1302	1274	0	0
T20	5207	5179	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	30639	0	0
T1	171746	30	0	0
T2	323953	579	0	0
T3	0	538	0	0
T4	26496	36	0	0
T10	0	40	0	0
T17	1572	0	0	0
T18	1419	0	0	0
T19	2367	0	0	0
T20	1963	0	0	0
T21	1339	0	0	0
T22	999	0	0	0
T23	2192	0	0	0
T24	0	76	0	0
T28	0	76	0	0
T29	0	60	0	0
T30	0	16	0	0
T31	0	56	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	151106838	0	0
T1	171746	171174	0	0
T2	323953	322876	0	0
T4	26496	2454	0	0
T5	3906	3767	0	0
T6	814	768	0	0
T7	2581	2479	0	0
T17	1572	1445	0	0
T18	1419	1408	0	0
T19	2367	2273	0	0
T20	1963	1943	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T24
1	0	Covered	T1,T2,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T2,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153651632	256970	0	0
DstReqKnown_A	105185012	104629307	0	0
SrcAckBusyChk_A	153651632	30721	0	0
SrcBusyKnown_A	153651632	151106838	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	256970	0	0
T1	171746	428	0	0
T2	323953	3151	0	0
T3	0	2079	0	0
T4	26496	245	0	0
T10	0	322	0	0
T17	1572	0	0	0
T18	1419	0	0	0
T19	2367	0	0	0
T20	1963	0	0	0
T21	1339	0	0	0
T22	999	0	0	0
T23	2192	0	0	0
T24	0	1069	0	0
T28	0	294	0	0
T29	0	332	0	0
T30	0	203	0	0
T31	0	466	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105185012	104629307	0	0
T1	42951	42899	0	0
T2	280836	280484	0	0
T4	8417	1436	0	0
T5	934	913	0	0
T6	540	530	0	0
T7	759	735	0	0
T17	782	748	0	0
T18	3775	3754	0	0
T19	650	636	0	0
T20	2601	2587	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	30721	0	0
T1	171746	30	0	0
T2	323953	579	0	0
T3	0	538	0	0
T4	26496	36	0	0
T10	0	40	0	0
T17	1572	0	0	0
T18	1419	0	0	0
T19	2367	0	0	0
T20	1963	0	0	0
T21	1339	0	0	0
T22	999	0	0	0
T23	2192	0	0	0
T24	0	76	0	0
T28	0	76	0	0
T29	0	60	0	0
T30	0	16	0	0
T31	0	56	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	151106838	0	0
T1	171746	171174	0	0
T2	323953	322876	0	0
T4	26496	2454	0	0
T5	3906	3767	0	0
T6	814	768	0	0
T7	2581	2479	0	0
T17	1572	1445	0	0
T18	1419	1408	0	0
T19	2367	2273	0	0
T20	1963	1943	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T24
1	0	Covered	T1,T2,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T2,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153651632	109221	0	0
DstReqKnown_A	451064317	446413811	0	0
SrcAckBusyChk_A	153651632	30647	0	0
SrcBusyKnown_A	153651632	151106838	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	109221	0	0
T1	171746	141	0	0
T2	323953	1545	0	0
T3	0	1362	0	0
T4	26496	110	0	0
T10	0	138	0	0
T17	1572	0	0	0
T18	1419	0	0	0
T19	2367	0	0	0
T20	1963	0	0	0
T21	1339	0	0	0
T22	999	0	0	0
T23	2192	0	0	0
T24	0	358	0	0
T28	0	185	0	0
T29	0	163	0	0
T30	0	88	0	0
T31	0	195	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	451064317	446413811	0	0
T1	178908	178309	0	0
T2	118722	118323	0	0
T4	64623	5983	0	0
T5	3944	3804	0	0
T6	2199	2073	0	0
T7	3186	3060	0	0
T17	3146	2892	0	0
T18	15768	15642	0	0
T19	2466	2368	0	0
T20	9346	9249	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	30647	0	0
T1	171746	30	0	0
T2	323953	579	0	0
T3	0	538	0	0
T4	26496	36	0	0
T10	0	40	0	0
T17	1572	0	0	0
T18	1419	0	0	0
T19	2367	0	0	0
T20	1963	0	0	0
T21	1339	0	0	0
T22	999	0	0	0
T23	2192	0	0	0
T24	0	76	0	0
T28	0	76	0	0
T29	0	60	0	0
T30	0	16	0	0
T31	0	56	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	151106838	0	0
T1	171746	171174	0	0
T2	323953	322876	0	0
T4	26496	2454	0	0
T5	3906	3767	0	0
T6	814	768	0	0
T7	2581	2479	0	0
T17	1572	1445	0	0
T18	1419	1408	0	0
T19	2367	2273	0	0
T20	1963	1943	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T4,T24
1	0	Covered	T1,T2,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T2,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153651632	159315	0	0
DstReqKnown_A	216314437	214079799	0	0
SrcAckBusyChk_A	153651632	30394	0	0
SrcBusyKnown_A	153651632	151106838	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	159315	0	0
T1	171746	226	0	0
T2	323953	2153	0	0
T3	0	1507	0	0
T4	26496	146	0	0
T10	0	201	0	0
T17	1572	0	0	0
T18	1419	0	0	0
T19	2367	0	0	0
T20	1963	0	0	0
T21	1339	0	0	0
T22	999	0	0	0
T23	2192	0	0	0
T24	0	592	0	0
T28	0	217	0	0
T29	0	227	0	0
T30	0	119	0	0
T31	0	280	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216314437	214079799	0	0
T1	85877	85591	0	0
T2	568726	566810	0	0
T4	31020	2871	0	0
T5	1893	1826	0	0
T6	1055	995	0	0
T7	1530	1469	0	0
T17	1510	1388	0	0
T18	7569	7508	0	0
T19	1183	1137	0	0
T20	4486	4439	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	30394	0	0
T1	171746	30	0	0
T2	323953	579	0	0
T3	0	538	0	0
T4	26496	27	0	0
T10	0	40	0	0
T17	1572	0	0	0
T18	1419	0	0	0
T19	2367	0	0	0
T20	1963	0	0	0
T21	1339	0	0	0
T22	999	0	0	0
T23	2192	0	0	0
T24	0	76	0	0
T28	0	75	0	0
T29	0	59	0	0
T30	0	16	0	0
T31	0	53	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	151106838	0	0
T1	171746	171174	0	0
T2	323953	322876	0	0
T4	26496	2454	0	0
T5	3906	3767	0	0
T6	814	768	0	0
T7	2581	2479	0	0
T17	1572	1445	0	0
T18	1419	1408	0	0
T19	2367	2273	0	0
T20	1963	1943	0	0