Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	964676	0	0
SrcPulseCheck_M	2147483647	962915	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	964676
T1	2195017	4372
T2	3593585	9256
T3	737991	428
T4	49802	20
T5	851929	944
T6	45166	0
T10	0	9850
T11	0	1778
T12	0	182
T13	0	1306
T14	0	196
T17	11638	0
T18	29109	0
T19	395474	426
T20	17204	0
T50	6540	1
T51	24736	3
T54	5296	0
T55	9554	1
T60	11759	1
T114	14540	1
T115	20114	4
T116	13218	1
T117	13810	1
T118	6094	1
T119	13014	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	962915
T1	780797	4372
T2	5040053	9256
T3	184209	428
T4	18953	20
T5	497604	944
T6	13648	0
T10	0	9853
T11	0	1598
T12	0	182
T13	0	1306
T14	0	196
T17	4826	0
T18	9050	0
T19	214366	426
T20	7192	0
T50	11850	1
T51	22640	3
T54	2322	0
T55	74436	1
T60	8057	1
T114	11918	1
T115	17498	4
T116	5462	1
T117	27116	1
T118	10217	1
T119	24682	1

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	476370467	25595	0	0
SrcPulseCheck_M	166836732	25595	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	476370467	25595
T1	105479	216
T2	157923	483
T3	182652	32
T4	14697	4
T5	157006	36
T6	11350	0
T10	0	571
T11	0	104
T12	0	14
T13	0	54
T17	2745	0
T18	7298	0
T19	76466	18
T20	4028	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	166836732	25595
T1	119645	216
T2	504330	483
T3	45663	32
T4	7654	4
T5	208844	36
T6	2364	0
T10	0	571
T11	0	104
T12	0	14
T13	0	54
T17	1343	0
T18	1672	0
T19	87723	18
T20	2015	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	476370467	31374	0	0
SrcPulseCheck_M	166836732	31390	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	476370467	31374
T1	105479	216
T2	157923	494
T3	182652	32
T4	14697	8
T5	157006	36
T6	11350	0
T10	0	584
T11	0	109
T12	0	14
T13	0	54
T17	2745	0
T18	7298	0
T19	76466	18
T20	4028	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	166836732	31390
T1	119645	216
T2	504330	494
T3	45663	32
T4	7654	8
T5	208844	36
T6	2364	0
T10	0	584
T11	0	109
T12	0	14
T13	0	54
T17	1343	0
T18	1672	0
T19	87723	18
T20	2015	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	166836732	31362	0	0
SrcPulseCheck_M	476370467	31379	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	166836732	31362
T1	119645	216
T2	504330	494
T3	45663	32
T4	7654	8
T5	208844	36
T6	2364	0
T10	0	584
T11	0	109
T12	0	14
T13	0	54
T17	1343	0
T18	1672	0
T19	87723	18
T20	2015	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	476370467	31379
T1	105479	216
T2	157923	494
T3	182652	32
T4	14697	8
T5	157006	36
T6	11350	0
T10	0	584
T11	0	109
T12	0	14
T13	0	54
T17	2745	0
T18	7298	0
T19	76466	18
T20	4028	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	238402796	25595	0	0
SrcPulseCheck_M	166836732	25595	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	238402796	25595
T1	527319	216
T2	789853	483
T3	91259	32
T4	3469	4
T5	78436	36
T6	5608	0
T10	0	571
T11	0	104
T12	0	14
T13	0	54
T17	1340	0
T18	3582	0
T19	38180	18
T20	1990	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	166836732	25595
T1	119645	216
T2	504330	483
T3	45663	32
T4	7654	4
T5	208844	36
T6	2364	0
T10	0	571
T11	0	104
T12	0	14
T13	0	54
T17	1343	0
T18	1672	0
T19	87723	18
T20	2015	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	238402796	31187	0	0
SrcPulseCheck_M	166836732	31216	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	238402796	31187
T1	527319	216
T2	789853	494
T3	91259	32
T4	3469	8
T5	78436	36
T6	5608	0
T10	0	584
T11	0	109
T12	0	14
T13	0	54
T17	1340	0
T18	3582	0
T19	38180	18
T20	1990	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	166836732	31216
T1	119645	216
T2	504330	494
T3	45663	32
T4	7654	8
T5	208844	36
T6	2364	0
T10	0	584
T11	0	109
T12	0	14
T13	0	54
T17	1343	0
T18	1672	0
T19	87723	18
T20	2015	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	166836732	31180	0	0
SrcPulseCheck_M	238402796	31190	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	166836732	31180
T1	119645	216
T2	504330	494
T3	45663	32
T4	7654	8
T5	208844	36
T6	2364	0
T10	0	584
T11	0	109
T12	0	14
T13	0	54
T17	1343	0
T18	1672	0
T19	87723	18
T20	2015	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	238402796	31190
T1	527319	216
T2	789853	494
T3	91259	32
T4	3469	8
T5	78436	36
T6	5608	0
T10	0	584
T11	0	109
T12	0	14
T13	0	54
T17	1340	0
T18	3582	0
T19	38180	18
T20	1990	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	119200746	25595	0	0
SrcPulseCheck_M	166836732	25595	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	119200746	25595
T1	263658	216
T2	394925	483
T3	45630	32
T4	1735	4
T5	39218	36
T6	2804	0
T10	0	571
T11	0	104
T12	0	14
T13	0	54
T17	670	0
T18	1791	0
T19	19090	18
T20	995	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	166836732	25595
T1	119645	216
T2	504330	483
T3	45663	32
T4	7654	4
T5	208844	36
T6	2364	0
T10	0	571
T11	0	104
T12	0	14
T13	0	54
T17	1343	0
T18	1672	0
T19	87723	18
T20	2015	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	119200746	31366	0	0
SrcPulseCheck_M	166836732	31407	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	119200746	31366
T1	263658	216
T2	394925	494
T3	45630	32
T4	1735	8
T5	39218	36
T6	2804	0
T10	0	584
T11	0	109
T12	0	14
T13	0	54
T17	670	0
T18	1791	0
T19	19090	18
T20	995	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	166836732	31407
T1	119645	216
T2	504330	494
T3	45663	32
T4	7654	8
T5	208844	36
T6	2364	0
T10	0	584
T11	0	109
T12	0	14
T13	0	54
T17	1343	0
T18	1672	0
T19	87723	18
T20	2015	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	166836732	31361	0	0
SrcPulseCheck_M	119200746	31371	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	166836732	31361
T1	119645	216
T2	504330	494
T3	45663	32
T4	7654	8
T5	208844	36
T6	2364	0
T10	0	584
T11	0	109
T12	0	14
T13	0	54
T17	1343	0
T18	1672	0
T19	87723	18
T20	2015	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	119200746	31371
T1	263658	216
T2	394925	494
T3	45630	32
T4	1735	8
T5	39218	36
T6	2804	0
T10	0	584
T11	0	109
T12	0	14
T13	0	54
T17	670	0
T18	1791	0
T19	19090	18
T20	995	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	507288975	25595	0	0
SrcPulseCheck_M	166836732	25595	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	507288975	25595
T1	124278	216
T2	166848	483
T3	190269	32
T4	15309	4
T5	211553	36
T6	11824	0
T10	0	571
T11	0	104
T12	0	14
T13	0	54
T17	2860	0
T18	7602	0
T19	97655	18
T20	4196	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	166836732	25595
T1	119645	216
T2	504330	483
T3	45663	32
T4	7654	4
T5	208844	36
T6	2364	0
T10	0	571
T11	0	104
T12	0	14
T13	0	54
T17	1343	0
T18	1672	0
T19	87723	18
T20	2015	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	507288975	31334	0	0
SrcPulseCheck_M	166836732	31348	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	507288975	31334
T1	124278	216
T2	166848	494
T3	190269	32
T4	15309	8
T5	211553	36
T6	11824	0
T10	0	584
T11	0	109
T12	0	14
T13	0	54
T17	2860	0
T18	7602	0
T19	97655	18
T20	4196	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	166836732	31348
T1	119645	216
T2	504330	494
T3	45663	32
T4	7654	8
T5	208844	36
T6	2364	0
T10	0	584
T11	0	109
T12	0	14
T13	0	54
T17	1343	0
T18	1672	0
T19	87723	18
T20	2015	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	166836732	31320	0	0
SrcPulseCheck_M	507288975	31339	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	166836732	31320
T1	119645	216
T2	504330	494
T3	45663	32
T4	7654	8
T5	208844	36
T6	2364	0
T10	0	584
T11	0	109
T12	0	14
T13	0	54
T17	1343	0
T18	1672	0
T19	87723	18
T20	2015	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	507288975	31339
T1	124278	216
T2	166848	494
T3	190269	32
T4	15309	8
T5	211553	36
T6	11824	0
T10	0	584
T11	0	109
T12	0	14
T13	0	54
T17	2860	0
T18	7602	0
T19	97655	18
T20	4196	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T4

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	243666270	25145	0	0
SrcPulseCheck_M	166836732	25595	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	243666270	25145
T1	610946	216
T2	800326	483
T3	91330	32
T4	7349	2
T5	104426	36
T6	5675	0
T10	0	571
T11	0	104
T12	0	14
T13	0	54
T17	1372	0
T18	3649	0
T19	49755	18
T20	2015	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	166836732	25595
T1	119645	216
T2	504330	483
T3	45663	32
T4	7654	4
T5	208844	36
T6	2364	0
T10	0	571
T11	0	104
T12	0	14
T13	0	54
T17	1343	0
T18	1672	0
T19	87723	18
T20	2015	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	243666270	31354	0	0
SrcPulseCheck_M	166836732	31489	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	243666270	31354
T1	610946	216
T2	800326	494
T3	91330	32
T4	7349	6
T5	104426	36
T6	5675	0
T10	0	584
T11	0	109
T12	0	14
T13	0	54
T17	1372	0
T18	3649	0
T19	49755	18
T20	2015	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	166836732	31489
T1	119645	216
T2	504330	494
T3	45663	32
T4	7654	8
T5	208844	36
T6	2364	0
T10	0	584
T11	0	109
T12	0	14
T13	0	54
T17	1343	0
T18	1672	0
T19	87723	18
T20	2015	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	166836732	31190	0	0
SrcPulseCheck_M	243666270	31380	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	166836732	31190
T1	119645	216
T2	504330	494
T3	45663	32
T4	7654	6
T5	208844	36
T6	2364	0
T10	0	584
T11	0	109
T12	0	14
T13	0	54
T17	1343	0
T18	1672	0
T19	87723	18
T20	2015	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	243666270	31380
T1	610946	216
T2	800326	494
T3	91330	32
T4	7349	7
T5	104426	36
T6	5675	0
T10	0	584
T11	0	109
T12	0	14
T13	0	54
T17	1372	0
T18	3649	0
T19	49755	18
T20	2015	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T51,T54,T56
1	0	Covered	T51,T54,T56
1	1	Covered	T59,T120,T121

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T51,T54,T56
1	0	Covered	T59,T120,T121
1	1	Covered	T51,T54,T56

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	166836732	26	0	0
SrcPulseCheck_M	476370467	26	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	166836732	26
T51	12368	1
T54	5296	1
T55	4777	1
T56	9425	1
T57	5056	1
T59	7961	3
T122	8792	1
T123	4592	1
T124	7156	1
T125	6575	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	476370467	26
T51	24735	1
T54	5187	1
T55	76432	1
T56	9231	1
T57	19416	1
T59	29393	3
T122	8440	1
T123	9185	1
T124	7156	1
T125	12882	1

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T50,T54,T56
1	0	Covered	T50,T54,T56
1	1	Covered	T126,T127

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T50,T54,T56
1	0	Covered	T126,T127
1	1	Covered	T50,T54,T56

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	166836732	24	0	0
SrcPulseCheck_M	476370467	24	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	166836732	24
T50	3270	1
T54	5296	1
T55	4777	2
T56	9425	1
T57	5056	1
T118	6094	2
T122	8792	2
T123	4592	1
T124	7156	1
T126	2402	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	476370467	24
T50	12556	1
T54	5187	1
T55	76432	2
T56	9231	1
T57	19416	1
T118	21668	2
T122	8440	2
T123	9185	1
T124	7156	1
T126	28831	2

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T50,T51,T55
1	0	Covered	T50,T51,T55
1	1	Covered	T51,T115,T128

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T50,T51,T55
1	0	Covered	T51,T115,T128
1	1	Covered	T50,T51,T55

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	166836732	26	0	0
SrcPulseCheck_M	238402796	26	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	166836732	26
T50	3270	1
T51	12368	3
T55	4777	1
T60	11759	1
T114	7270	1
T115	10057	4
T116	6609	1
T117	6905	1
T118	6094	1
T119	6507	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	238402796	26
T50	5925	1
T51	11320	3
T55	37218	1
T60	8057	1
T114	5959	1
T115	8749	4
T116	2731	1
T117	13558	1
T118	10217	1
T119	12341	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T50,T51,T54
1	0	Covered	T50,T51,T54
1	1	Covered	T51,T128,T129

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T50,T51,T54
1	0	Covered	T51,T128,T129
1	1	Covered	T50,T51,T54

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	166836732	20	0	0
SrcPulseCheck_M	238402796	20	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	166836732	20
T50	3270	1
T51	12368	2
T54	5296	1
T55	4777	2
T114	7270	1
T115	10057	2
T116	6609	1
T117	6905	1
T119	6507	1
T128	10076	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	238402796	20
T50	5925	1
T51	11320	2
T54	2322	1
T55	37218	2
T114	5959	1
T115	8749	2
T116	2731	1
T117	13558	1
T119	12341	1
T128	4089	2

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T50,T51,T56
1	0	Covered	T50,T51,T56
1	1	Covered	T50,T126,T130

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T50,T51,T56
1	0	Covered	T50,T126,T130
1	1	Covered	T50,T51,T56

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	166836732	28	0	0
SrcPulseCheck_M	119200746	28	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	166836732	28
T50	3270	2
T51	12368	1
T55	4777	1
T56	9425	1
T60	11759	2
T114	7270	1
T115	10057	1
T117	6905	2
T122	8792	1
T131	4433	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	119200746	28
T50	2961	2
T51	5662	1
T55	18607	1
T56	1930	1
T60	4031	2
T114	2977	1
T115	4375	1
T117	6780	2
T122	1802	1
T131	5768	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T50,T51,T60
1	0	Covered	T50,T51,T60
1	1	Covered	T50,T130,T127

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T50,T51,T60
1	0	Covered	T50,T130,T127
1	1	Covered	T50,T51,T60

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	166836732	33	0	0
SrcPulseCheck_M	119200746	33	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	166836732	33
T50	3270	2
T51	12368	1
T60	11759	2
T114	7270	1
T115	10057	1
T122	8792	1
T123	4592	1
T124	7156	1
T125	6575	1
T131	4433	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	119200746	33
T50	2961	2
T51	5662	1
T60	4031	2
T114	2977	1
T115	4375	1
T122	1802	1
T123	2045	1
T124	1437	1
T125	3056	1
T131	5768	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T53,T50,T56
1	0	Covered	T53,T50,T56
1	1	Covered	T50,T114,T115

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T53,T50,T56
1	0	Covered	T50,T114,T115
1	1	Covered	T53,T50,T56

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	166836732	45	0	0
SrcPulseCheck_M	507288975	45	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	166836732	45
T50	3270	2
T53	3235	1
T55	4777	1
T56	9425	2
T57	5056	1
T59	7961	2
T60	11759	1
T114	7270	3
T115	10057	3
T123	4592	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	507288975	45
T50	13080	2
T53	13482	1
T55	79619	1
T56	9617	2
T57	20226	1
T59	30620	2
T60	18092	1
T114	14539	3
T115	20113	3
T123	9569	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T50,T51,T54
1	0	Covered	T50,T51,T54
1	1	Covered	T50,T123,T132

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T50,T51,T54
1	0	Covered	T50,T123,T132
1	1	Covered	T50,T51,T54

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	166836732	43	0	0
SrcPulseCheck_M	507288975	43	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	166836732	43
T50	3270	3
T51	12368	2
T54	5296	1
T55	4777	1
T56	9425	1
T57	5056	1
T59	7961	2
T60	11759	1
T115	10057	1
T123	4592	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	507288975	43
T50	13080	3
T51	25767	2
T54	5404	1
T55	79619	1
T56	9617	1
T57	20226	1
T59	30620	2
T60	18092	1
T115	20113	1
T123	9569	3

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T53,T51,T54
1	0	Covered	T53,T51,T54
1	1	Covered	T54,T122,T114

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T53,T51,T54
1	0	Covered	T54,T122,T114
1	1	Covered	T53,T51,T54

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	166836732	41	0	0
SrcPulseCheck_M	243666270	41	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	166836732	41
T51	12368	1
T53	3235	1
T54	5296	3
T55	4777	1
T59	7961	1
T60	11759	1
T114	7270	2
T115	10057	1
T122	8792	3
T125	6575	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	243666270	41
T51	12368	1
T53	6471	1
T54	2594	3
T55	38218	1
T59	14697	1
T60	8684	1
T114	6979	2
T115	9654	1
T122	4220	3
T125	6441	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T53,T51,T52
1	0	Covered	T53,T51,T52
1	1	Covered	T54,T122,T114

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T53,T51,T52
1	0	Covered	T54,T122,T114
1	1	Covered	T53,T51,T52

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	166836732	40	0	0
SrcPulseCheck_M	243666270	40	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	166836732	40
T51	12368	1
T52	3568	1
T53	3235	1
T54	5296	2
T55	4777	2
T56	9425	1
T59	7961	2
T60	11759	1
T114	7270	3
T122	8792	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	243666270	40
T51	12368	1
T52	6852	1
T53	6471	1
T54	2594	2
T55	38218	2
T56	4616	1
T59	14697	2
T60	8684	1
T114	6979	3
T122	4220	2

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5

Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	473979546	97917	0	0
SrcPulseCheck_M	16537249	97270	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	473979546	97917
T1	105479	859
T2	157923	1830
T3	182652	83
T4	14697	0
T5	157006	185
T6	11350	0
T10	0	1912
T11	0	346
T12	0	35
T13	0	283
T14	0	49
T17	2745	0
T18	7298	0
T19	76466	84
T20	4028	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	16537249	97270
T1	3475	859
T2	810268	1830
T3	406	83
T4	44	0
T5	346	185
T6	828	0
T10	0	1913
T11	0	286
T12	0	35
T13	0	283
T14	0	49
T17	200	0
T18	531	0
T19	176	84
T20	293	0

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	237252428	97311	0	0
SrcPulseCheck_M	16537249	96683	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	237252428	97311
T1	527319	859
T2	789853	1830
T3	91259	83
T4	3469	0
T5	78436	185
T6	5608	0
T10	0	1912
T11	0	346
T12	0	35
T13	0	283
T14	0	49
T17	1340	0
T18	3582	0
T19	38180	84
T20	1990	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	16537249	96683
T1	3475	859
T2	810268	1830
T3	406	83
T4	44	0
T5	346	185
T6	828	0
T10	0	1913
T11	0	286
T12	0	35
T13	0	283
T14	0	49
T17	200	0
T18	531	0
T19	176	84
T20	293	0

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	118625572	96086	0	0
SrcPulseCheck_M	16537249	95479	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	118625572	96086
T1	263658	859
T2	394925	1830
T3	45630	83
T4	1735	0
T5	39218	185
T6	2804	0
T10	0	1912
T11	0	346
T12	0	35
T13	0	283
T14	0	49
T17	670	0
T18	1791	0
T19	19090	84
T20	995	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	16537249	95479
T1	3475	859
T2	810268	1830
T3	406	83
T4	44	0
T5	346	185
T6	828	0
T10	0	1913
T11	0	286
T12	0	35
T13	0	283
T14	0	49
T17	200	0
T18	531	0
T19	176	84
T20	293	0

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5

Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	504798337	116720	0	0
SrcPulseCheck_M	17086948	116506	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	504798337	116720
T1	124278	1147
T2	166848	2295
T3	190269	83
T4	15309	0
T5	211553	281
T6	11824	0
T10	0	2375
T11	0	418
T12	0	35
T13	0	295
T14	0	49
T17	2860	0
T18	7602	0
T19	97655	120
T20	4196	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	17086948	116506
T1	3763	1147
T2	810736	2295
T3	406	83
T4	44	0
T5	442	281
T6	828	0
T10	0	2375
T11	0	418
T12	0	35
T13	0	295
T14	0	49
T17	200	0
T18	531	0
T19	212	120
T20	293	0

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T5
0	Covered	T1,T6,T5

Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	242470804	115763	0	0
SrcPulseCheck_M	17146664	115167	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	242470804	115763
T1	610946	1207
T2	800326	2278
T3	91330	83
T4	7349	0
T5	104426	293
T6	5675	0
T10	0	2327
T11	0	417
T12	0	35
T13	0	306
T14	0	49
T17	1372	0
T18	3649	0
T19	49755	132
T20	2015	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	17146664	115167
T1	3823	1207
T2	809797	2178
T3	406	83
T4	44	0
T5	454	293
T6	828	0
T10	0	2327
T11	0	417
T12	0	35
T13	0	306
T14	0	49
T17	200	0
T18	531	0
T19	224	132
T20	293	0

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_io_meas_ctrl_en_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	91.67			100.00	100.00	u_io_meas_ctrl_shadowed_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb