Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T4,T2,T10
1	0	Covered	T1,T5,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T5
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T5
0	1	-	Covered	T1,T5,T4
0	0	1	Covered	T1,T5,T4
0	0	0	Covered	T1,T6,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T5
0	1	-	Covered	T1,T5,T4
0	0	1	Covered	T1,T5,T4
0	0	0	Covered	T1,T6,T5

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1668367320	1389363	0	0
DstReqKnown_A	2147483647	2147483647	0	0
SrcAckBusyChk_A	1668367320	283967	0	0
SrcBusyKnown_A	1668367320	1644814360	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1668367320	1389363	0	0
T1	1196450	16444	0	0
T2	5043300	18686	0	0
T3	456630	1112	0	0
T4	76540	266	0	0
T5	2088440	3056	0	0
T6	23640	0	0	0
T10	0	45017	0	0
T11	0	8858	0	0
T12	0	730	0	0
T13	0	2295	0	0
T17	13430	0	0	0
T18	16720	0	0	0
T19	877230	1279	0	0
T20	20150	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3263360	3260398	0	0
T2	4619750	4617070	0	0
T3	1202280	1200692	0	0
T4	85118	13530	0	0
T5	1181278	1179960	0	0
T6	74522	73294	0	0
T17	17974	16736	0	0
T18	47844	46888	0	0
T19	562292	561204	0	0
T20	26448	25338	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1668367320	283967	0	0
T1	1196450	2160	0	0
T2	5043300	4885	0	0
T3	456630	320	0	0
T4	76540	56	0	0
T5	2088440	360	0	0
T6	23640	0	0	0
T10	0	5775	0	0
T11	0	1065	0	0
T12	0	140	0	0
T13	0	540	0	0
T17	13430	0	0	0
T18	16720	0	0	0
T19	877230	180	0	0
T20	20150	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1668367320	1644814360	0	0
T1	1196450	1195170	0	0
T2	5043300	5038990	0	0
T3	456630	455960	0	0
T4	76540	10720	0	0
T5	2088440	2086130	0	0
T6	23640	23190	0	0
T17	13430	12440	0	0
T18	16720	16320	0	0
T19	877230	875650	0	0
T20	20150	19190	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Unreachable
1	0	Covered	T1,T5,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T5
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T5
0	1	-	Covered	T1,T5,T4
0	0	1	Covered	T1,T5,T4
0	0	0	Covered	T1,T6,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T5
0	1	-	Covered	T1,T5,T4
0	0	1	Covered	T1,T5,T4
0	0	0	Covered	T1,T6,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	166836732	85789	0	0
DstReqKnown_A	476370467	471920402	0	0
SrcAckBusyChk_A	166836732	25595	0	0
SrcBusyKnown_A	166836732	164481436	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	85789	0	0
T1	119645	1040	0	0
T2	504330	1403	0	0
T3	45663	82	0	0
T4	7654	12	0	0
T5	208844	218	0	0
T6	2364	0	0	0
T10	0	2785	0	0
T11	0	620	0	0
T12	0	49	0	0
T13	0	175	0	0
T17	1343	0	0	0
T18	1672	0	0	0
T19	87723	81	0	0
T20	2015	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476370467	471920402	0	0
T1	105479	105344	0	0
T2	157923	157785	0	0
T3	182652	182380	0	0
T4	14697	2055	0	0
T5	157006	156775	0	0
T6	11350	11133	0	0
T17	2745	2542	0	0
T18	7298	7122	0	0
T19	76466	76277	0	0
T20	4028	3839	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	25595	0	0
T1	119645	216	0	0
T2	504330	483	0	0
T3	45663	32	0	0
T4	7654	4	0	0
T5	208844	36	0	0
T6	2364	0	0	0
T10	0	571	0	0
T11	0	104	0	0
T12	0	14	0	0
T13	0	54	0	0
T17	1343	0	0	0
T18	1672	0	0	0
T19	87723	18	0	0
T20	2015	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	164481436	0	0
T1	119645	119517	0	0
T2	504330	503899	0	0
T3	45663	45596	0	0
T4	7654	1072	0	0
T5	208844	208613	0	0
T6	2364	2319	0	0
T17	1343	1244	0	0
T18	1672	1632	0	0
T19	87723	87565	0	0
T20	2015	1919	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Unreachable
1	0	Covered	T1,T5,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T5
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T5
0	1	-	Covered	T1,T5,T4
0	0	1	Covered	T1,T5,T4
0	0	0	Covered	T1,T6,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T5
0	1	-	Covered	T1,T5,T4
0	0	1	Covered	T1,T5,T4
0	0	0	Covered	T1,T6,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	166836732	123058	0	0
DstReqKnown_A	238402796	237291815	0	0
SrcAckBusyChk_A	166836732	25595	0	0
SrcBusyKnown_A	166836732	164481436	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	123058	0	0
T1	119645	1644	0	0
T2	504330	1884	0	0
T3	45663	114	0	0
T4	7654	17	0	0
T5	208844	311	0	0
T6	2364	0	0	0
T10	0	4458	0	0
T11	0	877	0	0
T12	0	70	0	0
T13	0	228	0	0
T17	1343	0	0	0
T18	1672	0	0	0
T19	87723	127	0	0
T20	2015	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238402796	237291815	0	0
T1	527319	526967	0	0
T2	789853	789434	0	0
T3	91259	91190	0	0
T4	3469	1028	0	0
T5	78436	78388	0	0
T6	5608	5566	0	0
T17	1340	1271	0	0
T18	3582	3561	0	0
T19	38180	38139	0	0
T20	1990	1941	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	25595	0	0
T1	119645	216	0	0
T2	504330	483	0	0
T3	45663	32	0	0
T4	7654	4	0	0
T5	208844	36	0	0
T6	2364	0	0	0
T10	0	571	0	0
T11	0	104	0	0
T12	0	14	0	0
T13	0	54	0	0
T17	1343	0	0	0
T18	1672	0	0	0
T19	87723	18	0	0
T20	2015	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	164481436	0	0
T1	119645	119517	0	0
T2	504330	503899	0	0
T3	45663	45596	0	0
T4	7654	1072	0	0
T5	208844	208613	0	0
T6	2364	2319	0	0
T17	1343	1244	0	0
T18	1672	1632	0	0
T19	87723	87565	0	0
T20	2015	1919	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Unreachable
1	0	Covered	T1,T5,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T5
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T5
0	1	-	Covered	T1,T5,T4
0	0	1	Covered	T1,T5,T4
0	0	0	Covered	T1,T6,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T5
0	1	-	Covered	T1,T5,T4
0	0	1	Covered	T1,T5,T4
0	0	0	Covered	T1,T6,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	166836732	194475	0	0
DstReqKnown_A	119200746	118645367	0	0
SrcAckBusyChk_A	166836732	25595	0	0
SrcBusyKnown_A	166836732	164481436	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	194475	0	0
T1	119645	2855	0	0
T2	504330	2740	0	0
T3	45663	164	0	0
T4	7654	26	0	0
T5	208844	518	0	0
T6	2364	0	0	0
T10	0	7761	0	0
T11	0	1494	0	0
T12	0	113	0	0
T13	0	349	0	0
T17	1343	0	0	0
T18	1672	0	0	0
T19	87723	215	0	0
T20	2015	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119200746	118645367	0	0
T1	263658	263483	0	0
T2	394925	394716	0	0
T3	45630	45595	0	0
T4	1735	514	0	0
T5	39218	39194	0	0
T6	2804	2783	0	0
T17	670	636	0	0
T18	1791	1781	0	0
T19	19090	19069	0	0
T20	995	971	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	25595	0	0
T1	119645	216	0	0
T2	504330	483	0	0
T3	45663	32	0	0
T4	7654	4	0	0
T5	208844	36	0	0
T6	2364	0	0	0
T10	0	571	0	0
T11	0	104	0	0
T12	0	14	0	0
T13	0	54	0	0
T17	1343	0	0	0
T18	1672	0	0	0
T19	87723	18	0	0
T20	2015	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	164481436	0	0
T1	119645	119517	0	0
T2	504330	503899	0	0
T3	45663	45596	0	0
T4	7654	1072	0	0
T5	208844	208613	0	0
T6	2364	2319	0	0
T17	1343	1244	0	0
T18	1672	1632	0	0
T19	87723	87565	0	0
T20	2015	1919	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Unreachable
1	0	Covered	T1,T5,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T5
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T5
0	1	-	Covered	T1,T5,T4
0	0	1	Covered	T1,T5,T4
0	0	0	Covered	T1,T6,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T5
0	1	-	Covered	T1,T5,T4
0	0	1	Covered	T1,T5,T4
0	0	0	Covered	T1,T6,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	166836732	84728	0	0
DstReqKnown_A	507288975	502614252	0	0
SrcAckBusyChk_A	166836732	25595	0	0
SrcBusyKnown_A	166836732	164481436	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	84728	0	0
T1	119645	1017	0	0
T2	504330	1371	0	0
T3	45663	82	0	0
T4	7654	12	0	0
T5	208844	180	0	0
T6	2364	0	0	0
T10	0	2727	0	0
T11	0	501	0	0
T12	0	49	0	0
T13	0	172	0	0
T17	1343	0	0	0
T18	1672	0	0	0
T19	87723	84	0	0
T20	2015	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507288975	502614252	0	0
T1	124278	124137	0	0
T2	166848	166704	0	0
T3	190269	189986	0	0
T4	15309	2140	0	0
T5	211553	211312	0	0
T6	11824	11598	0	0
T17	2860	2648	0	0
T18	7602	7419	0	0
T19	97655	97457	0	0
T20	4196	3999	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	25595	0	0
T1	119645	216	0	0
T2	504330	483	0	0
T3	45663	32	0	0
T4	7654	4	0	0
T5	208844	36	0	0
T6	2364	0	0	0
T10	0	571	0	0
T11	0	104	0	0
T12	0	14	0	0
T13	0	54	0	0
T17	1343	0	0	0
T18	1672	0	0	0
T19	87723	18	0	0
T20	2015	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	164481436	0	0
T1	119645	119517	0	0
T2	504330	503899	0	0
T3	45663	45596	0	0
T4	7654	1072	0	0
T5	208844	208613	0	0
T6	2364	2319	0	0
T17	1343	1244	0	0
T18	1672	1632	0	0
T19	87723	87565	0	0
T20	2015	1919	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Unreachable
1	0	Covered	T1,T5,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T5
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T5
0	1	-	Covered	T1,T5,T4
0	0	1	Covered	T1,T5,T4
0	0	0	Covered	T1,T6,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T5
0	1	-	Covered	T1,T5,T4
0	0	1	Covered	T1,T5,T4
0	0	0	Covered	T1,T6,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	166836732	123046	0	0
DstReqKnown_A	243666270	241421487	0	0
SrcAckBusyChk_A	166836732	25122	0	0
SrcBusyKnown_A	166836732	164481436	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	123046	0	0
T1	119645	1627	0	0
T2	504330	1869	0	0
T3	45663	114	0	0
T4	7654	10	0	0
T5	208844	289	0	0
T6	2364	0	0	0
T10	0	4465	0	0
T11	0	819	0	0
T12	0	84	0	0
T13	0	227	0	0
T17	1343	0	0	0
T18	1672	0	0	0
T19	87723	133	0	0
T20	2015	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243666270	241421487	0	0
T1	610946	610268	0	0
T2	800326	799896	0	0
T3	91330	91195	0	0
T4	7349	1028	0	0
T5	104426	104311	0	0
T6	5675	5567	0	0
T17	1372	1271	0	0
T18	3649	3561	0	0
T19	49755	49660	0	0
T20	2015	1919	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	25122	0	0
T1	119645	216	0	0
T2	504330	483	0	0
T3	45663	32	0	0
T4	7654	2	0	0
T5	208844	36	0	0
T6	2364	0	0	0
T10	0	571	0	0
T11	0	104	0	0
T12	0	14	0	0
T13	0	54	0	0
T17	1343	0	0	0
T18	1672	0	0	0
T19	87723	18	0	0
T20	2015	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	164481436	0	0
T1	119645	119517	0	0
T2	504330	503899	0	0
T3	45663	45596	0	0
T4	7654	1072	0	0
T5	208844	208613	0	0
T6	2364	2319	0	0
T17	1343	1244	0	0
T18	1672	1632	0	0
T19	87723	87565	0	0
T20	2015	1919	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T4,T2,T10
1	0	Covered	T1,T5,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T5
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Unreachable
1	0	Covered	T1,T5,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T5
0	1	-	Covered	T1,T5,T4
0	0	1	Covered	T1,T5,T4
0	0	0	Covered	T1,T6,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T5
0	1	-	Covered	T1,T5,T4
0	0	1	Covered	T1,T5,T4
0	0	0	Covered	T1,T6,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	166836732	108139	0	0
DstReqKnown_A	476370467	471920402	0	0
SrcAckBusyChk_A	166836732	31364	0	0
SrcBusyKnown_A	166836732	164481436	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	108139	0	0
T1	119645	1038	0	0
T2	504330	1402	0	0
T3	45663	82	0	0
T4	7654	28	0	0
T5	208844	218	0	0
T6	2364	0	0	0
T10	0	2858	0	0
T11	0	651	0	0
T12	0	49	0	0
T13	0	174	0	0
T17	1343	0	0	0
T18	1672	0	0	0
T19	87723	84	0	0
T20	2015	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476370467	471920402	0	0
T1	105479	105344	0	0
T2	157923	157785	0	0
T3	182652	182380	0	0
T4	14697	2055	0	0
T5	157006	156775	0	0
T6	11350	11133	0	0
T17	2745	2542	0	0
T18	7298	7122	0	0
T19	76466	76277	0	0
T20	4028	3839	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	31364	0	0
T1	119645	216	0	0
T2	504330	494	0	0
T3	45663	32	0	0
T4	7654	8	0	0
T5	208844	36	0	0
T6	2364	0	0	0
T10	0	584	0	0
T11	0	109	0	0
T12	0	14	0	0
T13	0	54	0	0
T17	1343	0	0	0
T18	1672	0	0	0
T19	87723	18	0	0
T20	2015	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	164481436	0	0
T1	119645	119517	0	0
T2	504330	503899	0	0
T3	45663	45596	0	0
T4	7654	1072	0	0
T5	208844	208613	0	0
T6	2364	2319	0	0
T17	1343	1244	0	0
T18	1672	1632	0	0
T19	87723	87565	0	0
T20	2015	1919	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T4,T2,T10
1	0	Covered	T1,T5,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T5
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Unreachable
1	0	Covered	T1,T5,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T5
0	1	-	Covered	T1,T5,T4
0	0	1	Covered	T1,T5,T4
0	0	0	Covered	T1,T6,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T5
0	1	-	Covered	T1,T5,T4
0	0	1	Covered	T1,T5,T4
0	0	0	Covered	T1,T6,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	166836732	155672	0	0
DstReqKnown_A	238402796	237291815	0	0
SrcAckBusyChk_A	166836732	31182	0	0
SrcBusyKnown_A	166836732	164481436	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	155672	0	0
T1	119645	1657	0	0
T2	504330	1915	0	0
T3	45663	114	0	0
T4	7654	40	0	0
T5	208844	313	0	0
T6	2364	0	0	0
T10	0	4559	0	0
T11	0	915	0	0
T12	0	70	0	0
T13	0	227	0	0
T17	1343	0	0	0
T18	1672	0	0	0
T19	87723	126	0	0
T20	2015	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238402796	237291815	0	0
T1	527319	526967	0	0
T2	789853	789434	0	0
T3	91259	91190	0	0
T4	3469	1028	0	0
T5	78436	78388	0	0
T6	5608	5566	0	0
T17	1340	1271	0	0
T18	3582	3561	0	0
T19	38180	38139	0	0
T20	1990	1941	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	31182	0	0
T1	119645	216	0	0
T2	504330	494	0	0
T3	45663	32	0	0
T4	7654	8	0	0
T5	208844	36	0	0
T6	2364	0	0	0
T10	0	584	0	0
T11	0	109	0	0
T12	0	14	0	0
T13	0	54	0	0
T17	1343	0	0	0
T18	1672	0	0	0
T19	87723	18	0	0
T20	2015	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	164481436	0	0
T1	119645	119517	0	0
T2	504330	503899	0	0
T3	45663	45596	0	0
T4	7654	1072	0	0
T5	208844	208613	0	0
T6	2364	2319	0	0
T17	1343	1244	0	0
T18	1672	1632	0	0
T19	87723	87565	0	0
T20	2015	1919	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T4,T2,T10
1	0	Covered	T1,T5,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T5
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Unreachable
1	0	Covered	T1,T5,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T5
0	1	-	Covered	T1,T5,T4
0	0	1	Covered	T1,T5,T4
0	0	0	Covered	T1,T6,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T5
0	1	-	Covered	T1,T5,T4
0	0	1	Covered	T1,T5,T4
0	0	0	Covered	T1,T6,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	166836732	249543	0	0
DstReqKnown_A	119200746	118645367	0	0
SrcAckBusyChk_A	166836732	31365	0	0
SrcBusyKnown_A	166836732	164481436	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	249543	0	0
T1	119645	2883	0	0
T2	504330	2777	0	0
T3	45663	164	0	0
T4	7654	60	0	0
T5	208844	536	0	0
T6	2364	0	0	0
T10	0	8020	0	0
T11	0	1580	0	0
T12	0	113	0	0
T13	0	344	0	0
T17	1343	0	0	0
T18	1672	0	0	0
T19	87723	223	0	0
T20	2015	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119200746	118645367	0	0
T1	263658	263483	0	0
T2	394925	394716	0	0
T3	45630	45595	0	0
T4	1735	514	0	0
T5	39218	39194	0	0
T6	2804	2783	0	0
T17	670	636	0	0
T18	1791	1781	0	0
T19	19090	19069	0	0
T20	995	971	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	31365	0	0
T1	119645	216	0	0
T2	504330	494	0	0
T3	45663	32	0	0
T4	7654	8	0	0
T5	208844	36	0	0
T6	2364	0	0	0
T10	0	584	0	0
T11	0	109	0	0
T12	0	14	0	0
T13	0	54	0	0
T17	1343	0	0	0
T18	1672	0	0	0
T19	87723	18	0	0
T20	2015	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	164481436	0	0
T1	119645	119517	0	0
T2	504330	503899	0	0
T3	45663	45596	0	0
T4	7654	1072	0	0
T5	208844	208613	0	0
T6	2364	2319	0	0
T17	1343	1244	0	0
T18	1672	1632	0	0
T19	87723	87565	0	0
T20	2015	1919	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T4,T2,T10
1	0	Covered	T1,T5,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T5
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Unreachable
1	0	Covered	T1,T5,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T5
0	1	-	Covered	T1,T5,T4
0	0	1	Covered	T1,T5,T4
0	0	0	Covered	T1,T6,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T5
0	1	-	Covered	T1,T5,T4
0	0	1	Covered	T1,T5,T4
0	0	0	Covered	T1,T6,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	166836732	106596	0	0
DstReqKnown_A	507288975	502614252	0	0
SrcAckBusyChk_A	166836732	31324	0	0
SrcBusyKnown_A	166836732	164481436	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	106596	0	0
T1	119645	1029	0	0
T2	504330	1406	0	0
T3	45663	82	0	0
T4	7654	27	0	0
T5	208844	178	0	0
T6	2364	0	0	0
T10	0	2804	0	0
T11	0	530	0	0
T12	0	49	0	0
T13	0	171	0	0
T17	1343	0	0	0
T18	1672	0	0	0
T19	87723	78	0	0
T20	2015	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507288975	502614252	0	0
T1	124278	124137	0	0
T2	166848	166704	0	0
T3	190269	189986	0	0
T4	15309	2140	0	0
T5	211553	211312	0	0
T6	11824	11598	0	0
T17	2860	2648	0	0
T18	7602	7419	0	0
T19	97655	97457	0	0
T20	4196	3999	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	31324	0	0
T1	119645	216	0	0
T2	504330	494	0	0
T3	45663	32	0	0
T4	7654	8	0	0
T5	208844	36	0	0
T6	2364	0	0	0
T10	0	584	0	0
T11	0	109	0	0
T12	0	14	0	0
T13	0	54	0	0
T17	1343	0	0	0
T18	1672	0	0	0
T19	87723	18	0	0
T20	2015	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	164481436	0	0
T1	119645	119517	0	0
T2	504330	503899	0	0
T3	45663	45596	0	0
T4	7654	1072	0	0
T5	208844	208613	0	0
T6	2364	2319	0	0
T17	1343	1244	0	0
T18	1672	1632	0	0
T19	87723	87565	0	0
T20	2015	1919	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Covered	T4,T2,T10
1	0	Covered	T1,T5,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T5
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Unreachable
1	0	Covered	T1,T5,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T5
0	1	-	Covered	T1,T5,T4
0	0	1	Covered	T1,T5,T4
0	0	0	Covered	T1,T6,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T5
0	1	-	Covered	T1,T5,T4
0	0	1	Covered	T1,T5,T4
0	0	0	Covered	T1,T6,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	166836732	158317	0	0
DstReqKnown_A	243666270	241421487	0	0
SrcAckBusyChk_A	166836732	31230	0	0
SrcBusyKnown_A	166836732	164481436	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	158317	0	0
T1	119645	1654	0	0
T2	504330	1919	0	0
T3	45663	114	0	0
T4	7654	34	0	0
T5	208844	295	0	0
T6	2364	0	0	0
T10	0	4580	0	0
T11	0	871	0	0
T12	0	84	0	0
T13	0	228	0	0
T17	1343	0	0	0
T18	1672	0	0	0
T19	87723	128	0	0
T20	2015	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243666270	241421487	0	0
T1	610946	610268	0	0
T2	800326	799896	0	0
T3	91330	91195	0	0
T4	7349	1028	0	0
T5	104426	104311	0	0
T6	5675	5567	0	0
T17	1372	1271	0	0
T18	3649	3561	0	0
T19	49755	49660	0	0
T20	2015	1919	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	31230	0	0
T1	119645	216	0	0
T2	504330	494	0	0
T3	45663	32	0	0
T4	7654	6	0	0
T5	208844	36	0	0
T6	2364	0	0	0
T10	0	584	0	0
T11	0	109	0	0
T12	0	14	0	0
T13	0	54	0	0
T17	1343	0	0	0
T18	1672	0	0	0
T19	87723	18	0	0
T20	2015	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166836732	164481436	0	0
T1	119645	119517	0	0
T2	504330	503899	0	0
T3	45663	45596	0	0
T4	7654	1072	0	0
T5	208844	208613	0	0
T6	2364	2319	0	0
T17	1343	1244	0	0
T18	1672	1632	0	0
T19	87723	87565	0	0
T20	2015	1919	0	0