Line Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Module :
prim_reg_cdc
| Total | Covered | Percent |
Conditions | 15 | 13 | 86.67 |
Logical | 15 | 13 | 86.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Covered | T2,T3,T28 |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
Assert Coverage for Module :
prim_reg_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1356050500 |
1318229 |
0 |
0 |
T1 |
1142570 |
1603 |
0 |
0 |
T2 |
1730290 |
7742 |
0 |
0 |
T3 |
4679310 |
14467 |
0 |
0 |
T5 |
21430 |
0 |
0 |
0 |
T9 |
0 |
7604 |
0 |
0 |
T10 |
0 |
14545 |
0 |
0 |
T16 |
23580 |
0 |
0 |
0 |
T17 |
18460 |
0 |
0 |
0 |
T18 |
10570 |
0 |
0 |
0 |
T19 |
15110 |
0 |
0 |
0 |
T20 |
742430 |
1127 |
0 |
0 |
T21 |
23110 |
0 |
0 |
0 |
T22 |
0 |
1475 |
0 |
0 |
T28 |
0 |
2744 |
0 |
0 |
T29 |
0 |
3955 |
0 |
0 |
T30 |
0 |
4639 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
729282 |
728674 |
0 |
0 |
T2 |
3686000 |
3665074 |
0 |
0 |
T3 |
2897162 |
2894992 |
0 |
0 |
T4 |
136410 |
135830 |
0 |
0 |
T5 |
14214 |
13546 |
0 |
0 |
T16 |
45102 |
44636 |
0 |
0 |
T17 |
12182 |
11030 |
0 |
0 |
T18 |
6954 |
6376 |
0 |
0 |
T19 |
18594 |
17576 |
0 |
0 |
T20 |
618880 |
617960 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1356050500 |
270963 |
0 |
0 |
T1 |
1142570 |
200 |
0 |
0 |
T2 |
1730290 |
1480 |
0 |
0 |
T3 |
4679310 |
4750 |
0 |
0 |
T5 |
21430 |
0 |
0 |
0 |
T9 |
0 |
945 |
0 |
0 |
T10 |
0 |
2875 |
0 |
0 |
T16 |
23580 |
0 |
0 |
0 |
T17 |
18460 |
0 |
0 |
0 |
T18 |
10570 |
0 |
0 |
0 |
T19 |
15110 |
0 |
0 |
0 |
T20 |
742430 |
200 |
0 |
0 |
T21 |
23110 |
0 |
0 |
0 |
T22 |
0 |
180 |
0 |
0 |
T28 |
0 |
315 |
0 |
0 |
T29 |
0 |
457 |
0 |
0 |
T30 |
0 |
511 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1356050500 |
1330040690 |
0 |
0 |
T1 |
1142570 |
1141460 |
0 |
0 |
T2 |
1730290 |
1717690 |
0 |
0 |
T3 |
4679310 |
4674560 |
0 |
0 |
T4 |
25910 |
25800 |
0 |
0 |
T5 |
21430 |
20370 |
0 |
0 |
T16 |
23580 |
23310 |
0 |
0 |
T17 |
18460 |
16590 |
0 |
0 |
T18 |
10570 |
9630 |
0 |
0 |
T19 |
15110 |
14180 |
0 |
0 |
T20 |
742430 |
741490 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
135605050 |
82028 |
0 |
0 |
T1 |
114257 |
101 |
0 |
0 |
T2 |
173029 |
511 |
0 |
0 |
T3 |
467931 |
1173 |
0 |
0 |
T5 |
2143 |
0 |
0 |
0 |
T9 |
0 |
461 |
0 |
0 |
T10 |
0 |
1016 |
0 |
0 |
T16 |
2358 |
0 |
0 |
0 |
T17 |
1846 |
0 |
0 |
0 |
T18 |
1057 |
0 |
0 |
0 |
T19 |
1511 |
0 |
0 |
0 |
T20 |
74243 |
76 |
0 |
0 |
T21 |
2311 |
0 |
0 |
0 |
T22 |
0 |
92 |
0 |
0 |
T28 |
0 |
113 |
0 |
0 |
T29 |
0 |
174 |
0 |
0 |
T30 |
0 |
201 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403887567 |
399193452 |
0 |
0 |
T1 |
110790 |
110683 |
0 |
0 |
T2 |
329915 |
327394 |
0 |
0 |
T3 |
260831 |
260569 |
0 |
0 |
T4 |
20726 |
20632 |
0 |
0 |
T5 |
2165 |
2058 |
0 |
0 |
T16 |
6860 |
6780 |
0 |
0 |
T17 |
1865 |
1675 |
0 |
0 |
T18 |
1057 |
963 |
0 |
0 |
T19 |
2846 |
2670 |
0 |
0 |
T20 |
82276 |
82127 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
135605050 |
24023 |
0 |
0 |
T1 |
114257 |
20 |
0 |
0 |
T2 |
173029 |
145 |
0 |
0 |
T3 |
467931 |
470 |
0 |
0 |
T5 |
2143 |
0 |
0 |
0 |
T9 |
0 |
92 |
0 |
0 |
T10 |
0 |
286 |
0 |
0 |
T16 |
2358 |
0 |
0 |
0 |
T17 |
1846 |
0 |
0 |
0 |
T18 |
1057 |
0 |
0 |
0 |
T19 |
1511 |
0 |
0 |
0 |
T20 |
74243 |
20 |
0 |
0 |
T21 |
2311 |
0 |
0 |
0 |
T22 |
0 |
18 |
0 |
0 |
T28 |
0 |
22 |
0 |
0 |
T29 |
0 |
32 |
0 |
0 |
T30 |
0 |
36 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
135605050 |
133004069 |
0 |
0 |
T1 |
114257 |
114146 |
0 |
0 |
T2 |
173029 |
171769 |
0 |
0 |
T3 |
467931 |
467456 |
0 |
0 |
T4 |
2591 |
2580 |
0 |
0 |
T5 |
2143 |
2037 |
0 |
0 |
T16 |
2358 |
2331 |
0 |
0 |
T17 |
1846 |
1659 |
0 |
0 |
T18 |
1057 |
963 |
0 |
0 |
T19 |
1511 |
1418 |
0 |
0 |
T20 |
74243 |
74149 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
135605050 |
116802 |
0 |
0 |
T1 |
114257 |
162 |
0 |
0 |
T2 |
173029 |
733 |
0 |
0 |
T3 |
467931 |
1439 |
0 |
0 |
T5 |
2143 |
0 |
0 |
0 |
T9 |
0 |
743 |
0 |
0 |
T10 |
0 |
1469 |
0 |
0 |
T16 |
2358 |
0 |
0 |
0 |
T17 |
1846 |
0 |
0 |
0 |
T18 |
1057 |
0 |
0 |
0 |
T19 |
1511 |
0 |
0 |
0 |
T20 |
74243 |
115 |
0 |
0 |
T21 |
2311 |
0 |
0 |
0 |
T22 |
0 |
145 |
0 |
0 |
T28 |
0 |
181 |
0 |
0 |
T29 |
0 |
281 |
0 |
0 |
T30 |
0 |
320 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
201034394 |
199864332 |
0 |
0 |
T1 |
55362 |
55341 |
0 |
0 |
T2 |
164504 |
163828 |
0 |
0 |
T3 |
130393 |
130325 |
0 |
0 |
T4 |
10351 |
10316 |
0 |
0 |
T5 |
1070 |
1029 |
0 |
0 |
T16 |
3411 |
3390 |
0 |
0 |
T17 |
900 |
838 |
0 |
0 |
T18 |
527 |
492 |
0 |
0 |
T19 |
1376 |
1335 |
0 |
0 |
T20 |
41119 |
41064 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
135605050 |
24023 |
0 |
0 |
T1 |
114257 |
20 |
0 |
0 |
T2 |
173029 |
145 |
0 |
0 |
T3 |
467931 |
470 |
0 |
0 |
T5 |
2143 |
0 |
0 |
0 |
T9 |
0 |
92 |
0 |
0 |
T10 |
0 |
286 |
0 |
0 |
T16 |
2358 |
0 |
0 |
0 |
T17 |
1846 |
0 |
0 |
0 |
T18 |
1057 |
0 |
0 |
0 |
T19 |
1511 |
0 |
0 |
0 |
T20 |
74243 |
20 |
0 |
0 |
T21 |
2311 |
0 |
0 |
0 |
T22 |
0 |
18 |
0 |
0 |
T28 |
0 |
22 |
0 |
0 |
T29 |
0 |
32 |
0 |
0 |
T30 |
0 |
36 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
135605050 |
133004069 |
0 |
0 |
T1 |
114257 |
114146 |
0 |
0 |
T2 |
173029 |
171769 |
0 |
0 |
T3 |
467931 |
467456 |
0 |
0 |
T4 |
2591 |
2580 |
0 |
0 |
T5 |
2143 |
2037 |
0 |
0 |
T16 |
2358 |
2331 |
0 |
0 |
T17 |
1846 |
1659 |
0 |
0 |
T18 |
1057 |
963 |
0 |
0 |
T19 |
1511 |
1418 |
0 |
0 |
T20 |
74243 |
74149 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
135605050 |
184965 |
0 |
0 |
T1 |
114257 |
288 |
0 |
0 |
T2 |
173029 |
1170 |
0 |
0 |
T3 |
467931 |
1909 |
0 |
0 |
T5 |
2143 |
0 |
0 |
0 |
T9 |
0 |
1285 |
0 |
0 |
T10 |
0 |
2328 |
0 |
0 |
T16 |
2358 |
0 |
0 |
0 |
T17 |
1846 |
0 |
0 |
0 |
T18 |
1057 |
0 |
0 |
0 |
T19 |
1511 |
0 |
0 |
0 |
T20 |
74243 |
186 |
0 |
0 |
T21 |
2311 |
0 |
0 |
0 |
T22 |
0 |
269 |
0 |
0 |
T28 |
0 |
321 |
0 |
0 |
T29 |
0 |
485 |
0 |
0 |
T30 |
0 |
565 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
100516649 |
99931727 |
0 |
0 |
T1 |
27681 |
27671 |
0 |
0 |
T2 |
822520 |
819139 |
0 |
0 |
T3 |
651966 |
651625 |
0 |
0 |
T4 |
5175 |
5158 |
0 |
0 |
T5 |
535 |
514 |
0 |
0 |
T16 |
1705 |
1695 |
0 |
0 |
T17 |
450 |
419 |
0 |
0 |
T18 |
264 |
247 |
0 |
0 |
T19 |
688 |
667 |
0 |
0 |
T20 |
20559 |
20531 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
135605050 |
24023 |
0 |
0 |
T1 |
114257 |
20 |
0 |
0 |
T2 |
173029 |
145 |
0 |
0 |
T3 |
467931 |
470 |
0 |
0 |
T5 |
2143 |
0 |
0 |
0 |
T9 |
0 |
92 |
0 |
0 |
T10 |
0 |
286 |
0 |
0 |
T16 |
2358 |
0 |
0 |
0 |
T17 |
1846 |
0 |
0 |
0 |
T18 |
1057 |
0 |
0 |
0 |
T19 |
1511 |
0 |
0 |
0 |
T20 |
74243 |
20 |
0 |
0 |
T21 |
2311 |
0 |
0 |
0 |
T22 |
0 |
18 |
0 |
0 |
T28 |
0 |
22 |
0 |
0 |
T29 |
0 |
32 |
0 |
0 |
T30 |
0 |
36 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
135605050 |
133004069 |
0 |
0 |
T1 |
114257 |
114146 |
0 |
0 |
T2 |
173029 |
171769 |
0 |
0 |
T3 |
467931 |
467456 |
0 |
0 |
T4 |
2591 |
2580 |
0 |
0 |
T5 |
2143 |
2037 |
0 |
0 |
T16 |
2358 |
2331 |
0 |
0 |
T17 |
1846 |
1659 |
0 |
0 |
T18 |
1057 |
963 |
0 |
0 |
T19 |
1511 |
1418 |
0 |
0 |
T20 |
74243 |
74149 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
135605050 |
82289 |
0 |
0 |
T1 |
114257 |
97 |
0 |
0 |
T2 |
173029 |
504 |
0 |
0 |
T3 |
467931 |
1173 |
0 |
0 |
T5 |
2143 |
0 |
0 |
0 |
T9 |
0 |
452 |
0 |
0 |
T10 |
0 |
992 |
0 |
0 |
T16 |
2358 |
0 |
0 |
0 |
T17 |
1846 |
0 |
0 |
0 |
T18 |
1057 |
0 |
0 |
0 |
T19 |
1511 |
0 |
0 |
0 |
T20 |
74243 |
74 |
0 |
0 |
T21 |
2311 |
0 |
0 |
0 |
T22 |
0 |
91 |
0 |
0 |
T28 |
0 |
134 |
0 |
0 |
T29 |
0 |
174 |
0 |
0 |
T30 |
0 |
230 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430254007 |
425305886 |
0 |
0 |
T1 |
115410 |
115298 |
0 |
0 |
T2 |
354472 |
351847 |
0 |
0 |
T3 |
273756 |
273476 |
0 |
0 |
T4 |
21590 |
21492 |
0 |
0 |
T5 |
2255 |
2143 |
0 |
0 |
T16 |
7146 |
7063 |
0 |
0 |
T17 |
1943 |
1745 |
0 |
0 |
T18 |
1101 |
1004 |
0 |
0 |
T19 |
2964 |
2781 |
0 |
0 |
T20 |
115706 |
115552 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
135605050 |
24023 |
0 |
0 |
T1 |
114257 |
20 |
0 |
0 |
T2 |
173029 |
145 |
0 |
0 |
T3 |
467931 |
470 |
0 |
0 |
T5 |
2143 |
0 |
0 |
0 |
T9 |
0 |
92 |
0 |
0 |
T10 |
0 |
286 |
0 |
0 |
T16 |
2358 |
0 |
0 |
0 |
T17 |
1846 |
0 |
0 |
0 |
T18 |
1057 |
0 |
0 |
0 |
T19 |
1511 |
0 |
0 |
0 |
T20 |
74243 |
20 |
0 |
0 |
T21 |
2311 |
0 |
0 |
0 |
T22 |
0 |
18 |
0 |
0 |
T28 |
0 |
22 |
0 |
0 |
T29 |
0 |
32 |
0 |
0 |
T30 |
0 |
36 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
135605050 |
133004069 |
0 |
0 |
T1 |
114257 |
114146 |
0 |
0 |
T2 |
173029 |
171769 |
0 |
0 |
T3 |
467931 |
467456 |
0 |
0 |
T4 |
2591 |
2580 |
0 |
0 |
T5 |
2143 |
2037 |
0 |
0 |
T16 |
2358 |
2331 |
0 |
0 |
T17 |
1846 |
1659 |
0 |
0 |
T18 |
1057 |
963 |
0 |
0 |
T19 |
1511 |
1418 |
0 |
0 |
T20 |
74243 |
74149 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
135605050 |
114747 |
0 |
0 |
T1 |
114257 |
158 |
0 |
0 |
T2 |
173029 |
878 |
0 |
0 |
T3 |
467931 |
1443 |
0 |
0 |
T5 |
2143 |
0 |
0 |
0 |
T9 |
0 |
743 |
0 |
0 |
T10 |
0 |
1444 |
0 |
0 |
T16 |
2358 |
0 |
0 |
0 |
T17 |
1846 |
0 |
0 |
0 |
T18 |
1057 |
0 |
0 |
0 |
T19 |
1511 |
0 |
0 |
0 |
T20 |
74243 |
115 |
0 |
0 |
T21 |
2311 |
0 |
0 |
0 |
T22 |
0 |
146 |
0 |
0 |
T28 |
0 |
102 |
0 |
0 |
T29 |
0 |
157 |
0 |
0 |
T30 |
0 |
175 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206654856 |
204283812 |
0 |
0 |
T1 |
55398 |
55344 |
0 |
0 |
T2 |
171589 |
170329 |
0 |
0 |
T3 |
131635 |
131501 |
0 |
0 |
T4 |
10363 |
10317 |
0 |
0 |
T5 |
1082 |
1029 |
0 |
0 |
T16 |
3429 |
3390 |
0 |
0 |
T17 |
933 |
838 |
0 |
0 |
T18 |
528 |
482 |
0 |
0 |
T19 |
1423 |
1335 |
0 |
0 |
T20 |
49780 |
49706 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
135605050 |
23508 |
0 |
0 |
T1 |
114257 |
20 |
0 |
0 |
T2 |
173029 |
145 |
0 |
0 |
T3 |
467931 |
470 |
0 |
0 |
T5 |
2143 |
0 |
0 |
0 |
T9 |
0 |
92 |
0 |
0 |
T10 |
0 |
286 |
0 |
0 |
T16 |
2358 |
0 |
0 |
0 |
T17 |
1846 |
0 |
0 |
0 |
T18 |
1057 |
0 |
0 |
0 |
T19 |
1511 |
0 |
0 |
0 |
T20 |
74243 |
20 |
0 |
0 |
T21 |
2311 |
0 |
0 |
0 |
T22 |
0 |
18 |
0 |
0 |
T28 |
0 |
11 |
0 |
0 |
T29 |
0 |
16 |
0 |
0 |
T30 |
0 |
18 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
135605050 |
133004069 |
0 |
0 |
T1 |
114257 |
114146 |
0 |
0 |
T2 |
173029 |
171769 |
0 |
0 |
T3 |
467931 |
467456 |
0 |
0 |
T4 |
2591 |
2580 |
0 |
0 |
T5 |
2143 |
2037 |
0 |
0 |
T16 |
2358 |
2331 |
0 |
0 |
T17 |
1846 |
1659 |
0 |
0 |
T18 |
1057 |
963 |
0 |
0 |
T19 |
1511 |
1418 |
0 |
0 |
T20 |
74243 |
74149 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
| Total | Covered | Percent |
Conditions | 12 | 11 | 91.67 |
Logical | 12 | 11 | 91.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Covered | T2,T3,T28 |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
135605050 |
104027 |
0 |
0 |
T1 |
114257 |
99 |
0 |
0 |
T2 |
173029 |
531 |
0 |
0 |
T3 |
467931 |
1200 |
0 |
0 |
T5 |
2143 |
0 |
0 |
0 |
T9 |
0 |
488 |
0 |
0 |
T10 |
0 |
1014 |
0 |
0 |
T16 |
2358 |
0 |
0 |
0 |
T17 |
1846 |
0 |
0 |
0 |
T18 |
1057 |
0 |
0 |
0 |
T19 |
1511 |
0 |
0 |
0 |
T20 |
74243 |
78 |
0 |
0 |
T21 |
2311 |
0 |
0 |
0 |
T22 |
0 |
93 |
0 |
0 |
T28 |
0 |
231 |
0 |
0 |
T29 |
0 |
338 |
0 |
0 |
T30 |
0 |
388 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403887567 |
399193452 |
0 |
0 |
T1 |
110790 |
110683 |
0 |
0 |
T2 |
329915 |
327394 |
0 |
0 |
T3 |
260831 |
260569 |
0 |
0 |
T4 |
20726 |
20632 |
0 |
0 |
T5 |
2165 |
2058 |
0 |
0 |
T16 |
6860 |
6780 |
0 |
0 |
T17 |
1865 |
1675 |
0 |
0 |
T18 |
1057 |
963 |
0 |
0 |
T19 |
2846 |
2670 |
0 |
0 |
T20 |
82276 |
82127 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
135605050 |
30348 |
0 |
0 |
T1 |
114257 |
20 |
0 |
0 |
T2 |
173029 |
151 |
0 |
0 |
T3 |
467931 |
480 |
0 |
0 |
T5 |
2143 |
0 |
0 |
0 |
T9 |
0 |
97 |
0 |
0 |
T10 |
0 |
289 |
0 |
0 |
T16 |
2358 |
0 |
0 |
0 |
T17 |
1846 |
0 |
0 |
0 |
T18 |
1057 |
0 |
0 |
0 |
T19 |
1511 |
0 |
0 |
0 |
T20 |
74243 |
20 |
0 |
0 |
T21 |
2311 |
0 |
0 |
0 |
T22 |
0 |
18 |
0 |
0 |
T28 |
0 |
44 |
0 |
0 |
T29 |
0 |
64 |
0 |
0 |
T30 |
0 |
72 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
135605050 |
133004069 |
0 |
0 |
T1 |
114257 |
114146 |
0 |
0 |
T2 |
173029 |
171769 |
0 |
0 |
T3 |
467931 |
467456 |
0 |
0 |
T4 |
2591 |
2580 |
0 |
0 |
T5 |
2143 |
2037 |
0 |
0 |
T16 |
2358 |
2331 |
0 |
0 |
T17 |
1846 |
1659 |
0 |
0 |
T18 |
1057 |
963 |
0 |
0 |
T19 |
1511 |
1418 |
0 |
0 |
T20 |
74243 |
74149 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
| Total | Covered | Percent |
Conditions | 12 | 11 | 91.67 |
Logical | 12 | 11 | 91.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Covered | T2,T3,T28 |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
135605050 |
146748 |
0 |
0 |
T1 |
114257 |
163 |
0 |
0 |
T2 |
173029 |
761 |
0 |
0 |
T3 |
467931 |
1483 |
0 |
0 |
T5 |
2143 |
0 |
0 |
0 |
T9 |
0 |
786 |
0 |
0 |
T10 |
0 |
1463 |
0 |
0 |
T16 |
2358 |
0 |
0 |
0 |
T17 |
1846 |
0 |
0 |
0 |
T18 |
1057 |
0 |
0 |
0 |
T19 |
1511 |
0 |
0 |
0 |
T20 |
74243 |
110 |
0 |
0 |
T21 |
2311 |
0 |
0 |
0 |
T22 |
0 |
146 |
0 |
0 |
T28 |
0 |
377 |
0 |
0 |
T29 |
0 |
546 |
0 |
0 |
T30 |
0 |
622 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
201034394 |
199864332 |
0 |
0 |
T1 |
55362 |
55341 |
0 |
0 |
T2 |
164504 |
163828 |
0 |
0 |
T3 |
130393 |
130325 |
0 |
0 |
T4 |
10351 |
10316 |
0 |
0 |
T5 |
1070 |
1029 |
0 |
0 |
T16 |
3411 |
3390 |
0 |
0 |
T17 |
900 |
838 |
0 |
0 |
T18 |
527 |
492 |
0 |
0 |
T19 |
1376 |
1335 |
0 |
0 |
T20 |
41119 |
41064 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
135605050 |
30162 |
0 |
0 |
T1 |
114257 |
20 |
0 |
0 |
T2 |
173029 |
151 |
0 |
0 |
T3 |
467931 |
480 |
0 |
0 |
T5 |
2143 |
0 |
0 |
0 |
T9 |
0 |
97 |
0 |
0 |
T10 |
0 |
289 |
0 |
0 |
T16 |
2358 |
0 |
0 |
0 |
T17 |
1846 |
0 |
0 |
0 |
T18 |
1057 |
0 |
0 |
0 |
T19 |
1511 |
0 |
0 |
0 |
T20 |
74243 |
20 |
0 |
0 |
T21 |
2311 |
0 |
0 |
0 |
T22 |
0 |
18 |
0 |
0 |
T28 |
0 |
44 |
0 |
0 |
T29 |
0 |
64 |
0 |
0 |
T30 |
0 |
72 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
135605050 |
133004069 |
0 |
0 |
T1 |
114257 |
114146 |
0 |
0 |
T2 |
173029 |
171769 |
0 |
0 |
T3 |
467931 |
467456 |
0 |
0 |
T4 |
2591 |
2580 |
0 |
0 |
T5 |
2143 |
2037 |
0 |
0 |
T16 |
2358 |
2331 |
0 |
0 |
T17 |
1846 |
1659 |
0 |
0 |
T18 |
1057 |
963 |
0 |
0 |
T19 |
1511 |
1418 |
0 |
0 |
T20 |
74243 |
74149 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
| Total | Covered | Percent |
Conditions | 12 | 11 | 91.67 |
Logical | 12 | 11 | 91.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Covered | T2,T3,T28 |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
135605050 |
234010 |
0 |
0 |
T1 |
114257 |
275 |
0 |
0 |
T2 |
173029 |
1218 |
0 |
0 |
T3 |
467931 |
1958 |
0 |
0 |
T5 |
2143 |
0 |
0 |
0 |
T9 |
0 |
1386 |
0 |
0 |
T10 |
0 |
2349 |
0 |
0 |
T16 |
2358 |
0 |
0 |
0 |
T17 |
1846 |
0 |
0 |
0 |
T18 |
1057 |
0 |
0 |
0 |
T19 |
1511 |
0 |
0 |
0 |
T20 |
74243 |
188 |
0 |
0 |
T21 |
2311 |
0 |
0 |
0 |
T22 |
0 |
258 |
0 |
0 |
T28 |
0 |
660 |
0 |
0 |
T29 |
0 |
948 |
0 |
0 |
T30 |
0 |
1086 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
100516649 |
99931727 |
0 |
0 |
T1 |
27681 |
27671 |
0 |
0 |
T2 |
822520 |
819139 |
0 |
0 |
T3 |
651966 |
651625 |
0 |
0 |
T4 |
5175 |
5158 |
0 |
0 |
T5 |
535 |
514 |
0 |
0 |
T16 |
1705 |
1695 |
0 |
0 |
T17 |
450 |
419 |
0 |
0 |
T18 |
264 |
247 |
0 |
0 |
T19 |
688 |
667 |
0 |
0 |
T20 |
20559 |
20531 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
135605050 |
30312 |
0 |
0 |
T1 |
114257 |
20 |
0 |
0 |
T2 |
173029 |
151 |
0 |
0 |
T3 |
467931 |
480 |
0 |
0 |
T5 |
2143 |
0 |
0 |
0 |
T9 |
0 |
97 |
0 |
0 |
T10 |
0 |
289 |
0 |
0 |
T16 |
2358 |
0 |
0 |
0 |
T17 |
1846 |
0 |
0 |
0 |
T18 |
1057 |
0 |
0 |
0 |
T19 |
1511 |
0 |
0 |
0 |
T20 |
74243 |
20 |
0 |
0 |
T21 |
2311 |
0 |
0 |
0 |
T22 |
0 |
18 |
0 |
0 |
T28 |
0 |
44 |
0 |
0 |
T29 |
0 |
64 |
0 |
0 |
T30 |
0 |
72 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
135605050 |
133004069 |
0 |
0 |
T1 |
114257 |
114146 |
0 |
0 |
T2 |
173029 |
171769 |
0 |
0 |
T3 |
467931 |
467456 |
0 |
0 |
T4 |
2591 |
2580 |
0 |
0 |
T5 |
2143 |
2037 |
0 |
0 |
T16 |
2358 |
2331 |
0 |
0 |
T17 |
1846 |
1659 |
0 |
0 |
T18 |
1057 |
963 |
0 |
0 |
T19 |
1511 |
1418 |
0 |
0 |
T20 |
74243 |
74149 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
| Total | Covered | Percent |
Conditions | 12 | 11 | 91.67 |
Logical | 12 | 11 | 91.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Covered | T2,T3,T28 |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
135605050 |
104271 |
0 |
0 |
T1 |
114257 |
98 |
0 |
0 |
T2 |
173029 |
525 |
0 |
0 |
T3 |
467931 |
1200 |
0 |
0 |
T5 |
2143 |
0 |
0 |
0 |
T9 |
0 |
475 |
0 |
0 |
T10 |
0 |
1001 |
0 |
0 |
T16 |
2358 |
0 |
0 |
0 |
T17 |
1846 |
0 |
0 |
0 |
T18 |
1057 |
0 |
0 |
0 |
T19 |
1511 |
0 |
0 |
0 |
T20 |
74243 |
74 |
0 |
0 |
T21 |
2311 |
0 |
0 |
0 |
T22 |
0 |
92 |
0 |
0 |
T28 |
0 |
270 |
0 |
0 |
T29 |
0 |
329 |
0 |
0 |
T30 |
0 |
450 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430254007 |
425305886 |
0 |
0 |
T1 |
115410 |
115298 |
0 |
0 |
T2 |
354472 |
351847 |
0 |
0 |
T3 |
273756 |
273476 |
0 |
0 |
T4 |
21590 |
21492 |
0 |
0 |
T5 |
2255 |
2143 |
0 |
0 |
T16 |
7146 |
7063 |
0 |
0 |
T17 |
1943 |
1745 |
0 |
0 |
T18 |
1101 |
1004 |
0 |
0 |
T19 |
2964 |
2781 |
0 |
0 |
T20 |
115706 |
115552 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
135605050 |
30358 |
0 |
0 |
T1 |
114257 |
20 |
0 |
0 |
T2 |
173029 |
151 |
0 |
0 |
T3 |
467931 |
480 |
0 |
0 |
T5 |
2143 |
0 |
0 |
0 |
T9 |
0 |
97 |
0 |
0 |
T10 |
0 |
289 |
0 |
0 |
T16 |
2358 |
0 |
0 |
0 |
T17 |
1846 |
0 |
0 |
0 |
T18 |
1057 |
0 |
0 |
0 |
T19 |
1511 |
0 |
0 |
0 |
T20 |
74243 |
20 |
0 |
0 |
T21 |
2311 |
0 |
0 |
0 |
T22 |
0 |
18 |
0 |
0 |
T28 |
0 |
44 |
0 |
0 |
T29 |
0 |
64 |
0 |
0 |
T30 |
0 |
72 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
135605050 |
133004069 |
0 |
0 |
T1 |
114257 |
114146 |
0 |
0 |
T2 |
173029 |
171769 |
0 |
0 |
T3 |
467931 |
467456 |
0 |
0 |
T4 |
2591 |
2580 |
0 |
0 |
T5 |
2143 |
2037 |
0 |
0 |
T16 |
2358 |
2331 |
0 |
0 |
T17 |
1846 |
1659 |
0 |
0 |
T18 |
1057 |
963 |
0 |
0 |
T19 |
1511 |
1418 |
0 |
0 |
T20 |
74243 |
74149 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
| Total | Covered | Percent |
Conditions | 12 | 11 | 91.67 |
Logical | 12 | 11 | 91.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Covered | T2,T3,T28 |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
135605050 |
148342 |
0 |
0 |
T1 |
114257 |
162 |
0 |
0 |
T2 |
173029 |
911 |
0 |
0 |
T3 |
467931 |
1489 |
0 |
0 |
T5 |
2143 |
0 |
0 |
0 |
T9 |
0 |
785 |
0 |
0 |
T10 |
0 |
1469 |
0 |
0 |
T16 |
2358 |
0 |
0 |
0 |
T17 |
1846 |
0 |
0 |
0 |
T18 |
1057 |
0 |
0 |
0 |
T19 |
1511 |
0 |
0 |
0 |
T20 |
74243 |
111 |
0 |
0 |
T21 |
2311 |
0 |
0 |
0 |
T22 |
0 |
143 |
0 |
0 |
T28 |
0 |
355 |
0 |
0 |
T29 |
0 |
523 |
0 |
0 |
T30 |
0 |
602 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206654856 |
204283812 |
0 |
0 |
T1 |
55398 |
55344 |
0 |
0 |
T2 |
171589 |
170329 |
0 |
0 |
T3 |
131635 |
131501 |
0 |
0 |
T4 |
10363 |
10317 |
0 |
0 |
T5 |
1082 |
1029 |
0 |
0 |
T16 |
3429 |
3390 |
0 |
0 |
T17 |
933 |
838 |
0 |
0 |
T18 |
528 |
482 |
0 |
0 |
T19 |
1423 |
1335 |
0 |
0 |
T20 |
49780 |
49706 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
135605050 |
30183 |
0 |
0 |
T1 |
114257 |
20 |
0 |
0 |
T2 |
173029 |
151 |
0 |
0 |
T3 |
467931 |
480 |
0 |
0 |
T5 |
2143 |
0 |
0 |
0 |
T9 |
0 |
97 |
0 |
0 |
T10 |
0 |
289 |
0 |
0 |
T16 |
2358 |
0 |
0 |
0 |
T17 |
1846 |
0 |
0 |
0 |
T18 |
1057 |
0 |
0 |
0 |
T19 |
1511 |
0 |
0 |
0 |
T20 |
74243 |
20 |
0 |
0 |
T21 |
2311 |
0 |
0 |
0 |
T22 |
0 |
18 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
T29 |
0 |
57 |
0 |
0 |
T30 |
0 |
61 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
135605050 |
133004069 |
0 |
0 |
T1 |
114257 |
114146 |
0 |
0 |
T2 |
173029 |
171769 |
0 |
0 |
T3 |
467931 |
467456 |
0 |
0 |
T4 |
2591 |
2580 |
0 |
0 |
T5 |
2143 |
2037 |
0 |
0 |
T16 |
2358 |
2331 |
0 |
0 |
T17 |
1846 |
1659 |
0 |
0 |
T18 |
1057 |
963 |
0 |
0 |
T19 |
1511 |
1418 |
0 |
0 |
T20 |
74243 |
74149 |
0 |
0 |