Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	306999	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1367144

1

T5

3

T6

6

T24

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	429368	1			T5	2		T26	31		T27	7
values[0x0]	575981	1			T5	5		T6	17		T24	9
values[0x1]	668794	1			T6	22		T24	10		T25	13

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	185553	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1488590

1

T5

3

T6

11

T24

7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5803	1			T27	1		T2	6		T4	1
valid_sources[0x01]	5772	1			T30	1		T18	3		T2	6
valid_sources[0x02]	5748	1			T2	19		T3	2		T11	134
valid_sources[0x03]	6651	1			T2	12		T11	167		T12	88
valid_sources[0x04]	5635	1			T2	4		T11	186		T12	118
valid_sources[0x05]	6127	1			T2	2		T11	153		T12	83
valid_sources[0x06]	6224	1			T30	4		T2	2		T4	5
valid_sources[0x07]	6119	1			T29	1		T2	5		T22	1
valid_sources[0x08]	7349	1			T29	1		T2	15		T4	1
valid_sources[0x09]	6485	1			T18	1		T2	9		T4	7
valid_sources[0x0a]	6378	1			T18	1		T2	5		T4	4
valid_sources[0x0b]	7482	1			T3	3		T35	1		T11	139
valid_sources[0x0c]	6119	1			T6	1		T26	1		T20	3
valid_sources[0x0d]	6445	1			T27	1		T29	2		T2	11
valid_sources[0x0e]	6147	1			T2	8		T19	3		T4	4
valid_sources[0x0f]	6675	1			T26	2		T27	1		T2	2
valid_sources[0x10]	6491	1			T28	10		T2	5		T3	1
valid_sources[0x11]	7742	1			T26	1		T30	2		T2	9
valid_sources[0x12]	6644	1			T2	7		T11	165		T12	53
valid_sources[0x13]	6813	1			T2	4		T19	3		T4	1
valid_sources[0x14]	6253	1			T26	1		T2	5		T3	3
valid_sources[0x15]	6012	1			T30	1		T2	11		T20	2
valid_sources[0x16]	7160	1			T2	15		T20	1		T3	4
valid_sources[0x17]	5973	1			T26	1		T2	11		T3	7
valid_sources[0x18]	6100	1			T30	1		T2	8		T20	1
valid_sources[0x19]	6135	1			T30	1		T2	1		T4	1
valid_sources[0x1a]	5974	1			T25	2		T26	1		T29	2
valid_sources[0x1b]	6211	1			T2	22		T22	17		T3	4
valid_sources[0x1c]	6785	1			T2	17		T3	3		T11	149
valid_sources[0x1d]	6011	1			T18	2		T2	8		T4	3
valid_sources[0x1e]	6491	1			T26	2		T2	10		T3	5
valid_sources[0x1f]	5911	1			T29	2		T2	10		T20	2
valid_sources[0x20]	5960	1			T6	1		T2	8		T35	1
valid_sources[0x21]	6856	1			T2	10		T3	9		T11	145
valid_sources[0x22]	5982	1			T30	3		T2	3		T19	3
valid_sources[0x23]	7064	1			T26	1		T2	3		T4	1
valid_sources[0x24]	6384	1			T27	2		T30	1		T2	12
valid_sources[0x25]	6073	1			T30	2		T2	6		T19	3
valid_sources[0x26]	6489	1			T2	8		T3	1		T11	149
valid_sources[0x27]	6084	1			T6	3		T26	1		T27	1
valid_sources[0x28]	7217	1			T6	1		T29	2		T2	17
valid_sources[0x29]	6110	1			T2	5		T11	124		T12	55
valid_sources[0x2a]	6615	1			T6	1		T24	1		T26	1
valid_sources[0x2b]	6934	1			T5	7		T6	2		T18	1
valid_sources[0x2c]	6153	1			T26	1		T29	6		T18	1
valid_sources[0x2d]	6796	1			T6	1		T26	1		T30	1
valid_sources[0x2e]	7047	1			T2	3		T19	1		T3	8
valid_sources[0x2f]	5814	1			T2	3		T3	12		T111	2
valid_sources[0x30]	6020	1			T2	5		T4	1		T3	4
valid_sources[0x31]	7206	1			T2	3		T19	3		T3	4
valid_sources[0x32]	6478	1			T2	10		T20	1		T11	160
valid_sources[0x33]	6527	1			T25	3		T29	4		T18	4
valid_sources[0x34]	5466	1			T24	2		T26	1		T30	1
valid_sources[0x35]	6230	1			T24	2		T26	1		T2	7
valid_sources[0x36]	6556	1			T6	1		T26	2		T30	2
valid_sources[0x37]	6257	1			T29	1		T30	1		T2	7
valid_sources[0x38]	6459	1			T24	1		T2	4		T19	1
valid_sources[0x39]	6619	1			T30	2		T2	8		T4	3
valid_sources[0x3a]	6244	1			T26	1		T2	3		T4	1
valid_sources[0x3b]	6246	1			T24	2		T18	1		T2	7
valid_sources[0x3c]	8128	1			T2	5		T3	2		T11	144
valid_sources[0x3d]	6620	1			T18	2		T2	21		T20	1
valid_sources[0x3e]	6023	1			T27	1		T2	10		T19	1
valid_sources[0x3f]	8241	1			T6	1		T2	16		T3	1
valid_sources[0x40]	8223	1			T6	2		T26	1		T27	1
valid_sources[0x41]	6748	1			T26	2		T2	3		T19	1
valid_sources[0x42]	5831	1			T18	1		T2	8		T4	3
valid_sources[0x43]	6891	1			T26	1		T29	4		T18	1
valid_sources[0x44]	6605	1			T26	1		T2	4		T3	12
valid_sources[0x45]	6102	1			T26	1		T30	1		T2	13
valid_sources[0x46]	6540	1			T2	4		T3	3		T36	5
valid_sources[0x47]	7511	1			T2	2		T3	3		T11	172
valid_sources[0x48]	6440	1			T29	1		T1	246		T3	1
valid_sources[0x49]	6396	1			T26	1		T2	5		T20	1
valid_sources[0x4a]	8068	1			T26	1		T2	9		T4	2
valid_sources[0x4b]	7273	1			T2	5		T20	1		T11	168
valid_sources[0x4c]	6149	1			T6	1		T25	1		T2	4
valid_sources[0x4d]	5801	1			T26	1		T18	2		T2	9
valid_sources[0x4e]	6500	1			T18	3		T2	8		T111	7
valid_sources[0x4f]	6365	1			T18	2		T2	3		T4	1
valid_sources[0x50]	6264	1			T2	10		T4	3		T3	5
valid_sources[0x51]	6666	1			T6	2		T2	11		T3	1
valid_sources[0x52]	7533	1			T2	2		T19	8		T3	2
valid_sources[0x53]	6814	1			T2	5		T3	7		T11	123
valid_sources[0x54]	9151	1			T2	3		T11	151		T12	140
valid_sources[0x55]	6640	1			T26	1		T2	3		T11	152
valid_sources[0x56]	7693	1			T67	1		T2	15		T19	1
valid_sources[0x57]	7806	1			T30	2		T2	18		T4	2
valid_sources[0x58]	6442	1			T18	1		T2	5		T3	9
valid_sources[0x59]	6398	1			T24	2		T27	3		T2	2
valid_sources[0x5a]	6644	1			T29	5		T2	3		T4	2
valid_sources[0x5b]	6322	1			T26	1		T29	3		T2	6
valid_sources[0x5c]	6094	1			T18	1		T2	5		T3	3
valid_sources[0x5d]	6471	1			T24	5		T2	3		T3	11
valid_sources[0x5e]	6122	1			T27	2		T2	8		T20	1
valid_sources[0x5f]	6170	1			T2	5		T19	1		T20	1
valid_sources[0x60]	6299	1			T6	1		T29	1		T2	10
valid_sources[0x61]	6645	1			T2	13		T3	4		T11	174
valid_sources[0x62]	5938	1			T26	1		T27	2		T2	5
valid_sources[0x63]	6552	1			T25	2		T30	1		T18	1
valid_sources[0x64]	5699	1			T25	2		T2	4		T3	2
valid_sources[0x65]	6493	1			T3	3		T11	145		T12	96
valid_sources[0x66]	6146	1			T27	1		T18	1		T2	16
valid_sources[0x67]	6042	1			T30	1		T2	4		T3	4
valid_sources[0x68]	6092	1			T2	14		T4	1		T3	3
valid_sources[0x69]	6025	1			T2	11		T11	133		T12	97
valid_sources[0x6a]	6163	1			T2	14		T3	4		T11	162
valid_sources[0x6b]	6300	1			T26	1		T2	2		T3	5
valid_sources[0x6c]	6456	1			T2	7		T19	1		T20	2
valid_sources[0x6d]	6761	1			T30	3		T18	1		T2	14
valid_sources[0x6e]	6589	1			T2	8		T19	1		T111	14
valid_sources[0x6f]	6408	1			T30	1		T2	1		T3	6
valid_sources[0x70]	7000	1			T30	1		T2	5		T19	2
valid_sources[0x71]	5856	1			T6	1		T24	1		T26	1
valid_sources[0x72]	6793	1			T29	1		T18	1		T2	17
valid_sources[0x73]	6613	1			T25	1		T2	12		T3	2
valid_sources[0x74]	6864	1			T6	4		T2	4		T3	5
valid_sources[0x75]	6478	1			T26	1		T2	20		T20	1
valid_sources[0x76]	7030	1			T2	4		T20	1		T3	10
valid_sources[0x77]	7101	1			T2	10		T4	1		T3	6
valid_sources[0x78]	7172	1			T6	2		T26	1		T30	2
valid_sources[0x79]	6300	1			T2	3		T3	7		T35	3
valid_sources[0x7a]	7468	1			T2	6		T19	4		T4	1
valid_sources[0x7b]	6710	1			T2	9		T19	2		T4	2
valid_sources[0x7c]	6214	1			T30	2		T2	2		T21	1
valid_sources[0x7d]	6651	1			T18	1		T2	5		T3	10
valid_sources[0x7e]	6084	1			T29	1		T2	5		T11	158
valid_sources[0x7f]	8023	1			T6	1		T26	1		T2	9
valid_sources[0x80]	6430	1			T2	2		T11	139		T12	107

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

352446

1

T5

1

T26

13

T27

2

values[0x0]

all_enables

biggest_size

521910

1

T5

2

T6

4

T24

2

values[0x1]

all_enables

biggest_size

492788

1

T6

2

T24

4

T25

3