Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T5,T26,T27 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T5,T26,T27 |
1 | 1 | Covered | T5,T26,T27 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T26,T27 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
274708415 |
274706093 |
0 |
0 |
selKnown1 |
664052727 |
664050405 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
274708415 |
274706093 |
0 |
0 |
T5 |
5341 |
5338 |
0 |
0 |
T6 |
5227 |
5224 |
0 |
0 |
T7 |
7082 |
7079 |
0 |
0 |
T24 |
5025 |
5022 |
0 |
0 |
T25 |
5122 |
5119 |
0 |
0 |
T26 |
3053 |
3050 |
0 |
0 |
T27 |
6872 |
6869 |
0 |
0 |
T28 |
1745 |
1742 |
0 |
0 |
T29 |
4346 |
4343 |
0 |
0 |
T30 |
2457 |
2454 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
664052727 |
664050405 |
0 |
0 |
T5 |
12663 |
12660 |
0 |
0 |
T6 |
12783 |
12780 |
0 |
0 |
T7 |
17358 |
17355 |
0 |
0 |
T24 |
12300 |
12297 |
0 |
0 |
T25 |
12612 |
12609 |
0 |
0 |
T26 |
6828 |
6825 |
0 |
0 |
T27 |
16260 |
16257 |
0 |
0 |
T28 |
4263 |
4260 |
0 |
0 |
T29 |
9969 |
9966 |
0 |
0 |
T30 |
6216 |
6213 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
109955818 |
109955044 |
0 |
0 |
selKnown1 |
221350909 |
221350135 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
109955818 |
109955044 |
0 |
0 |
T5 |
2185 |
2184 |
0 |
0 |
T6 |
2091 |
2090 |
0 |
0 |
T7 |
2833 |
2832 |
0 |
0 |
T24 |
2010 |
2009 |
0 |
0 |
T25 |
2049 |
2048 |
0 |
0 |
T26 |
1290 |
1289 |
0 |
0 |
T27 |
2793 |
2792 |
0 |
0 |
T28 |
698 |
697 |
0 |
0 |
T29 |
1827 |
1826 |
0 |
0 |
T30 |
983 |
982 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
221350909 |
221350135 |
0 |
0 |
T5 |
4221 |
4220 |
0 |
0 |
T6 |
4261 |
4260 |
0 |
0 |
T7 |
5786 |
5785 |
0 |
0 |
T24 |
4100 |
4099 |
0 |
0 |
T25 |
4204 |
4203 |
0 |
0 |
T26 |
2276 |
2275 |
0 |
0 |
T27 |
5420 |
5419 |
0 |
0 |
T28 |
1421 |
1420 |
0 |
0 |
T29 |
3323 |
3322 |
0 |
0 |
T30 |
2072 |
2071 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T5,T26,T27 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T5,T26,T27 |
1 | 1 | Covered | T5,T26,T27 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T26,T27 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
109775088 |
109774314 |
0 |
0 |
selKnown1 |
221350909 |
221350135 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
109775088 |
109774314 |
0 |
0 |
T5 |
2064 |
2063 |
0 |
0 |
T6 |
2091 |
2090 |
0 |
0 |
T7 |
2833 |
2832 |
0 |
0 |
T24 |
2010 |
2009 |
0 |
0 |
T25 |
2049 |
2048 |
0 |
0 |
T26 |
1119 |
1118 |
0 |
0 |
T27 |
2684 |
2683 |
0 |
0 |
T28 |
698 |
697 |
0 |
0 |
T29 |
1608 |
1607 |
0 |
0 |
T30 |
983 |
982 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
221350909 |
221350135 |
0 |
0 |
T5 |
4221 |
4220 |
0 |
0 |
T6 |
4261 |
4260 |
0 |
0 |
T7 |
5786 |
5785 |
0 |
0 |
T24 |
4100 |
4099 |
0 |
0 |
T25 |
4204 |
4203 |
0 |
0 |
T26 |
2276 |
2275 |
0 |
0 |
T27 |
5420 |
5419 |
0 |
0 |
T28 |
1421 |
1420 |
0 |
0 |
T29 |
3323 |
3322 |
0 |
0 |
T30 |
2072 |
2071 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
54977509 |
54976735 |
0 |
0 |
selKnown1 |
221350909 |
221350135 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
54977509 |
54976735 |
0 |
0 |
T5 |
1092 |
1091 |
0 |
0 |
T6 |
1045 |
1044 |
0 |
0 |
T7 |
1416 |
1415 |
0 |
0 |
T24 |
1005 |
1004 |
0 |
0 |
T25 |
1024 |
1023 |
0 |
0 |
T26 |
644 |
643 |
0 |
0 |
T27 |
1395 |
1394 |
0 |
0 |
T28 |
349 |
348 |
0 |
0 |
T29 |
911 |
910 |
0 |
0 |
T30 |
491 |
490 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
221350909 |
221350135 |
0 |
0 |
T5 |
4221 |
4220 |
0 |
0 |
T6 |
4261 |
4260 |
0 |
0 |
T7 |
5786 |
5785 |
0 |
0 |
T24 |
4100 |
4099 |
0 |
0 |
T25 |
4204 |
4203 |
0 |
0 |
T26 |
2276 |
2275 |
0 |
0 |
T27 |
5420 |
5419 |
0 |
0 |
T28 |
1421 |
1420 |
0 |
0 |
T29 |
3323 |
3322 |
0 |
0 |
T30 |
2072 |
2071 |
0 |
0 |