Module Definition
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Module Instance : tb.dut.u_main_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
i_cg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_io_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
i_cg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_io_div2_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
i_cg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_io_div4_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
i_cg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_usb_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
i_cg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_clk_io_div4_peri_cg.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_io_div4_peri_cg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_clk_io_div2_peri_cg.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_io_div2_peri_cg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_clk_io_peri_cg.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_io_peri_cg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_clk_usb_peri_cg.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_usb_peri_cg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_clk_main_aes_trans.u_cg.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_cg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_clk_main_hmac_trans.u_cg.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_cg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_clk_main_kmac_trans.u_cg.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_cg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_clk_main_otbn_trans.u_cg.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_cg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_gating
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS2222100.00
CONT_ASSIGN2611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
22 1 1
23 1 1
MISSING_ELSE
26 1 1


Cond Coverage for Module : prim_generic_clock_gating
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       23
 EXPRESSION (en_i | test_en_i)
             --1-   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT6,T25,T26
10CoveredT5,T6,T7

 LINE       26
 EXPRESSION (en_latch & clk_i)
             ----1---   --2--
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT5,T6,T7
11CoveredT5,T6,T7

Branch Coverage for Module : prim_generic_clock_gating
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 22 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 22 if ((!clk_i))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7

Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS2222100.00
CONT_ASSIGN2611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
22 1 1
23 1 1
MISSING_ELSE
26 1 1


Cond Coverage for Instance : tb.dut.u_main_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       23
 EXPRESSION (en_i | test_en_i)
             --1-   ----2----
-1--2-StatusTests
00CoveredT5,T7,T24
01CoveredT6,T25,T26
10CoveredT5,T6,T7

 LINE       26
 EXPRESSION (en_latch & clk_i)
             ----1---   --2--
-1--2-StatusTests
01CoveredT5,T7,T24
10CoveredT5,T6,T7
11CoveredT5,T6,T7

Branch Coverage for Instance : tb.dut.u_main_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 22 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 22 if ((!clk_i))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7

Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS2222100.00
CONT_ASSIGN2611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
22 1 1
23 1 1
MISSING_ELSE
26 1 1


Cond Coverage for Instance : tb.dut.u_io_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       23
 EXPRESSION (en_i | test_en_i)
             --1-   ----2----
-1--2-StatusTests
00CoveredT5,T7,T24
01CoveredT6,T25,T26
10CoveredT5,T6,T7

 LINE       26
 EXPRESSION (en_latch & clk_i)
             ----1---   --2--
-1--2-StatusTests
01CoveredT5,T7,T24
10CoveredT5,T6,T7
11CoveredT5,T6,T7

Branch Coverage for Instance : tb.dut.u_io_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 22 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 22 if ((!clk_i))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7

Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS2222100.00
CONT_ASSIGN2611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
22 1 1
23 1 1
MISSING_ELSE
26 1 1


Cond Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       23
 EXPRESSION (en_i | test_en_i)
             --1-   ----2----
-1--2-StatusTests
00CoveredT5,T7,T24
01CoveredT6,T25,T26
10CoveredT5,T6,T7

 LINE       26
 EXPRESSION (en_latch & clk_i)
             ----1---   --2--
-1--2-StatusTests
01CoveredT5,T7,T24
10CoveredT5,T6,T7
11CoveredT5,T6,T7

Branch Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 22 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 22 if ((!clk_i))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7

Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS2222100.00
CONT_ASSIGN2611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
22 1 1
23 1 1
MISSING_ELSE
26 1 1


Cond Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       23
 EXPRESSION (en_i | test_en_i)
             --1-   ----2----
-1--2-StatusTests
00CoveredT5,T7,T24
01CoveredT6,T25,T26
10CoveredT5,T6,T7

 LINE       26
 EXPRESSION (en_latch & clk_i)
             ----1---   --2--
-1--2-StatusTests
01CoveredT5,T7,T24
10CoveredT5,T6,T7
11CoveredT5,T6,T7

Branch Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 22 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 22 if ((!clk_i))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7

Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS2222100.00
CONT_ASSIGN2611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
22 1 1
23 1 1
MISSING_ELSE
26 1 1


Cond Coverage for Instance : tb.dut.u_usb_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       23
 EXPRESSION (en_i | test_en_i)
             --1-   ----2----
-1--2-StatusTests
00CoveredT5,T7,T24
01CoveredT6,T25,T26
10CoveredT5,T6,T7

 LINE       26
 EXPRESSION (en_latch & clk_i)
             ----1---   --2--
-1--2-StatusTests
01CoveredT5,T7,T24
10CoveredT5,T6,T7
11CoveredT5,T6,T7

Branch Coverage for Instance : tb.dut.u_usb_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 22 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 22 if ((!clk_i))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7

Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_cg.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS2222100.00
CONT_ASSIGN2611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
22 1 1
23 1 1
MISSING_ELSE
26 1 1


Cond Coverage for Instance : tb.dut.u_clk_io_div4_peri_cg.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       23
 EXPRESSION (en_i | test_en_i)
             --1-   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT6,T25,T26
10CoveredT5,T6,T7

 LINE       26
 EXPRESSION (en_latch & clk_i)
             ----1---   --2--
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT5,T6,T7
11CoveredT5,T6,T7

Branch Coverage for Instance : tb.dut.u_clk_io_div4_peri_cg.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 22 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 22 if ((!clk_i))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7

Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_cg.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS2222100.00
CONT_ASSIGN2611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
22 1 1
23 1 1
MISSING_ELSE
26 1 1


Cond Coverage for Instance : tb.dut.u_clk_io_div2_peri_cg.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       23
 EXPRESSION (en_i | test_en_i)
             --1-   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT6,T25,T26
10CoveredT5,T6,T7

 LINE       26
 EXPRESSION (en_latch & clk_i)
             ----1---   --2--
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT5,T6,T7
11CoveredT5,T6,T7

Branch Coverage for Instance : tb.dut.u_clk_io_div2_peri_cg.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 22 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 22 if ((!clk_i))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7

Line Coverage for Instance : tb.dut.u_clk_io_peri_cg.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS2222100.00
CONT_ASSIGN2611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
22 1 1
23 1 1
MISSING_ELSE
26 1 1


Cond Coverage for Instance : tb.dut.u_clk_io_peri_cg.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       23
 EXPRESSION (en_i | test_en_i)
             --1-   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT6,T25,T26
10CoveredT5,T6,T7

 LINE       26
 EXPRESSION (en_latch & clk_i)
             ----1---   --2--
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT5,T6,T7
11CoveredT5,T6,T7

Branch Coverage for Instance : tb.dut.u_clk_io_peri_cg.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 22 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 22 if ((!clk_i))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7

Line Coverage for Instance : tb.dut.u_clk_usb_peri_cg.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS2222100.00
CONT_ASSIGN2611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
22 1 1
23 1 1
MISSING_ELSE
26 1 1


Cond Coverage for Instance : tb.dut.u_clk_usb_peri_cg.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       23
 EXPRESSION (en_i | test_en_i)
             --1-   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT6,T25,T26
10CoveredT5,T6,T7

 LINE       26
 EXPRESSION (en_latch & clk_i)
             ----1---   --2--
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT5,T6,T7
11CoveredT5,T6,T7

Branch Coverage for Instance : tb.dut.u_clk_usb_peri_cg.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 22 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 22 if ((!clk_i))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_cg.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS2222100.00
CONT_ASSIGN2611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
22 1 1
23 1 1
MISSING_ELSE
26 1 1


Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_cg.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       23
 EXPRESSION (en_i | test_en_i)
             --1-   ----2----
-1--2-StatusTests
00CoveredT30,T2,T20
01CoveredT2,T20,T3
10CoveredT5,T6,T7

 LINE       26
 EXPRESSION (en_latch & clk_i)
             ----1---   --2--
-1--2-StatusTests
01CoveredT30,T2,T20
10CoveredT5,T6,T7
11CoveredT5,T6,T7

Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_cg.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 22 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 22 if ((!clk_i))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_cg.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS2222100.00
CONT_ASSIGN2611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
22 1 1
23 1 1
MISSING_ELSE
26 1 1


Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_cg.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       23
 EXPRESSION (en_i | test_en_i)
             --1-   ----2----
-1--2-StatusTests
00CoveredT30,T2,T20
01CoveredT2,T3,T32
10CoveredT5,T6,T7

 LINE       26
 EXPRESSION (en_latch & clk_i)
             ----1---   --2--
-1--2-StatusTests
01CoveredT30,T2,T20
10CoveredT5,T6,T7
11CoveredT5,T6,T7

Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_cg.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 22 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 22 if ((!clk_i))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_cg.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS2222100.00
CONT_ASSIGN2611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
22 1 1
23 1 1
MISSING_ELSE
26 1 1


Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_cg.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       23
 EXPRESSION (en_i | test_en_i)
             --1-   ----2----
-1--2-StatusTests
00CoveredT30,T2,T3
01CoveredT2,T20,T3
10CoveredT5,T6,T7

 LINE       26
 EXPRESSION (en_latch & clk_i)
             ----1---   --2--
-1--2-StatusTests
01CoveredT30,T2,T3
10CoveredT5,T6,T7
11CoveredT5,T6,T7

Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_cg.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 22 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 22 if ((!clk_i))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_cg.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS2222100.00
CONT_ASSIGN2611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
22 1 1
23 1 1
MISSING_ELSE
26 1 1


Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_cg.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       23
 EXPRESSION (en_i | test_en_i)
             --1-   ----2----
-1--2-StatusTests
00CoveredT30,T2,T3
01CoveredT2,T20,T3
10CoveredT5,T6,T7

 LINE       26
 EXPRESSION (en_latch & clk_i)
             ----1---   --2--
-1--2-StatusTests
01CoveredT30,T2,T3
10CoveredT5,T6,T7
11CoveredT5,T6,T7

Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_cg.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 22 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 22 if ((!clk_i))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%