Line Coverage for Module :
prim_generic_clock_gating
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 22 | 2 | 2 | 100.00 |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
22 |
1 |
1 |
23 |
1 |
1 |
|
|
|
MISSING_ELSE |
26 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_gating
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 23
EXPRESSION (en_i | test_en_i)
--1- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T6,T25,T26 |
1 | 0 | Covered | T5,T6,T7 |
LINE 26
EXPRESSION (en_latch & clk_i)
----1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
Branch Coverage for Module :
prim_generic_clock_gating
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
22 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 22 if ((!clk_i))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 22 | 2 | 2 | 100.00 |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
22 |
1 |
1 |
23 |
1 |
1 |
|
|
|
MISSING_ELSE |
26 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_main_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 23
EXPRESSION (en_i | test_en_i)
--1- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T7,T24 |
0 | 1 | Covered | T6,T25,T26 |
1 | 0 | Covered | T5,T6,T7 |
LINE 26
EXPRESSION (en_latch & clk_i)
----1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T7,T24 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_main_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
22 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 22 if ((!clk_i))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 22 | 2 | 2 | 100.00 |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
22 |
1 |
1 |
23 |
1 |
1 |
|
|
|
MISSING_ELSE |
26 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 23
EXPRESSION (en_i | test_en_i)
--1- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T7,T24 |
0 | 1 | Covered | T6,T25,T26 |
1 | 0 | Covered | T5,T6,T7 |
LINE 26
EXPRESSION (en_latch & clk_i)
----1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T7,T24 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_io_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
22 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 22 if ((!clk_i))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 22 | 2 | 2 | 100.00 |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
22 |
1 |
1 |
23 |
1 |
1 |
|
|
|
MISSING_ELSE |
26 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 23
EXPRESSION (en_i | test_en_i)
--1- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T7,T24 |
0 | 1 | Covered | T6,T25,T26 |
1 | 0 | Covered | T5,T6,T7 |
LINE 26
EXPRESSION (en_latch & clk_i)
----1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T7,T24 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
22 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 22 if ((!clk_i))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 22 | 2 | 2 | 100.00 |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
22 |
1 |
1 |
23 |
1 |
1 |
|
|
|
MISSING_ELSE |
26 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 23
EXPRESSION (en_i | test_en_i)
--1- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T7,T24 |
0 | 1 | Covered | T6,T25,T26 |
1 | 0 | Covered | T5,T6,T7 |
LINE 26
EXPRESSION (en_latch & clk_i)
----1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T7,T24 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
22 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 22 if ((!clk_i))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 22 | 2 | 2 | 100.00 |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
22 |
1 |
1 |
23 |
1 |
1 |
|
|
|
MISSING_ELSE |
26 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_usb_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 23
EXPRESSION (en_i | test_en_i)
--1- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T7,T24 |
0 | 1 | Covered | T6,T25,T26 |
1 | 0 | Covered | T5,T6,T7 |
LINE 26
EXPRESSION (en_latch & clk_i)
----1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T7,T24 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_usb_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
22 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 22 if ((!clk_i))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_cg.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 22 | 2 | 2 | 100.00 |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
22 |
1 |
1 |
23 |
1 |
1 |
|
|
|
MISSING_ELSE |
26 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_io_div4_peri_cg.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 23
EXPRESSION (en_i | test_en_i)
--1- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T6,T25,T26 |
1 | 0 | Covered | T5,T6,T7 |
LINE 26
EXPRESSION (en_latch & clk_i)
----1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_io_div4_peri_cg.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
22 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 22 if ((!clk_i))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_cg.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 22 | 2 | 2 | 100.00 |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
22 |
1 |
1 |
23 |
1 |
1 |
|
|
|
MISSING_ELSE |
26 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_io_div2_peri_cg.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 23
EXPRESSION (en_i | test_en_i)
--1- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T6,T25,T26 |
1 | 0 | Covered | T5,T6,T7 |
LINE 26
EXPRESSION (en_latch & clk_i)
----1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_io_div2_peri_cg.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
22 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 22 if ((!clk_i))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Line Coverage for Instance : tb.dut.u_clk_io_peri_cg.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 22 | 2 | 2 | 100.00 |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
22 |
1 |
1 |
23 |
1 |
1 |
|
|
|
MISSING_ELSE |
26 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_io_peri_cg.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 23
EXPRESSION (en_i | test_en_i)
--1- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T6,T25,T26 |
1 | 0 | Covered | T5,T6,T7 |
LINE 26
EXPRESSION (en_latch & clk_i)
----1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_io_peri_cg.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
22 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 22 if ((!clk_i))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Line Coverage for Instance : tb.dut.u_clk_usb_peri_cg.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 22 | 2 | 2 | 100.00 |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
22 |
1 |
1 |
23 |
1 |
1 |
|
|
|
MISSING_ELSE |
26 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_usb_peri_cg.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 23
EXPRESSION (en_i | test_en_i)
--1- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T6,T25,T26 |
1 | 0 | Covered | T5,T6,T7 |
LINE 26
EXPRESSION (en_latch & clk_i)
----1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_usb_peri_cg.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
22 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 22 if ((!clk_i))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_cg.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 22 | 2 | 2 | 100.00 |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
22 |
1 |
1 |
23 |
1 |
1 |
|
|
|
MISSING_ELSE |
26 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_cg.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 23
EXPRESSION (en_i | test_en_i)
--1- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T30,T2,T20 |
0 | 1 | Covered | T2,T20,T3 |
1 | 0 | Covered | T5,T6,T7 |
LINE 26
EXPRESSION (en_latch & clk_i)
----1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T30,T2,T20 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_cg.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
22 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 22 if ((!clk_i))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_cg.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 22 | 2 | 2 | 100.00 |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
22 |
1 |
1 |
23 |
1 |
1 |
|
|
|
MISSING_ELSE |
26 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_cg.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 23
EXPRESSION (en_i | test_en_i)
--1- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T30,T2,T20 |
0 | 1 | Covered | T2,T3,T32 |
1 | 0 | Covered | T5,T6,T7 |
LINE 26
EXPRESSION (en_latch & clk_i)
----1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T30,T2,T20 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_cg.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
22 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 22 if ((!clk_i))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_cg.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 22 | 2 | 2 | 100.00 |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
22 |
1 |
1 |
23 |
1 |
1 |
|
|
|
MISSING_ELSE |
26 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_cg.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 23
EXPRESSION (en_i | test_en_i)
--1- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T30,T2,T3 |
0 | 1 | Covered | T2,T20,T3 |
1 | 0 | Covered | T5,T6,T7 |
LINE 26
EXPRESSION (en_latch & clk_i)
----1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T30,T2,T3 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_cg.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
22 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 22 if ((!clk_i))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_cg.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 22 | 2 | 2 | 100.00 |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
22 |
1 |
1 |
23 |
1 |
1 |
|
|
|
MISSING_ELSE |
26 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_cg.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 23
EXPRESSION (en_i | test_en_i)
--1- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T30,T2,T3 |
0 | 1 | Covered | T2,T20,T3 |
1 | 0 | Covered | T5,T6,T7 |
LINE 26
EXPRESSION (en_latch & clk_i)
----1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T30,T2,T3 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_cg.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
22 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv' or '../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 22 if ((!clk_i))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |