Unified Coverage Report :: Module :: prim_lc_sync

Module : prim_lc_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_clkmgr_byp.u_en_sync	100.00	100.00					100.00
tb.dut.u_clkmgr_byp.u_lc_byp_req	100.00	100.00					100.00

---

Module Instance : tb.dut.u_clkmgr_byp.u_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_clkmgr_byp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_clkmgr_byp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_lc_byp_req

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	2	2

---

Assert Coverage for Module : prim_lc_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1548	1548	0	0
OutputsKnown_A	145803282	141693832	0	0
gen_flops.OutputDelay_A	145803282	141680320	0	4644

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1548	1548	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T24	2	2	0	0
T25	2	2	0	0
T26	2	2	0	0
T27	2	2	0	0
T28	2	2	0	0
T29	2	2	0	0
T30	2	2	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145803282	141693832	0	0
T5	2196	2106	0	0
T6	2306	2190	0	0
T7	2074	1988	0	0
T24	2306	2224	0	0
T25	2100	1986	0	0
T26	4742	4576	0	0
T27	2708	2628	0	0
T28	2874	2712	0	0
T29	4846	4510	0	0
T30	4276	3970	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145803282	141680320	0	4644
T5	2196	2100	0	6
T6	2306	2184	0	6
T7	2074	1982	0	6
T24	2306	2218	0	6
T25	2100	1980	0	6
T26	4742	4570	0	6
T27	2708	2622	0	6
T28	2874	2706	0	6
T29	4846	4504	0	6
T30	4276	3964	0	6

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	774	774	0	0
OutputsKnown_A	72901641	70846916	0	0
gen_flops.OutputDelay_A	72901641	70840160	0	2322

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774	774	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72901641	70846916	0	0
T5	1098	1053	0	0
T6	1153	1095	0	0
T7	1037	994	0	0
T24	1153	1112	0	0
T25	1050	993	0	0
T26	2371	2288	0	0
T27	1354	1314	0	0
T28	1437	1356	0	0
T29	2423	2255	0	0
T30	2138	1985	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72901641	70840160	0	2322
T5	1098	1050	0	3
T6	1153	1092	0	3
T7	1037	991	0	3
T24	1153	1109	0	3
T25	1050	990	0	3
T26	2371	2285	0	3
T27	1354	1311	0	3
T28	1437	1353	0	3
T29	2423	2252	0	3
T30	2138	1982	0	3

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	2	2

---

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	774	774	0	0
OutputsKnown_A	72901641	70846916	0	0
gen_flops.OutputDelay_A	72901641	70840160	0	2322

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774	774	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72901641	70846916	0	0
T5	1098	1053	0	0
T6	1153	1095	0	0
T7	1037	994	0	0
T24	1153	1112	0	0
T25	1050	993	0	0
T26	2371	2288	0	0
T27	1354	1314	0	0
T28	1437	1356	0	0
T29	2423	2255	0	0
T30	2138	1985	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72901641	70840160	0	2322
T5	1098	1050	0	3
T6	1153	1092	0	3
T7	1037	991	0	3
T24	1153	1109	0	3
T25	1050	990	0	3
T26	2371	2285	0	3
T27	1354	1311	0	3
T28	1437	1353	0	3
T29	2423	2252	0	3
T30	2138	1982	0	3