Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	484318	0	0
SrcPulseCheck_M	2147483647	484831	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	484318
T1	313456	156
T2	591141	278
T3	0	226
T4	110392	40
T5	479333	490
T8	0	390
T15	7265	0
T16	14371	0
T17	10946	0
T18	29480	0
T19	906920	970
T20	7791	0
T21	0	248
T24	0	968
T26	0	230
T27	0	838
T56	9426	1
T58	8444	2
T59	17928	2
T60	11648	2
T61	28694	2
T62	9281	1
T63	10896	1
T124	14678	2
T125	17876	3
T126	21018	2
T127	7099	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	484831
T1	163154	156
T2	311426	278
T3	0	226
T4	64544	40
T5	111353	490
T8	0	390
T15	4293	0
T16	6125	0
T17	6464	0
T18	9555	0
T19	530380	970
T20	4551	0
T21	0	248
T24	0	968
T26	0	230
T27	0	838
T56	5056	1
T58	18428	2
T59	16002	2
T60	5136	2
T61	25792	2
T62	8303	1
T63	9597	1
T124	27996	2
T125	32498	3
T126	9080	2
T127	2870	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	277070554	12281	0	0
SrcPulseCheck_M	59576302	12281	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	277070554	12281
T1	65582	12
T2	123123	22
T3	0	14
T4	27212	8
T5	115671	18
T8	0	30
T15	1518	0
T16	3359	0
T17	2236	0
T18	7322	0
T19	174693	38
T20	1635	0
T24	0	40
T26	0	10
T27	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	59576302	12281
T1	64904	12
T2	124413	22
T3	0	14
T4	28346	8
T5	23118	18
T8	0	30
T15	1551	0
T16	1749	0
T17	2329	0
T18	1906	0
T19	220770	38
T20	1635	0
T24	0	40
T26	0	10
T27	0	26

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	277070554	18230	0	0
SrcPulseCheck_M	59576302	18249	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	277070554	18230
T1	65582	12
T2	123123	22
T3	0	14
T4	27212	16
T5	115671	18
T8	0	30
T15	1518	0
T16	3359	0
T17	2236	0
T18	7322	0
T19	174693	38
T20	1635	0
T24	0	40
T26	0	10
T27	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	59576302	18249
T1	64904	12
T2	124413	22
T3	0	14
T4	28346	16
T5	23118	18
T8	0	30
T15	1551	0
T16	1749	0
T17	2329	0
T18	1906	0
T19	220770	38
T20	1635	0
T24	0	40
T26	0	10
T27	0	26

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	59576302	18214	0	0
SrcPulseCheck_M	277070554	18233	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	59576302	18214
T1	64904	12
T2	124413	22
T3	0	14
T4	28346	16
T5	23118	18
T8	0	30
T15	1551	0
T16	1749	0
T17	2329	0
T18	1906	0
T19	220770	38
T20	1635	0
T24	0	40
T26	0	10
T27	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	277070554	18233
T1	65582	12
T2	123123	22
T3	0	14
T4	27212	16
T5	115671	18
T8	0	30
T15	1518	0
T16	3359	0
T17	2236	0
T18	7322	0
T19	174693	38
T20	1635	0
T24	0	40
T26	0	10
T27	0	26

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	137912410	12281	0	0
SrcPulseCheck_M	59576302	12281	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	137912410	12281
T1	32758	12
T2	61528	22
T3	0	14
T4	7568	8
T5	57729	18
T8	0	30
T15	747	0
T16	1647	0
T17	1158	0
T18	3607	0
T19	87280	38
T20	805	0
T24	0	40
T26	0	10
T27	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	59576302	12281
T1	64904	12
T2	124413	22
T3	0	14
T4	28346	8
T5	23118	18
T8	0	30
T15	1551	0
T16	1749	0
T17	2329	0
T18	1906	0
T19	220770	38
T20	1635	0
T24	0	40
T26	0	10
T27	0	26

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	137912410	18175	0	0
SrcPulseCheck_M	59576302	18210	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	137912410	18175
T1	32758	12
T2	61528	22
T3	0	14
T4	7568	16
T5	57729	18
T8	0	30
T15	747	0
T16	1647	0
T17	1158	0
T18	3607	0
T19	87280	38
T20	805	0
T24	0	40
T26	0	10
T27	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	59576302	18210
T1	64904	12
T2	124413	22
T3	0	14
T4	28346	16
T5	23118	18
T8	0	30
T15	1551	0
T16	1749	0
T17	2329	0
T18	1906	0
T19	220770	38
T20	1635	0
T24	0	40
T26	0	10
T27	0	26

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	59576302	18169	0	0
SrcPulseCheck_M	137912410	18179	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	59576302	18169
T1	64904	12
T2	124413	22
T3	0	14
T4	28346	16
T5	23118	18
T8	0	30
T15	1551	0
T16	1749	0
T17	2329	0
T18	1906	0
T19	220770	38
T20	1635	0
T24	0	40
T26	0	10
T27	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	137912410	18179
T1	32758	12
T2	61528	22
T3	0	14
T4	7568	16
T5	57729	18
T8	0	30
T15	747	0
T16	1647	0
T17	1158	0
T18	3607	0
T19	87280	38
T20	805	0
T24	0	40
T26	0	10
T27	0	26

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	68955833	12281	0	0
SrcPulseCheck_M	59576302	12281	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	68955833	12281
T1	16379	12
T2	30764	22
T3	0	14
T4	3784	8
T5	28863	18
T8	0	30
T15	373	0
T16	823	0
T17	578	0
T18	1804	0
T19	43640	38
T20	403	0
T24	0	40
T26	0	10
T27	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	59576302	12281
T1	64904	12
T2	124413	22
T3	0	14
T4	28346	8
T5	23118	18
T8	0	30
T15	1551	0
T16	1749	0
T17	2329	0
T18	1906	0
T19	220770	38
T20	1635	0
T24	0	40
T26	0	10
T27	0	26

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	68955833	18279	0	0
SrcPulseCheck_M	59576302	18329	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	68955833	18279
T1	16379	12
T2	30764	22
T3	0	14
T4	3784	16
T5	28863	18
T8	0	30
T15	373	0
T16	823	0
T17	578	0
T18	1804	0
T19	43640	38
T20	403	0
T24	0	40
T26	0	10
T27	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	59576302	18329
T1	64904	12
T2	124413	22
T3	0	14
T4	28346	16
T5	23118	18
T8	0	30
T15	1551	0
T16	1749	0
T17	2329	0
T18	1906	0
T19	220770	38
T20	1635	0
T24	0	40
T26	0	10
T27	0	26

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	59576302	18279	0	0
SrcPulseCheck_M	68955833	18286	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	59576302	18279
T1	64904	12
T2	124413	22
T3	0	14
T4	28346	16
T5	23118	18
T8	0	30
T15	1551	0
T16	1749	0
T17	2329	0
T18	1906	0
T19	220770	38
T20	1635	0
T24	0	40
T26	0	10
T27	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	68955833	18286
T1	16379	12
T2	30764	22
T3	0	14
T4	3784	16
T5	28863	18
T8	0	30
T15	373	0
T16	823	0
T17	578	0
T18	1804	0
T19	43640	38
T20	403	0
T24	0	40
T26	0	10
T27	0	26

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	293590803	12281	0	0
SrcPulseCheck_M	59576302	12281	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	293590803	12281
T1	68317	12
T2	128257	22
T3	0	14
T4	28346	8
T5	138494	18
T8	0	30
T15	1582	0
T16	3499	0
T17	2329	0
T18	7627	0
T19	205977	38
T20	1703	0
T24	0	40
T26	0	10
T27	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	59576302	12281
T1	64904	12
T2	124413	22
T3	0	14
T4	28346	8
T5	23118	18
T8	0	30
T15	1551	0
T16	1749	0
T17	2329	0
T18	1906	0
T19	220770	38
T20	1635	0
T24	0	40
T26	0	10
T27	0	26

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	293590803	18184	0	0
SrcPulseCheck_M	59576302	18199	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	293590803	18184
T1	68317	12
T2	128257	22
T3	0	14
T4	28346	16
T5	138494	18
T8	0	30
T15	1582	0
T16	3499	0
T17	2329	0
T18	7627	0
T19	205977	38
T20	1703	0
T24	0	40
T26	0	10
T27	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	59576302	18199
T1	64904	12
T2	124413	22
T3	0	14
T4	28346	16
T5	23118	18
T8	0	30
T15	1551	0
T16	1749	0
T17	2329	0
T18	1906	0
T19	220770	38
T20	1635	0
T24	0	40
T26	0	10
T27	0	26

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	59576302	18179	0	0
SrcPulseCheck_M	293590803	18187	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	59576302	18179
T1	64904	12
T2	124413	22
T3	0	14
T4	28346	16
T5	23118	18
T8	0	30
T15	1551	0
T16	1749	0
T17	2329	0
T18	1906	0
T19	220770	38
T20	1635	0
T24	0	40
T26	0	10
T27	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	293590803	18187
T1	68317	12
T2	128257	22
T3	0	14
T4	28346	16
T5	138494	18
T8	0	30
T15	1582	0
T16	3499	0
T17	2329	0
T18	7627	0
T19	205977	38
T20	1703	0
T24	0	40
T26	0	10
T27	0	26

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	141066997	11907	0	0
SrcPulseCheck_M	59576302	12281	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	141066997	11907
T1	32793	12
T2	61564	22
T3	0	14
T4	13606	4
T5	63598	18
T8	0	30
T15	759	0
T16	1680	0
T17	1118	0
T18	3661	0
T19	101750	38
T20	817	0
T24	0	40
T26	0	10
T27	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	59576302	12281
T1	64904	12
T2	124413	22
T3	0	14
T4	28346	8
T5	23118	18
T8	0	30
T15	1551	0
T16	1749	0
T17	2329	0
T18	1906	0
T19	220770	38
T20	1635	0
T24	0	40
T26	0	10
T27	0	26

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	141066997	17986	0	0
SrcPulseCheck_M	59576302	18148	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	141066997	17986
T1	32793	12
T2	61564	22
T3	0	14
T4	13606	12
T5	63598	18
T8	0	30
T15	759	0
T16	1680	0
T17	1118	0
T18	3661	0
T19	101750	38
T20	817	0
T24	0	40
T26	0	10
T27	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	59576302	18148
T1	64904	12
T2	124413	22
T3	0	14
T4	28346	16
T5	23118	18
T8	0	30
T15	1551	0
T16	1749	0
T17	2329	0
T18	1906	0
T19	220770	38
T20	1635	0
T24	0	40
T26	0	10
T27	0	26

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	59576302	17861	0	0
SrcPulseCheck_M	141066997	18008	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	59576302	17861
T1	64904	12
T2	124413	22
T3	0	14
T4	28346	12
T5	23118	18
T8	0	30
T15	1551	0
T16	1749	0
T17	2329	0
T18	1906	0
T19	220770	38
T20	1635	0
T24	0	40
T26	0	10
T27	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	141066997	18008
T1	32793	12
T2	61564	22
T3	0	14
T4	13606	12
T5	63598	18
T8	0	30
T15	759	0
T16	1680	0
T17	1118	0
T18	3661	0
T19	101750	38
T20	817	0
T24	0	40
T26	0	10
T27	0	26

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T55,T57,T61
1	0	Covered	T55,T57,T61
1	1	Covered	T55,T64,T124

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T55,T57,T61
1	0	Covered	T55,T64,T124
1	1	Covered	T55,T57,T61

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	59576302	34	0	0
SrcPulseCheck_M	277070554	34	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	59576302	34
T55	6519	2
T57	8718	1
T60	5824	1
T61	14347	1
T62	9281	1
T64	10709	2
T124	7339	4
T125	8938	1
T126	10509	2
T128	11657	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	277070554	34
T55	21582	2
T57	8718	1
T60	5824	1
T61	27546	1
T62	18183	1
T64	41120	2
T124	29355	4
T125	34323	1
T126	10294	2
T128	11657	2

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T55,T57,T63
1	0	Covered	T55,T57,T63
1	1	Covered	T124,T129,T130

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T55,T57,T63
1	0	Covered	T124,T129,T130
1	1	Covered	T55,T57,T63

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	59576302	34	0	0
SrcPulseCheck_M	277070554	34	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	59576302	34
T55	6519	2
T57	8718	1
T59	8964	1
T61	14347	1
T63	10896	1
T64	10709	2
T65	8803	1
T124	7339	4
T125	8938	1
T131	12263	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	277070554	34
T55	21582	2
T57	8718	1
T59	17929	1
T61	27546	1
T63	20921	1
T64	41120	2
T65	8450	1
T124	29355	4
T125	34323	1
T131	49051	2

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T56,T63,T61
1	0	Covered	T56,T63,T61
1	1	Covered	T58,T60,T124

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T56,T63,T61
1	0	Covered	T58,T60,T124
1	1	Covered	T56,T63,T61

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	59576302	32	0	0
SrcPulseCheck_M	137912410	32	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	59576302	32
T56	4713	1
T58	4222	2
T59	8964	2
T60	5824	2
T61	14347	2
T62	9281	1
T63	10896	1
T124	7339	2
T125	8938	3
T126	10509	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	137912410	32
T56	2528	1
T58	9214	2
T59	8001	2
T60	2568	2
T61	12896	2
T62	8303	1
T63	9597	1
T124	13998	2
T125	16249	3
T126	4540	2

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T56,T61,T58
1	0	Covered	T56,T61,T58
1	1	Covered	T56,T58,T59

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T56,T61,T58
1	0	Covered	T56,T58,T59
1	1	Covered	T56,T61,T58

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	59576302	40	0	0
SrcPulseCheck_M	137912410	40	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	59576302	40
T56	4713	2
T58	4222	2
T59	8964	3
T60	5824	2
T61	14347	3
T124	7339	5
T125	8938	1
T126	10509	3
T127	7099	1
T128	11657	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	137912410	40
T56	2528	2
T58	9214	2
T59	8001	3
T60	2568	2
T61	12896	3
T124	13998	5
T125	16249	1
T126	4540	3
T127	2870	1
T128	4927	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T55,T59,T65
1	0	Covered	T55,T59,T65
1	1	Covered	T128,T132,T133

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T55,T59,T65
1	0	Covered	T128,T132,T133
1	1	Covered	T55,T59,T65

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	59576302	36	0	0
SrcPulseCheck_M	68955833	36	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	59576302	36
T55	6519	1
T59	8964	1
T62	9281	3
T65	8803	1
T124	7339	1
T127	7099	1
T128	11657	3
T132	6843	5
T134	11708	1
T135	11708	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	68955833	36
T55	4997	1
T59	4002	1
T62	4154	3
T65	1850	1
T124	7000	1
T127	1434	1
T128	2466	3
T132	2940	5
T134	2357	1
T135	2492	2

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T55,T56,T59
1	0	Covered	T55,T56,T59
1	1	Covered	T62,T132,T133

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T55,T56,T59
1	0	Covered	T62,T132,T133
1	1	Covered	T55,T56,T59

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	59576302	38	0	0
SrcPulseCheck_M	68955833	38	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	59576302	38
T55	6519	1
T56	4713	1
T59	8964	1
T62	9281	3
T65	8803	1
T124	7339	1
T125	8938	2
T126	10509	1
T128	11657	2
T134	11708	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	68955833	38
T55	4997	1
T56	1262	1
T59	4002	1
T62	4154	3
T65	1850	1
T124	7000	1
T125	8123	2
T126	2269	1
T128	2466	2
T134	2357	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T55,T56,T61
1	0	Covered	T55,T56,T61
1	1	Covered	T62,T125,T128

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T55,T56,T61
1	0	Covered	T62,T125,T128
1	1	Covered	T55,T56,T61

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	59576302	30	0	0
SrcPulseCheck_M	293590803	30	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	59576302	30
T55	6519	1
T56	4713	1
T58	4222	1
T59	8964	1
T61	14347	1
T62	9281	2
T65	8803	1
T125	8938	2
T126	10509	1
T131	12263	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	293590803	30
T55	22483	1
T56	6041	1
T58	20103	1
T59	18677	1
T61	28695	1
T62	18941	2
T65	8803	1
T125	35755	2
T126	10723	1
T131	51097	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T55,T61,T59
1	0	Covered	T55,T61,T59
1	1	Covered	T62,T125,T134

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T55,T61,T59
1	0	Covered	T62,T125,T134
1	1	Covered	T55,T61,T59

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	59576302	34	0	0
SrcPulseCheck_M	293590803	34	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	59576302	34
T55	6519	2
T59	8964	1
T61	14347	1
T62	9281	3
T64	10709	1
T125	8938	2
T126	10509	2
T128	11657	1
T131	12263	2
T134	11708	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	293590803	34
T55	22483	2
T59	18677	1
T61	28695	1
T62	18941	3
T64	42835	1
T125	35755	2
T126	10723	2
T128	12144	1
T131	51097	2
T134	11947	2

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T57,T63,T64
1	0	Covered	T57,T63,T64
1	1	Covered	T126,T135,T136

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T57,T63,T64
1	0	Covered	T126,T135,T136
1	1	Covered	T57,T63,T64

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	59576302	31	0	0
SrcPulseCheck_M	141066997	31	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	59576302	31
T57	8718	1
T60	5824	2
T63	10896	3
T64	10709	1
T124	7339	2
T126	10509	2
T128	11657	1
T135	11708	3
T137	9909	1
T138	6062	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	141066997	31
T57	4359	1
T60	2912	2
T63	10461	3
T64	20562	1
T124	14678	2
T126	5147	2
T128	5828	1
T135	5854	3
T137	21619	1
T138	6766	2

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T57,T63,T59
1	0	Covered	T57,T63,T59
1	1	Covered	T126,T133

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T57,T63,T59
1	0	Covered	T126,T133
1	1	Covered	T57,T63,T59

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	59576302	29	0	0
SrcPulseCheck_M	141066997	29	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	59576302	29
T57	8718	2
T59	8964	1
T60	5824	1
T62	9281	1
T63	10896	2
T64	10709	1
T124	7339	3
T126	10509	2
T128	11657	1
T131	12263	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	141066997	29
T57	4359	2
T59	8964	1
T60	2912	1
T62	9091	1
T63	10461	2
T64	20562	1
T124	14678	3
T126	5147	2
T128	5828	1
T131	24527	1

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5

Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	274512764	45393	0	0
SrcPulseCheck_M	12484027	45274	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	274512764	45393
T1	65582	30
T2	123123	53
T3	0	49
T4	27212	0
T5	115671	104
T8	0	75
T15	1518	0
T16	3359	0
T17	2236	0
T18	7322	0
T19	174693	202
T20	1635	0
T21	0	62
T24	0	188
T26	0	41
T27	0	185

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	12484027	45274
T1	147	30
T2	268	53
T3	0	49
T4	71	0
T5	1838	104
T8	0	75
T15	111	0
T16	245	0
T17	162	0
T18	534	0
T19	378	202
T20	119	0
T21	0	62
T24	0	188
T26	0	41
T27	0	185

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	136683880	44948	0	0
SrcPulseCheck_M	12484027	44838	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	136683880	44948
T1	32758	30
T2	61528	53
T3	0	49
T4	7568	0
T5	57729	104
T8	0	75
T15	747	0
T16	1647	0
T17	1158	0
T18	3607	0
T19	87280	202
T20	805	0
T21	0	62
T24	0	188
T26	0	41
T27	0	176

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	12484027	44838
T1	147	30
T2	268	53
T3	0	49
T4	71	0
T5	1838	104
T8	0	75
T15	111	0
T16	245	0
T17	162	0
T18	534	0
T19	378	202
T20	119	0
T21	0	62
T24	0	188
T26	0	41
T27	0	176

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	68341574	44478	0	0
SrcPulseCheck_M	12484027	44373	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	68341574	44478
T1	16379	30
T2	30764	53
T3	0	43
T4	3784	0
T5	28863	97
T8	0	75
T15	373	0
T16	823	0
T17	578	0
T18	1804	0
T19	43640	202
T20	403	0
T21	0	62
T24	0	188
T26	0	41
T27	0	164

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	12484027	44373
T1	147	30
T2	268	53
T3	0	43
T4	71	0
T5	1838	97
T8	0	75
T15	111	0
T16	245	0
T17	162	0
T18	534	0
T19	378	202
T20	119	0
T21	0	62
T24	0	188
T26	0	41
T27	0	164

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5

Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	290926322	53494	0	0
SrcPulseCheck_M	12498351	53494	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	290926322	53494
T1	68317	30
T2	128257	53
T3	0	43
T4	28346	0
T5	138494	131
T8	0	75
T15	1582	0
T16	3499	0
T17	2329	0
T18	7627	0
T19	205977	250
T20	1703	0
T21	0	62
T24	0	284
T26	0	77
T27	0	235

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	12498351	53494
T1	147	30
T2	268	53
T3	0	43
T4	71	0
T5	1874	131
T8	0	75
T15	111	0
T16	245	0
T17	162	0
T18	534	0
T19	426	250
T20	119	0
T21	0	62
T24	0	284
T26	0	77
T27	0	235

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T5
0	Covered	T6,T1,T5

Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	139788084	53080	0	0
SrcPulseCheck_M	12498939	53081	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	139788084	53080
T1	32793	30
T2	61564	53
T3	0	42
T4	13606	0
T5	63598	119
T8	0	75
T15	759	0
T16	1680	0
T17	1118	0
T18	3661	0
T19	101750	262
T20	817	0
T21	0	62
T24	0	320
T26	0	65
T27	0	189

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	12498939	53081
T1	147	30
T2	268	53
T3	0	42
T4	71	0
T5	1862	119
T8	0	75
T15	111	0
T16	245	0
T17	162	0
T18	534	0
T19	438	262
T20	119	0
T21	0	62
T24	0	320
T26	0	65
T27	0	189

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_io_meas_ctrl_en_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	91.67			100.00	100.00	u_io_meas_ctrl_shadowed_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb