Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T4,T11,T14
1	0	Covered	T1,T5,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T5
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T5
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T5
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T1,T5

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	595763020	725929	0	0
DstReqKnown_A	1837193194	1817957414	0	0
SrcAckBusyChk_A	595763020	151712	0	0
SrcBusyKnown_A	595763020	577038880	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595763020	725929	0	0
T1	649040	937	0	0
T2	1244130	1747	0	0
T3	0	387	0	0
T4	283460	978	0	0
T5	231180	572	0	0
T8	0	1537	0	0
T15	15510	0	0	0
T16	17490	0	0	0
T17	23290	0	0	0
T18	19060	0	0	0
T19	2207700	3224	0	0
T20	16350	0	0	0
T24	0	2053	0	0
T26	0	852	0	0
T27	0	680	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1837193194	1817957414	0	0
T1	431658	430958	0	0
T2	810472	809866	0	0
T4	161032	13690	0	0
T5	808710	806166	0	0
T6	45586	45070	0	0
T15	9958	9200	0	0
T16	22016	21048	0	0
T17	14838	13882	0	0
T18	48042	46864	0	0
T19	1226680	1225814	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595763020	151712	0	0
T1	649040	120	0	0
T2	1244130	220	0	0
T3	0	140	0	0
T4	283460	112	0	0
T5	231180	180	0	0
T8	0	300	0	0
T15	15510	0	0	0
T16	17490	0	0	0
T17	23290	0	0	0
T18	19060	0	0	0
T19	2207700	380	0	0
T20	16350	0	0	0
T24	0	400	0	0
T26	0	100	0	0
T27	0	260	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595763020	577038880	0	0
T1	649040	647840	0	0
T2	1244130	1243050	0	0
T4	283460	21670	0	0
T5	231180	230470	0	0
T6	11430	11280	0	0
T15	15510	14270	0	0
T16	17490	16640	0	0
T17	23290	21460	0	0
T18	19060	18530	0	0
T19	2207700	2206080	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T5
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T5
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T5
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	59576302	40210	0	0
DstReqKnown_A	277070554	273776370	0	0
SrcAckBusyChk_A	59576302	12281	0	0
SrcBusyKnown_A	59576302	57703888	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	40210	0	0
T1	64904	59	0	0
T2	124413	109	0	0
T3	0	34	0	0
T4	28346	42	0	0
T5	23118	47	0	0
T8	0	107	0	0
T15	1551	0	0	0
T16	1749	0	0	0
T17	2329	0	0	0
T18	1906	0	0	0
T19	220770	230	0	0
T20	1635	0	0	0
T24	0	142	0	0
T26	0	53	0	0
T27	0	68	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	277070554	273776370	0	0
T1	65582	65461	0	0
T2	123123	123015	0	0
T4	27212	2080	0	0
T5	115671	115237	0	0
T6	6862	6769	0	0
T15	1518	1397	0	0
T16	3359	3197	0	0
T17	2236	2060	0	0
T18	7322	7118	0	0
T19	174693	174531	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	12281	0	0
T1	64904	12	0	0
T2	124413	22	0	0
T3	0	14	0	0
T4	28346	8	0	0
T5	23118	18	0	0
T8	0	30	0	0
T15	1551	0	0	0
T16	1749	0	0	0
T17	2329	0	0	0
T18	1906	0	0	0
T19	220770	38	0	0
T20	1635	0	0	0
T24	0	40	0	0
T26	0	10	0	0
T27	0	26	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	57703888	0	0
T1	64904	64784	0	0
T2	124413	124305	0	0
T4	28346	2167	0	0
T5	23118	23047	0	0
T6	1143	1128	0	0
T15	1551	1427	0	0
T16	1749	1664	0	0
T17	2329	2146	0	0
T18	1906	1853	0	0
T19	220770	220608	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T5
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T5
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T5
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	59576302	54970	0	0
DstReqKnown_A	137912410	137088311	0	0
SrcAckBusyChk_A	59576302	12281	0	0
SrcBusyKnown_A	59576302	57703888	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	54970	0	0
T1	64904	96	0	0
T2	124413	174	0	0
T3	0	39	0	0
T4	28346	67	0	0
T5	23118	58	0	0
T8	0	154	0	0
T15	1551	0	0	0
T16	1749	0	0	0
T17	2329	0	0	0
T18	1906	0	0	0
T19	220770	327	0	0
T20	1635	0	0	0
T24	0	207	0	0
T26	0	82	0	0
T27	0	68	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137912410	137088311	0	0
T1	32758	32730	0	0
T2	61528	61507	0	0
T4	7568	1040	0	0
T5	57729	57619	0	0
T6	3568	3554	0	0
T15	747	699	0	0
T16	1647	1599	0	0
T17	1158	1137	0	0
T18	3607	3559	0	0
T19	87280	87266	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	12281	0	0
T1	64904	12	0	0
T2	124413	22	0	0
T3	0	14	0	0
T4	28346	8	0	0
T5	23118	18	0	0
T8	0	30	0	0
T15	1551	0	0	0
T16	1749	0	0	0
T17	2329	0	0	0
T18	1906	0	0	0
T19	220770	38	0	0
T20	1635	0	0	0
T24	0	40	0	0
T26	0	10	0	0
T27	0	26	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	57703888	0	0
T1	64904	64784	0	0
T2	124413	124305	0	0
T4	28346	2167	0	0
T5	23118	23047	0	0
T6	1143	1128	0	0
T15	1551	1427	0	0
T16	1749	1664	0	0
T17	2329	2146	0	0
T18	1906	1853	0	0
T19	220770	220608	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T5
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T5
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T5
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	59576302	84830	0	0
DstReqKnown_A	68955833	68543877	0	0
SrcAckBusyChk_A	59576302	12281	0	0
SrcBusyKnown_A	59576302	57703888	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	84830	0	0
T1	64904	166	0	0
T2	124413	306	0	0
T3	0	53	0	0
T4	28346	120	0	0
T5	23118	76	0	0
T8	0	245	0	0
T15	1551	0	0	0
T16	1749	0	0	0
T17	2329	0	0	0
T18	1906	0	0	0
T19	220770	546	0	0
T20	1635	0	0	0
T24	0	332	0	0
T26	0	149	0	0
T27	0	68	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68955833	68543877	0	0
T1	16379	16365	0	0
T2	30764	30754	0	0
T4	3784	520	0	0
T5	28863	28808	0	0
T6	1784	1777	0	0
T15	373	349	0	0
T16	823	799	0	0
T17	578	568	0	0
T18	1804	1780	0	0
T19	43640	43633	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	12281	0	0
T1	64904	12	0	0
T2	124413	22	0	0
T3	0	14	0	0
T4	28346	8	0	0
T5	23118	18	0	0
T8	0	30	0	0
T15	1551	0	0	0
T16	1749	0	0	0
T17	2329	0	0	0
T18	1906	0	0	0
T19	220770	38	0	0
T20	1635	0	0	0
T24	0	40	0	0
T26	0	10	0	0
T27	0	26	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	57703888	0	0
T1	64904	64784	0	0
T2	124413	124305	0	0
T4	28346	2167	0	0
T5	23118	23047	0	0
T6	1143	1128	0	0
T15	1551	1427	0	0
T16	1749	1664	0	0
T17	2329	2146	0	0
T18	1906	1853	0	0
T19	220770	220608	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T5
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T5
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T5
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	59576302	39582	0	0
DstReqKnown_A	293590803	290153059	0	0
SrcAckBusyChk_A	59576302	12281	0	0
SrcBusyKnown_A	59576302	57703888	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	39582	0	0
T1	64904	59	0	0
T2	124413	108	0	0
T3	0	34	0	0
T4	28346	48	0	0
T5	23118	47	0	0
T8	0	105	0	0
T15	1551	0	0	0
T16	1749	0	0	0
T17	2329	0	0	0
T18	1906	0	0	0
T19	220770	191	0	0
T20	1635	0	0	0
T24	0	140	0	0
T26	0	60	0	0
T27	0	68	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293590803	290153059	0	0
T1	68317	68191	0	0
T2	128257	128146	0	0
T4	28346	2167	0	0
T5	138494	138039	0	0
T6	7148	7051	0	0
T15	1582	1456	0	0
T16	3499	3330	0	0
T17	2329	2146	0	0
T18	7627	7415	0	0
T19	205977	205808	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	12281	0	0
T1	64904	12	0	0
T2	124413	22	0	0
T3	0	14	0	0
T4	28346	8	0	0
T5	23118	18	0	0
T8	0	30	0	0
T15	1551	0	0	0
T16	1749	0	0	0
T17	2329	0	0	0
T18	1906	0	0	0
T19	220770	38	0	0
T20	1635	0	0	0
T24	0	40	0	0
T26	0	10	0	0
T27	0	26	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	57703888	0	0
T1	64904	64784	0	0
T2	124413	124305	0	0
T4	28346	2167	0	0
T5	23118	23047	0	0
T6	1143	1128	0	0
T15	1551	1427	0	0
T16	1749	1664	0	0
T17	2329	2146	0	0
T18	1906	1853	0	0
T19	220770	220608	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T5
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T5
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T5
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	59576302	53097	0	0
DstReqKnown_A	141066997	139417090	0	0
SrcAckBusyChk_A	59576302	11848	0	0
SrcBusyKnown_A	59576302	57703888	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	53097	0	0
T1	64904	94	0	0
T2	124413	176	0	0
T3	0	37	0	0
T4	28346	37	0	0
T5	23118	58	0	0
T8	0	156	0	0
T15	1551	0	0	0
T16	1749	0	0	0
T17	2329	0	0	0
T18	1906	0	0	0
T19	220770	316	0	0
T20	1635	0	0	0
T24	0	210	0	0
T26	0	83	0	0
T27	0	68	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141066997	139417090	0	0
T1	32793	32732	0	0
T2	61564	61511	0	0
T4	13606	1038	0	0
T5	63598	63380	0	0
T6	3431	3384	0	0
T15	759	699	0	0
T16	1680	1599	0	0
T17	1118	1030	0	0
T18	3661	3560	0	0
T19	101750	101669	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	11848	0	0
T1	64904	12	0	0
T2	124413	22	0	0
T3	0	14	0	0
T4	28346	4	0	0
T5	23118	18	0	0
T8	0	30	0	0
T15	1551	0	0	0
T16	1749	0	0	0
T17	2329	0	0	0
T18	1906	0	0	0
T19	220770	38	0	0
T20	1635	0	0	0
T24	0	40	0	0
T26	0	10	0	0
T27	0	26	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	57703888	0	0
T1	64904	64784	0	0
T2	124413	124305	0	0
T4	28346	2167	0	0
T5	23118	23047	0	0
T6	1143	1128	0	0
T15	1551	1427	0	0
T16	1749	1664	0	0
T17	2329	2146	0	0
T18	1906	1853	0	0
T19	220770	220608	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T4,T11,T14
1	0	Covered	T1,T5,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T5
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T5
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T5
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	59576302	64660	0	0
DstReqKnown_A	277070554	273776370	0	0
SrcAckBusyChk_A	59576302	18218	0	0
SrcBusyKnown_A	59576302	57703888	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	64660	0	0
T1	64904	58	0	0
T2	124413	109	0	0
T3	0	33	0	0
T4	28346	84	0	0
T5	23118	47	0	0
T8	0	107	0	0
T15	1551	0	0	0
T16	1749	0	0	0
T17	2329	0	0	0
T18	1906	0	0	0
T19	220770	230	0	0
T20	1635	0	0	0
T24	0	143	0	0
T26	0	51	0	0
T27	0	68	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	277070554	273776370	0	0
T1	65582	65461	0	0
T2	123123	123015	0	0
T4	27212	2080	0	0
T5	115671	115237	0	0
T6	6862	6769	0	0
T15	1518	1397	0	0
T16	3359	3197	0	0
T17	2236	2060	0	0
T18	7322	7118	0	0
T19	174693	174531	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	18218	0	0
T1	64904	12	0	0
T2	124413	22	0	0
T3	0	14	0	0
T4	28346	16	0	0
T5	23118	18	0	0
T8	0	30	0	0
T15	1551	0	0	0
T16	1749	0	0	0
T17	2329	0	0	0
T18	1906	0	0	0
T19	220770	38	0	0
T20	1635	0	0	0
T24	0	40	0	0
T26	0	10	0	0
T27	0	26	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	57703888	0	0
T1	64904	64784	0	0
T2	124413	124305	0	0
T4	28346	2167	0	0
T5	23118	23047	0	0
T6	1143	1128	0	0
T15	1551	1427	0	0
T16	1749	1664	0	0
T17	2329	2146	0	0
T18	1906	1853	0	0
T19	220770	220608	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T4,T11,T14
1	0	Covered	T1,T5,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T5
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T5
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T5
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	59576302	90977	0	0
DstReqKnown_A	137912410	137088311	0	0
SrcAckBusyChk_A	59576302	18171	0	0
SrcBusyKnown_A	59576302	57703888	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	90977	0	0
T1	64904	94	0	0
T2	124413	175	0	0
T3	0	36	0	0
T4	28346	132	0	0
T5	23118	58	0	0
T8	0	154	0	0
T15	1551	0	0	0
T16	1749	0	0	0
T17	2329	0	0	0
T18	1906	0	0	0
T19	220770	327	0	0
T20	1635	0	0	0
T24	0	207	0	0
T26	0	82	0	0
T27	0	68	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137912410	137088311	0	0
T1	32758	32730	0	0
T2	61528	61507	0	0
T4	7568	1040	0	0
T5	57729	57619	0	0
T6	3568	3554	0	0
T15	747	699	0	0
T16	1647	1599	0	0
T17	1158	1137	0	0
T18	3607	3559	0	0
T19	87280	87266	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	18171	0	0
T1	64904	12	0	0
T2	124413	22	0	0
T3	0	14	0	0
T4	28346	16	0	0
T5	23118	18	0	0
T8	0	30	0	0
T15	1551	0	0	0
T16	1749	0	0	0
T17	2329	0	0	0
T18	1906	0	0	0
T19	220770	38	0	0
T20	1635	0	0	0
T24	0	40	0	0
T26	0	10	0	0
T27	0	26	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	57703888	0	0
T1	64904	64784	0	0
T2	124413	124305	0	0
T4	28346	2167	0	0
T5	23118	23047	0	0
T6	1143	1128	0	0
T15	1551	1427	0	0
T16	1749	1664	0	0
T17	2329	2146	0	0
T18	1906	1853	0	0
T19	220770	220608	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T4,T11,T14
1	0	Covered	T1,T5,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T5
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T5
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T5
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	59576302	145471	0	0
DstReqKnown_A	68955833	68543877	0	0
SrcAckBusyChk_A	59576302	18279	0	0
SrcBusyKnown_A	59576302	57703888	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	145471	0	0
T1	64904	162	0	0
T2	124413	310	0	0
T3	0	51	0	0
T4	28346	236	0	0
T5	23118	76	0	0
T8	0	249	0	0
T15	1551	0	0	0
T16	1749	0	0	0
T17	2329	0	0	0
T18	1906	0	0	0
T19	220770	555	0	0
T20	1635	0	0	0
T24	0	327	0	0
T26	0	149	0	0
T27	0	68	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68955833	68543877	0	0
T1	16379	16365	0	0
T2	30764	30754	0	0
T4	3784	520	0	0
T5	28863	28808	0	0
T6	1784	1777	0	0
T15	373	349	0	0
T16	823	799	0	0
T17	578	568	0	0
T18	1804	1780	0	0
T19	43640	43633	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	18279	0	0
T1	64904	12	0	0
T2	124413	22	0	0
T3	0	14	0	0
T4	28346	16	0	0
T5	23118	18	0	0
T8	0	30	0	0
T15	1551	0	0	0
T16	1749	0	0	0
T17	2329	0	0	0
T18	1906	0	0	0
T19	220770	38	0	0
T20	1635	0	0	0
T24	0	40	0	0
T26	0	10	0	0
T27	0	26	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	57703888	0	0
T1	64904	64784	0	0
T2	124413	124305	0	0
T4	28346	2167	0	0
T5	23118	23047	0	0
T6	1143	1128	0	0
T15	1551	1427	0	0
T16	1749	1664	0	0
T17	2329	2146	0	0
T18	1906	1853	0	0
T19	220770	220608	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T4,T11,T14
1	0	Covered	T1,T5,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T5
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T5
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T5
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	59576302	62814	0	0
DstReqKnown_A	293590803	290153059	0	0
SrcAckBusyChk_A	59576302	18181	0	0
SrcBusyKnown_A	59576302	57703888	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	62814	0	0
T1	64904	55	0	0
T2	124413	106	0	0
T3	0	33	0	0
T4	28346	96	0	0
T5	23118	47	0	0
T8	0	105	0	0
T15	1551	0	0	0
T16	1749	0	0	0
T17	2329	0	0	0
T18	1906	0	0	0
T19	220770	190	0	0
T20	1635	0	0	0
T24	0	140	0	0
T26	0	60	0	0
T27	0	68	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	293590803	290153059	0	0
T1	68317	68191	0	0
T2	128257	128146	0	0
T4	28346	2167	0	0
T5	138494	138039	0	0
T6	7148	7051	0	0
T15	1582	1456	0	0
T16	3499	3330	0	0
T17	2329	2146	0	0
T18	7627	7415	0	0
T19	205977	205808	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	18181	0	0
T1	64904	12	0	0
T2	124413	22	0	0
T3	0	14	0	0
T4	28346	16	0	0
T5	23118	18	0	0
T8	0	30	0	0
T15	1551	0	0	0
T16	1749	0	0	0
T17	2329	0	0	0
T18	1906	0	0	0
T19	220770	38	0	0
T20	1635	0	0	0
T24	0	40	0	0
T26	0	10	0	0
T27	0	26	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	57703888	0	0
T1	64904	64784	0	0
T2	124413	124305	0	0
T4	28346	2167	0	0
T5	23118	23047	0	0
T6	1143	1128	0	0
T15	1551	1427	0	0
T16	1749	1664	0	0
T17	2329	2146	0	0
T18	1906	1853	0	0
T19	220770	220608	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Covered	T4,T11,T14
1	0	Covered	T1,T5,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T5
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Unreachable
1	0	Covered	T1,T5,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T5
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T5
0	1	-	Covered	T1,T5,T2
0	0	1	Covered	T1,T5,T2
0	0	0	Covered	T6,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	59576302	89318	0	0
DstReqKnown_A	141066997	139417090	0	0
SrcAckBusyChk_A	59576302	17891	0	0
SrcBusyKnown_A	59576302	57703888	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	89318	0	0
T1	64904	94	0	0
T2	124413	174	0	0
T3	0	37	0	0
T4	28346	116	0	0
T5	23118	58	0	0
T8	0	155	0	0
T15	1551	0	0	0
T16	1749	0	0	0
T17	2329	0	0	0
T18	1906	0	0	0
T19	220770	312	0	0
T20	1635	0	0	0
T24	0	205	0	0
T26	0	83	0	0
T27	0	68	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141066997	139417090	0	0
T1	32793	32732	0	0
T2	61564	61511	0	0
T4	13606	1038	0	0
T5	63598	63380	0	0
T6	3431	3384	0	0
T15	759	699	0	0
T16	1680	1599	0	0
T17	1118	1030	0	0
T18	3661	3560	0	0
T19	101750	101669	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	17891	0	0
T1	64904	12	0	0
T2	124413	22	0	0
T3	0	14	0	0
T4	28346	12	0	0
T5	23118	18	0	0
T8	0	30	0	0
T15	1551	0	0	0
T16	1749	0	0	0
T17	2329	0	0	0
T18	1906	0	0	0
T19	220770	38	0	0
T20	1635	0	0	0
T24	0	40	0	0
T26	0	10	0	0
T27	0	26	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	57703888	0	0
T1	64904	64784	0	0
T2	124413	124305	0	0
T4	28346	2167	0	0
T5	23118	23047	0	0
T6	1143	1128	0	0
T15	1551	1427	0	0
T16	1749	1664	0	0
T17	2329	2146	0	0
T18	1906	1853	0	0
T19	220770	220608	0	0