Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	640592	0	0
SrcPulseCheck_M	2147483647	639504	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	640592
T1	1252002	1036
T2	0	414
T3	0	3790
T4	0	150
T5	139142	168
T11	0	382
T12	0	148
T13	0	3156
T14	0	276
T15	0	68
T18	6606	0
T26	19678	0
T27	12528	0
T28	28975	0
T29	17506	0
T30	20315	0
T34	0	154
T35	0	46
T36	0	20
T37	6665	0
T38	28235	0
T59	22086	1
T62	25786	4
T63	4542	2
T64	10670	1
T65	25986	2
T87	6510	0
T88	19672	4
T131	16156	1
T132	13882	2
T133	24982	0
T134	6700	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	639504
T1	353836	1036
T2	0	414
T3	0	3790
T4	0	150
T5	28321	168
T11	0	382
T12	0	148
T13	0	3156
T14	0	276
T15	0	68
T18	4107	0
T26	8123	0
T27	7222	0
T28	9387	0
T29	7249	0
T30	8566	0
T34	0	154
T35	0	46
T36	0	20
T37	3919	0
T38	9118	0
T59	40686	1
T62	11410	4
T63	42834	2
T64	4468	1
T65	23744	2
T87	2739	0
T88	7946	4
T131	25954	1
T132	71714	2
T133	10416	0
T134	12521	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	340405026	16295	0	0
SrcPulseCheck_M	92815926	16295	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	340405026	16295
T1	293640	52
T2	0	34
T3	0	166
T4	0	30
T5	35389	6
T11	0	30
T12	0	12
T18	1346	0
T26	4428	0
T27	2563	0
T28	7197	0
T29	4110	0
T30	4737	0
T34	0	6
T35	0	8
T36	0	4
T37	1445	0
T38	6807	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	92815926	16295
T1	97408	52
T2	0	34
T3	0	166
T4	0	30
T5	5144	6
T11	0	30
T12	0	12
T18	1507	0
T26	2214	0
T27	2563	0
T28	1873	0
T29	2012	0
T30	2418	0
T34	0	6
T35	0	8
T36	0	4
T37	1411	0
T38	1772	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	340405026	22346	0	0
SrcPulseCheck_M	92815926	22360	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	340405026	22346
T1	293640	52
T2	0	34
T3	0	166
T4	0	60
T5	35389	6
T11	0	30
T12	0	12
T18	1346	0
T26	4428	0
T27	2563	0
T28	7197	0
T29	4110	0
T30	4737	0
T34	0	6
T35	0	16
T36	0	8
T37	1445	0
T38	6807	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	92815926	22360
T1	97408	52
T2	0	34
T3	0	166
T4	0	60
T5	5144	6
T11	0	30
T12	0	12
T18	1507	0
T26	2214	0
T27	2563	0
T28	1873	0
T29	2012	0
T30	2418	0
T34	0	6
T35	0	16
T36	0	8
T37	1411	0
T38	1772	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	92815926	22335	0	0
SrcPulseCheck_M	340405026	22348	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	92815926	22335
T1	97408	52
T2	0	34
T3	0	166
T4	0	60
T5	5144	6
T11	0	30
T12	0	12
T18	1507	0
T26	2214	0
T27	2563	0
T28	1873	0
T29	2012	0
T30	2418	0
T34	0	6
T35	0	16
T36	0	8
T37	1411	0
T38	1772	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	340405026	22348
T1	293640	52
T2	0	34
T3	0	166
T4	0	60
T5	35389	6
T11	0	30
T12	0	12
T18	1346	0
T26	4428	0
T27	2563	0
T28	7197	0
T29	4110	0
T30	4737	0
T34	0	6
T35	0	16
T36	0	8
T37	1445	0
T38	6807	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	169488888	16295	0	0
SrcPulseCheck_M	92815926	16295	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	169488888	16295
T1	146592	52
T2	0	34
T3	0	166
T4	0	30
T5	17641	6
T11	0	30
T12	0	12
T18	661	0
T26	2407	0
T27	1352	0
T28	3545	0
T29	2029	0
T30	2350	0
T34	0	6
T35	0	8
T36	0	4
T37	669	0
T38	3590	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	92815926	16295
T1	97408	52
T2	0	34
T3	0	166
T4	0	30
T5	5144	6
T11	0	30
T12	0	12
T18	1507	0
T26	2214	0
T27	2563	0
T28	1873	0
T29	2012	0
T30	2418	0
T34	0	6
T35	0	8
T36	0	4
T37	1411	0
T38	1772	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	169488888	22323	0	0
SrcPulseCheck_M	92815926	22348	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	169488888	22323
T1	146592	52
T2	0	34
T3	0	166
T4	0	60
T5	17641	6
T11	0	30
T12	0	12
T18	661	0
T26	2407	0
T27	1352	0
T28	3545	0
T29	2029	0
T30	2350	0
T34	0	6
T35	0	16
T36	0	8
T37	669	0
T38	3590	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	92815926	22348
T1	97408	52
T2	0	34
T3	0	166
T4	0	60
T5	5144	6
T11	0	30
T12	0	12
T18	1507	0
T26	2214	0
T27	2563	0
T28	1873	0
T29	2012	0
T30	2418	0
T34	0	6
T35	0	16
T36	0	8
T37	1411	0
T38	1772	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	92815926	22311	0	0
SrcPulseCheck_M	169488888	22327	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	92815926	22311
T1	97408	52
T2	0	34
T3	0	166
T4	0	60
T5	5144	6
T11	0	30
T12	0	12
T18	1507	0
T26	2214	0
T27	2563	0
T28	1873	0
T29	2012	0
T30	2418	0
T34	0	6
T35	0	16
T36	0	8
T37	1411	0
T38	1772	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	169488888	22327
T1	146592	52
T2	0	34
T3	0	166
T4	0	60
T5	17641	6
T11	0	30
T12	0	12
T18	661	0
T26	2407	0
T27	1352	0
T28	3545	0
T29	2029	0
T30	2350	0
T34	0	6
T35	0	16
T36	0	8
T37	669	0
T38	3590	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	84743993	16295	0	0
SrcPulseCheck_M	92815926	16295	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	84743993	16295
T1	73294	52
T2	0	34
T3	0	166
T4	0	30
T5	8821	6
T11	0	30
T12	0	12
T18	330	0
T26	1203	0
T27	676	0
T28	1773	0
T29	1015	0
T30	1175	0
T34	0	6
T35	0	8
T36	0	4
T37	335	0
T38	1795	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	92815926	16295
T1	97408	52
T2	0	34
T3	0	166
T4	0	30
T5	5144	6
T11	0	30
T12	0	12
T18	1507	0
T26	2214	0
T27	2563	0
T28	1873	0
T29	2012	0
T30	2418	0
T34	0	6
T35	0	8
T36	0	4
T37	1411	0
T38	1772	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	84743993	22333	0	0
SrcPulseCheck_M	92815926	22364	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	84743993	22333
T1	73294	52
T2	0	34
T3	0	166
T4	0	60
T5	8821	6
T11	0	30
T12	0	12
T18	330	0
T26	1203	0
T27	676	0
T28	1773	0
T29	1015	0
T30	1175	0
T34	0	6
T35	0	16
T36	0	8
T37	335	0
T38	1795	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	92815926	22364
T1	97408	52
T2	0	34
T3	0	166
T4	0	60
T5	5144	6
T11	0	30
T12	0	12
T18	1507	0
T26	2214	0
T27	2563	0
T28	1873	0
T29	2012	0
T30	2418	0
T34	0	6
T35	0	16
T36	0	8
T37	1411	0
T38	1772	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	92815926	22328	0	0
SrcPulseCheck_M	84743993	22341	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	92815926	22328
T1	97408	52
T2	0	34
T3	0	166
T4	0	60
T5	5144	6
T11	0	30
T12	0	12
T18	1507	0
T26	2214	0
T27	2563	0
T28	1873	0
T29	2012	0
T30	2418	0
T34	0	6
T35	0	16
T36	0	8
T37	1411	0
T38	1772	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	84743993	22341
T1	73294	52
T2	0	34
T3	0	166
T4	0	60
T5	8821	6
T11	0	30
T12	0	12
T18	330	0
T26	1203	0
T27	676	0
T28	1773	0
T29	1015	0
T30	1175	0
T34	0	6
T35	0	16
T36	0	8
T37	335	0
T38	1795	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	362040064	16295	0	0
SrcPulseCheck_M	92815926	16295	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	362040064	16295
T1	347884	52
T2	0	34
T3	0	166
T4	0	30
T5	36865	6
T11	0	30
T12	0	12
T18	1440	0
T26	4612	0
T27	2670	0
T28	7497	0
T29	4282	0
T30	4935	0
T34	0	6
T35	0	8
T36	0	4
T37	1467	0
T38	7091	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	92815926	16295
T1	97408	52
T2	0	34
T3	0	166
T4	0	30
T5	5144	6
T11	0	30
T12	0	12
T18	1507	0
T26	2214	0
T27	2563	0
T28	1873	0
T29	2012	0
T30	2418	0
T34	0	6
T35	0	8
T36	0	4
T37	1411	0
T38	1772	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	362040064	22444	0	0
SrcPulseCheck_M	92815926	22459	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	362040064	22444
T1	347884	52
T2	0	34
T3	0	166
T4	0	60
T5	36865	6
T11	0	30
T12	0	12
T18	1440	0
T26	4612	0
T27	2670	0
T28	7497	0
T29	4282	0
T30	4935	0
T34	0	6
T35	0	16
T36	0	8
T37	1467	0
T38	7091	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	92815926	22459
T1	97408	52
T2	0	34
T3	0	166
T4	0	60
T5	5144	6
T11	0	30
T12	0	12
T18	1507	0
T26	2214	0
T27	2563	0
T28	1873	0
T29	2012	0
T30	2418	0
T34	0	6
T35	0	16
T36	0	8
T37	1411	0
T38	1772	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	92815926	22430	0	0
SrcPulseCheck_M	362040064	22448	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	92815926	22430
T1	97408	52
T2	0	34
T3	0	166
T4	0	60
T5	5144	6
T11	0	30
T12	0	12
T18	1507	0
T26	2214	0
T27	2563	0
T28	1873	0
T29	2012	0
T30	2418	0
T34	0	6
T35	0	16
T36	0	8
T37	1411	0
T38	1772	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	362040064	22448
T1	347884	52
T2	0	34
T3	0	166
T4	0	60
T5	36865	6
T11	0	30
T12	0	12
T18	1440	0
T26	4612	0
T27	2670	0
T28	7497	0
T29	4282	0
T30	4935	0
T34	0	6
T35	0	16
T36	0	8
T37	1467	0
T38	7091	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	173732217	15830	0	0
SrcPulseCheck_M	92815926	16295	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	173732217	15830
T1	158346	52
T2	0	34
T3	0	166
T4	0	15
T5	20575	6
T11	0	30
T12	0	12
T18	701	0
T26	2214	0
T27	1282	0
T28	3598	0
T29	2055	0
T30	2369	0
T34	0	6
T35	0	7
T36	0	2
T37	681	0
T38	3403	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	92815926	16295
T1	97408	52
T2	0	34
T3	0	166
T4	0	30
T5	5144	6
T11	0	30
T12	0	12
T18	1507	0
T26	2214	0
T27	2563	0
T28	1873	0
T29	2012	0
T30	2418	0
T34	0	6
T35	0	8
T36	0	4
T37	1411	0
T38	1772	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	173732217	21988	0	0
SrcPulseCheck_M	92815926	22282	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	173732217	21988
T1	158346	52
T2	0	34
T3	0	166
T4	0	45
T5	20575	6
T11	0	30
T12	0	12
T18	701	0
T26	2214	0
T27	1282	0
T28	3598	0
T29	2055	0
T30	2369	0
T34	0	6
T35	0	16
T36	0	6
T37	681	0
T38	3403	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	92815926	22282
T1	97408	52
T2	0	34
T3	0	166
T4	0	60
T5	5144	6
T11	0	30
T12	0	12
T18	1507	0
T26	2214	0
T27	2563	0
T28	1873	0
T29	2012	0
T30	2418	0
T34	0	6
T35	0	16
T36	0	8
T37	1411	0
T38	1772	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	92815926	21847	0	0
SrcPulseCheck_M	173732217	22030	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	92815926	21847
T1	97408	52
T2	0	34
T3	0	166
T4	0	45
T5	5144	6
T11	0	30
T12	0	12
T18	1507	0
T26	2214	0
T27	2563	0
T28	1873	0
T29	2012	0
T30	2418	0
T34	0	6
T35	0	16
T36	0	6
T37	1411	0
T38	1772	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	173732217	22030
T1	158346	52
T2	0	34
T3	0	166
T4	0	45
T5	20575	6
T11	0	30
T12	0	12
T18	701	0
T26	2214	0
T27	1282	0
T28	3598	0
T29	2055	0
T30	2369	0
T34	0	6
T35	0	16
T36	0	6
T37	681	0
T38	3403	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T58,T59,T62
1	0	Covered	T58,T59,T62
1	1	Covered	T58,T135

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T58,T59,T62
1	0	Covered	T58,T135
1	1	Covered	T58,T59,T62

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	92815926	30	0	0
SrcPulseCheck_M	340405026	30	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	92815926	30
T58	6615	3
T59	11043	2
T62	12893	2
T63	2271	1
T64	5335	1
T87	6510	1
T133	12491	1
T134	6700	1
T136	3513	1
T137	2962	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	340405026	30
T58	105848	3
T59	42405	2
T62	13028	2
T63	43608	1
T64	5335	1
T87	6442	1
T133	12360	1
T134	26799	1
T136	15329	1
T137	25846	2

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T58,T59,T62
1	0	Covered	T58,T59,T62
1	1	Covered	T135

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T58,T59,T62
1	0	Covered	T135
1	1	Covered	T58,T59,T62

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	92815926	25	0	0
SrcPulseCheck_M	340405026	25	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	92815926	25
T58	6615	1
T59	11043	1
T62	12893	2
T63	2271	1
T64	5335	1
T133	12491	2
T137	2962	2
T138	2018	1
T139	3651	1
T140	4095	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	340405026	25
T58	105848	1
T59	42405	1
T62	13028	2
T63	43608	1
T64	5335	1
T133	12360	2
T137	25846	2
T138	32302	1
T139	21906	1
T140	18724	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T59,T62,T63
1	0	Covered	T59,T62,T63
1	1	Covered	T62,T63,T132

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T59,T62,T63
1	0	Covered	T62,T63,T132
1	1	Covered	T59,T62,T63

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	92815926	39	0	0
SrcPulseCheck_M	169488888	39	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	92815926	39
T59	11043	1
T62	12893	4
T63	2271	2
T64	5335	1
T65	12993	2
T88	9836	4
T131	8078	1
T132	6941	2
T133	12491	3
T134	6700	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	169488888	39
T59	20343	1
T62	5705	4
T63	21417	2
T64	2234	1
T65	11872	2
T88	3973	4
T131	12977	1
T132	35857	2
T133	5208	3
T134	12521	2

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T59,T62,T63
1	0	Covered	T59,T62,T63
1	1	Covered	T62,T88,T134

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T59,T62,T63
1	0	Covered	T62,T88,T134
1	1	Covered	T59,T62,T63

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	92815926	36	0	0
SrcPulseCheck_M	169488888	36	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	92815926	36
T59	11043	1
T62	12893	4
T63	2271	1
T64	5335	1
T65	12993	2
T87	6510	1
T88	9836	3
T131	8078	2
T132	6941	1
T133	12491	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	169488888	36
T59	20343	1
T62	5705	4
T63	21417	1
T64	2234	1
T65	11872	2
T87	2739	1
T88	3973	3
T131	12977	2
T132	35857	1
T133	5208	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T58,T59,T60
1	0	Covered	T58,T59,T60
1	1	Covered	T60,T63,T141

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T58,T59,T60
1	0	Covered	T60,T63,T141
1	1	Covered	T58,T59,T60

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	92815926	34	0	0
SrcPulseCheck_M	84743993	34	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	92815926	34
T58	6615	1
T59	11043	2
T60	5260	2
T62	12893	1
T63	2271	2
T87	6510	2
T89	3130	1
T132	6941	1
T137	2962	1
T138	2018	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	84743993	34
T58	26041	1
T59	10173	2
T60	1851	2
T62	2854	1
T63	10709	2
T87	1369	2
T89	2941	1
T132	17928	1
T137	6305	1
T138	7871	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T58,T59,T60
1	0	Covered	T58,T59,T60
1	1	Covered	T59,T60,T141

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T58,T59,T60
1	0	Covered	T59,T60,T141
1	1	Covered	T58,T59,T60

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	92815926	33	0	0
SrcPulseCheck_M	84743993	33	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	92815926	33
T58	6615	1
T59	11043	3
T60	5260	2
T85	6295	1
T87	6510	2
T88	9836	1
T89	3130	1
T131	8078	1
T132	6941	2
T133	12491	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	84743993	33
T58	26041	1
T59	10173	3
T60	1851	2
T85	5921	1
T87	1369	2
T88	1987	1
T89	2941	1
T131	6487	1
T132	17928	2
T133	2599	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T58,T59,T60
1	0	Covered	T58,T59,T60
1	1	Covered	T136,T142,T139

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T58,T59,T60
1	0	Covered	T136,T142,T139
1	1	Covered	T58,T59,T60

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	92815926	35	0	0
SrcPulseCheck_M	362040064	35	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	92815926	35
T58	6615	1
T59	11043	1
T60	5260	1
T61	12101	1
T63	2271	1
T65	12993	1
T87	6510	1
T88	9836	1
T131	8078	1
T132	6941	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	362040064	35
T58	110263	1
T59	44174	1
T60	8624	1
T61	172887	1
T63	45427	1
T65	26517	1
T87	6711	1
T88	10036	1
T131	28850	1
T132	77136	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T58,T59,T62
1	0	Covered	T58,T59,T62
1	1	Covered	T136,T142,T139

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T58,T59,T62
1	0	Covered	T136,T142,T139
1	1	Covered	T58,T59,T62

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	92815926	25	0	0
SrcPulseCheck_M	362040064	25	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	92815926	25
T58	6615	1
T59	11043	1
T62	12893	1
T65	12993	1
T87	6510	1
T131	8078	1
T132	6941	2
T136	3513	2
T142	7637	2
T143	4394	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	362040064	25
T58	110263	1
T59	44174	1
T62	13572	1
T65	26517	1
T87	6711	1
T131	28850	1
T132	77136	2
T136	15968	2
T142	7956	2
T143	43948	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T58,T59,T61
1	0	Covered	T58,T59,T61
1	1	Covered	T88,T89,T137

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T58,T59,T61
1	0	Covered	T88,T89,T137
1	1	Covered	T58,T59,T61

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	92815926	36	0	0
SrcPulseCheck_M	173732217	36	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	92815926	36
T58	6615	1
T59	11043	1
T61	12101	1
T85	6295	1
T88	9836	2
T89	3130	2
T131	8078	2
T132	6941	1
T133	12491	1
T143	4394	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	173732217	36
T58	52926	1
T59	21203	1
T61	82987	1
T85	12590	1
T88	4818	2
T89	6261	2
T131	13848	2
T132	37025	1
T133	6181	1
T143	21095	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T58,T60,T61
1	0	Covered	T58,T60,T61
1	1	Covered	T131,T137,T139

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T58,T60,T61
1	0	Covered	T131,T137,T139
1	1	Covered	T58,T60,T61

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	92815926	33	0	0
SrcPulseCheck_M	173732217	33	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	92815926	33
T58	6615	1
T60	5260	1
T61	12101	1
T62	12893	1
T65	12993	1
T85	6295	1
T88	9836	1
T89	3130	1
T131	8078	2
T132	6941	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	173732217	33
T58	52926	1
T60	4139	1
T61	82987	1
T62	6514	1
T65	12728	1
T85	12590	1
T88	4818	1
T89	6261	1
T131	13848	2
T132	37025	1

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	337456022	63673	0	0
SrcPulseCheck_M	12082156	62934	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	337456022	63673
T1	293640	199
T2	0	78
T3	0	793
T5	35389	39
T11	0	73
T12	0	28
T13	0	744
T14	0	69
T18	1346	0
T26	4428	0
T27	2563	0
T28	7197	0
T29	4110	0
T30	4737	0
T34	0	34
T35	0	2
T37	1445	0
T38	6807	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	12082156	62934
T1	3086	199
T2	0	78
T3	0	793
T5	98	39
T11	0	73
T12	0	28
T13	0	744
T14	0	69
T18	108	0
T26	322	0
T27	186	0
T28	524	0
T29	299	0
T30	345	0
T34	0	34
T35	0	2
T37	107	0
T38	496	0

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	168061331	62827	0	0
SrcPulseCheck_M	12082156	62099	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	168061331	62827
T1	146592	199
T2	0	78
T3	0	793
T5	17641	39
T11	0	73
T12	0	28
T13	0	744
T14	0	69
T18	661	0
T26	2407	0
T27	1352	0
T28	3545	0
T29	2029	0
T30	2350	0
T34	0	34
T35	0	2
T37	669	0
T38	3590	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	12082156	62099
T1	3086	199
T2	0	78
T3	0	793
T5	98	39
T11	0	73
T12	0	28
T13	0	744
T14	0	69
T18	108	0
T26	322	0
T27	186	0
T28	524	0
T29	299	0
T30	345	0
T34	0	34
T35	0	2
T37	107	0
T38	496	0

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	84030210	61597	0	0
SrcPulseCheck_M	12082156	60889	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	84030210	61597
T1	73294	199
T2	0	78
T3	0	793
T5	8821	36
T11	0	73
T12	0	28
T13	0	744
T14	0	69
T18	330	0
T26	1203	0
T27	676	0
T28	1773	0
T29	1015	0
T30	1175	0
T34	0	34
T35	0	2
T37	335	0
T38	1795	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	12082156	60889
T1	3086	199
T2	0	78
T3	0	793
T5	98	36
T11	0	73
T12	0	28
T13	0	744
T14	0	69
T18	108	0
T26	322	0
T27	186	0
T28	524	0
T29	299	0
T30	345	0
T34	0	34
T35	0	2
T37	107	0
T38	496	0

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	358968050	75068	0	0
SrcPulseCheck_M	12286548	75068	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	358968050	75068
T1	347884	283
T2	0	78
T3	0	913
T5	36865	36
T11	0	73
T12	0	28
T13	0	924
T14	0	69
T15	0	68
T18	1440	0
T26	4612	0
T27	2670	0
T28	7497	0
T29	4282	0
T30	4935	0
T34	0	34
T37	1467	0
T38	7091	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	12286548	75068
T1	3170	283
T2	0	78
T3	0	913
T5	98	36
T11	0	73
T12	0	28
T13	0	924
T14	0	69
T15	0	68
T18	108	0
T26	322	0
T27	186	0
T28	524	0
T29	299	0
T30	345	0
T34	0	34
T37	107	0
T38	496	0

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	172257682	73406	0	0
SrcPulseCheck_M	12286311	73406	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	172257682	73406
T1	158346	247
T2	0	78
T3	0	961
T5	20575	47
T11	0	73
T12	0	28
T13	0	852
T14	0	69
T15	0	68
T18	701	0
T26	2214	0
T27	1282	0
T28	3598	0
T29	2055	0
T30	2369	0
T34	0	34
T37	681	0
T38	3403	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	12286311	73406
T1	3134	247
T2	0	78
T3	0	961
T5	110	47
T11	0	73
T12	0	28
T13	0	852
T14	0	69
T15	0	68
T18	108	0
T26	322	0
T27	186	0
T28	524	0
T29	299	0
T30	345	0
T34	0	34
T37	107	0
T38	496	0

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_io_meas_ctrl_en_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	91.67			100.00	100.00	u_io_meas_ctrl_shadowed_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb