Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T4,T35,T36
1	0	Covered	T5,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	928159260	954140	0	0
DstReqKnown_A	2147483647	2147483647	0	0
SrcAckBusyChk_A	928159260	192265	0	0
SrcBusyKnown_A	928159260	906522150	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	928159260	954140	0	0
T1	974080	1870	0	0
T2	0	2853	0	0
T3	0	13481	0	0
T4	0	3505	0	0
T5	51440	142	0	0
T11	0	1060	0	0
T12	0	960	0	0
T18	15070	0	0	0
T26	22140	0	0	0
T27	25630	0	0	0
T28	18730	0	0	0
T29	20120	0	0	0
T30	24180	0	0	0
T34	0	531	0	0
T35	0	322	0	0
T36	0	453	0	0
T37	14110	0	0	0
T38	17720	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T5	238582	237766	0	0
T6	20880	19908	0	0
T7	7720	6524	0	0
T8	8608	7794	0	0
T25	25662	24812	0	0
T26	29728	28628	0	0
T27	17086	16368	0	0
T28	47220	45774	0	0
T29	26982	26446	0	0
T30	31132	30212	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	928159260	192265	0	0
T1	974080	520	0	0
T2	0	340	0	0
T3	0	1660	0	0
T4	0	420	0	0
T5	51440	60	0	0
T11	0	300	0	0
T12	0	120	0	0
T18	15070	0	0	0
T26	22140	0	0	0
T27	25630	0	0	0
T28	18730	0	0	0
T29	20120	0	0	0
T30	24180	0	0	0
T34	0	60	0	0
T35	0	118	0	0
T36	0	56	0	0
T37	14110	0	0	0
T38	17720	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	928159260	906522150	0	0
T5	51440	51260	0	0
T6	8320	7870	0	0
T7	11690	9700	0	0
T8	15270	13740	0	0
T25	19700	19020	0	0
T26	22140	21260	0	0
T27	25630	24420	0	0
T28	18730	18100	0	0
T29	20120	19660	0	0
T30	24180	23430	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T5,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	92815926	55377	0	0
DstReqKnown_A	340405026	336668551	0	0
SrcAckBusyChk_A	92815926	16295	0	0
SrcBusyKnown_A	92815926	90652215	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92815926	55377	0	0
T1	97408	135	0	0
T2	0	176	0	0
T3	0	847	0	0
T4	0	149	0	0
T5	5144	13	0	0
T11	0	76	0	0
T12	0	69	0	0
T18	1507	0	0	0
T26	2214	0	0	0
T27	2563	0	0	0
T28	1873	0	0	0
T29	2012	0	0	0
T30	2418	0	0	0
T34	0	32	0	0
T35	0	21	0	0
T36	0	18	0	0
T37	1411	0	0	0
T38	1772	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340405026	336668551	0	0
T5	35389	35241	0	0
T6	3199	3024	0	0
T7	1194	991	0	0
T8	1298	1150	0	0
T25	3860	3725	0	0
T26	4428	4252	0	0
T27	2563	2442	0	0
T28	7197	6953	0	0
T29	4110	4017	0	0
T30	4737	4589	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92815926	16295	0	0
T1	97408	52	0	0
T2	0	34	0	0
T3	0	166	0	0
T4	0	30	0	0
T5	5144	6	0	0
T11	0	30	0	0
T12	0	12	0	0
T18	1507	0	0	0
T26	2214	0	0	0
T27	2563	0	0	0
T28	1873	0	0	0
T29	2012	0	0	0
T30	2418	0	0	0
T34	0	6	0	0
T35	0	8	0	0
T36	0	4	0	0
T37	1411	0	0	0
T38	1772	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92815926	90652215	0	0
T5	5144	5126	0	0
T6	832	787	0	0
T7	1169	970	0	0
T8	1527	1374	0	0
T25	1970	1902	0	0
T26	2214	2126	0	0
T27	2563	2442	0	0
T28	1873	1810	0	0
T29	2012	1966	0	0
T30	2418	2343	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T5,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	92815926	78834	0	0
DstReqKnown_A	169488888	168570299	0	0
SrcAckBusyChk_A	92815926	16295	0	0
SrcBusyKnown_A	92815926	90652215	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92815926	78834	0	0
T1	97408	186	0	0
T2	0	283	0	0
T3	0	1347	0	0
T4	0	235	0	0
T5	5144	13	0	0
T11	0	111	0	0
T12	0	98	0	0
T18	1507	0	0	0
T26	2214	0	0	0
T27	2563	0	0	0
T28	1873	0	0	0
T29	2012	0	0	0
T30	2418	0	0	0
T34	0	54	0	0
T35	0	21	0	0
T36	0	28	0	0
T37	1411	0	0	0
T38	1772	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169488888	168570299	0	0
T5	17641	17620	0	0
T6	1539	1512	0	0
T7	551	496	0	0
T8	596	575	0	0
T25	2015	1960	0	0
T26	2407	2338	0	0
T27	1352	1318	0	0
T28	3545	3476	0	0
T29	2029	2008	0	0
T30	2350	2295	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92815926	16295	0	0
T1	97408	52	0	0
T2	0	34	0	0
T3	0	166	0	0
T4	0	30	0	0
T5	5144	6	0	0
T11	0	30	0	0
T12	0	12	0	0
T18	1507	0	0	0
T26	2214	0	0	0
T27	2563	0	0	0
T28	1873	0	0	0
T29	2012	0	0	0
T30	2418	0	0	0
T34	0	6	0	0
T35	0	8	0	0
T36	0	4	0	0
T37	1411	0	0	0
T38	1772	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92815926	90652215	0	0
T5	5144	5126	0	0
T6	832	787	0	0
T7	1169	970	0	0
T8	1527	1374	0	0
T25	1970	1902	0	0
T26	2214	2126	0	0
T27	2563	2442	0	0
T28	1873	1810	0	0
T29	2012	1966	0	0
T30	2418	2343	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T5,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	92815926	124330	0	0
DstReqKnown_A	84743993	84284802	0	0
SrcAckBusyChk_A	92815926	16295	0	0
SrcBusyKnown_A	92815926	90652215	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92815926	124330	0	0
T1	97408	277	0	0
T2	0	502	0	0
T3	0	2334	0	0
T4	0	414	0	0
T5	5144	19	0	0
T11	0	153	0	0
T12	0	170	0	0
T18	1507	0	0	0
T26	2214	0	0	0
T27	2563	0	0	0
T28	1873	0	0	0
T29	2012	0	0	0
T30	2418	0	0	0
T34	0	91	0	0
T35	0	27	0	0
T36	0	49	0	0
T37	1411	0	0	0
T38	1772	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84743993	84284802	0	0
T5	8821	8811	0	0
T6	770	756	0	0
T7	275	247	0	0
T8	298	288	0	0
T25	1006	978	0	0
T26	1203	1169	0	0
T27	676	659	0	0
T28	1773	1739	0	0
T29	1015	1005	0	0
T30	1175	1147	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92815926	16295	0	0
T1	97408	52	0	0
T2	0	34	0	0
T3	0	166	0	0
T4	0	30	0	0
T5	5144	6	0	0
T11	0	30	0	0
T12	0	12	0	0
T18	1507	0	0	0
T26	2214	0	0	0
T27	2563	0	0	0
T28	1873	0	0	0
T29	2012	0	0	0
T30	2418	0	0	0
T34	0	6	0	0
T35	0	8	0	0
T36	0	4	0	0
T37	1411	0	0	0
T38	1772	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92815926	90652215	0	0
T5	5144	5126	0	0
T6	832	787	0	0
T7	1169	970	0	0
T8	1527	1374	0	0
T25	1970	1902	0	0
T26	2214	2126	0	0
T27	2563	2442	0	0
T28	1873	1810	0	0
T29	2012	1966	0	0
T30	2418	2343	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T5,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	92815926	54916	0	0
DstReqKnown_A	362040064	358134493	0	0
SrcAckBusyChk_A	92815926	16295	0	0
SrcBusyKnown_A	92815926	90652215	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92815926	54916	0	0
T1	97408	133	0	0
T2	0	172	0	0
T3	0	828	0	0
T4	0	174	0	0
T5	5144	13	0	0
T11	0	74	0	0
T12	0	56	0	0
T18	1507	0	0	0
T26	2214	0	0	0
T27	2563	0	0	0
T28	1873	0	0	0
T29	2012	0	0	0
T30	2418	0	0	0
T34	0	32	0	0
T35	0	21	0	0
T36	0	18	0	0
T37	1411	0	0	0
T38	1772	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362040064	358134493	0	0
T5	36865	36710	0	0
T6	3333	3150	0	0
T7	1243	1032	0	0
T8	1419	1265	0	0
T25	4020	3880	0	0
T26	4612	4429	0	0
T27	2670	2544	0	0
T28	7497	7243	0	0
T29	4282	4185	0	0
T30	4935	4780	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92815926	16295	0	0
T1	97408	52	0	0
T2	0	34	0	0
T3	0	166	0	0
T4	0	30	0	0
T5	5144	6	0	0
T11	0	30	0	0
T12	0	12	0	0
T18	1507	0	0	0
T26	2214	0	0	0
T27	2563	0	0	0
T28	1873	0	0	0
T29	2012	0	0	0
T30	2418	0	0	0
T34	0	6	0	0
T35	0	8	0	0
T36	0	4	0	0
T37	1411	0	0	0
T38	1772	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92815926	90652215	0	0
T5	5144	5126	0	0
T6	832	787	0	0
T7	1169	970	0	0
T8	1527	1374	0	0
T25	1970	1902	0	0
T26	2214	2126	0	0
T27	2563	2442	0	0
T28	1873	1810	0	0
T29	2012	1966	0	0
T30	2418	2343	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T5,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	92815926	76541	0	0
DstReqKnown_A	173732217	171861458	0	0
SrcAckBusyChk_A	92815926	15797	0	0
SrcBusyKnown_A	92815926	90652215	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92815926	76541	0	0
T1	97408	188	0	0
T2	0	288	0	0
T3	0	1352	0	0
T4	0	134	0	0
T5	5144	13	0	0
T11	0	114	0	0
T12	0	88	0	0
T18	1507	0	0	0
T26	2214	0	0	0
T27	2563	0	0	0
T28	1873	0	0	0
T29	2012	0	0	0
T30	2418	0	0	0
T34	0	56	0	0
T35	0	18	0	0
T36	0	14	0	0
T37	1411	0	0	0
T38	1772	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173732217	171861458	0	0
T5	20575	20501	0	0
T6	1599	1512	0	0
T7	597	496	0	0
T8	693	619	0	0
T25	1930	1863	0	0
T26	2214	2126	0	0
T27	1282	1221	0	0
T28	3598	3476	0	0
T29	2055	2008	0	0
T30	2369	2295	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92815926	15797	0	0
T1	97408	52	0	0
T2	0	34	0	0
T3	0	166	0	0
T4	0	15	0	0
T5	5144	6	0	0
T11	0	30	0	0
T12	0	12	0	0
T18	1507	0	0	0
T26	2214	0	0	0
T27	2563	0	0	0
T28	1873	0	0	0
T29	2012	0	0	0
T30	2418	0	0	0
T34	0	6	0	0
T35	0	6	0	0
T36	0	2	0	0
T37	1411	0	0	0
T38	1772	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92815926	90652215	0	0
T5	5144	5126	0	0
T6	832	787	0	0
T7	1169	970	0	0
T8	1527	1374	0	0
T25	1970	1902	0	0
T26	2214	2126	0	0
T27	2563	2442	0	0
T28	1873	1810	0	0
T29	2012	1966	0	0
T30	2418	2343	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T4,T35,T36
1	0	Covered	T5,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	92815926	79272	0	0
DstReqKnown_A	340405026	336668551	0	0
SrcAckBusyChk_A	92815926	22337	0	0
SrcBusyKnown_A	92815926	90652215	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92815926	79272	0	0
T1	97408	137	0	0
T2	0	178	0	0
T3	0	849	0	0
T4	0	305	0	0
T5	5144	13	0	0
T11	0	79	0	0
T12	0	68	0	0
T18	1507	0	0	0
T26	2214	0	0	0
T27	2563	0	0	0
T28	1873	0	0	0
T29	2012	0	0	0
T30	2418	0	0	0
T34	0	32	0	0
T35	0	40	0	0
T36	0	42	0	0
T37	1411	0	0	0
T38	1772	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340405026	336668551	0	0
T5	35389	35241	0	0
T6	3199	3024	0	0
T7	1194	991	0	0
T8	1298	1150	0	0
T25	3860	3725	0	0
T26	4428	4252	0	0
T27	2563	2442	0	0
T28	7197	6953	0	0
T29	4110	4017	0	0
T30	4737	4589	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92815926	22337	0	0
T1	97408	52	0	0
T2	0	34	0	0
T3	0	166	0	0
T4	0	60	0	0
T5	5144	6	0	0
T11	0	30	0	0
T12	0	12	0	0
T18	1507	0	0	0
T26	2214	0	0	0
T27	2563	0	0	0
T28	1873	0	0	0
T29	2012	0	0	0
T30	2418	0	0	0
T34	0	6	0	0
T35	0	16	0	0
T36	0	8	0	0
T37	1411	0	0	0
T38	1772	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92815926	90652215	0	0
T5	5144	5126	0	0
T6	832	787	0	0
T7	1169	970	0	0
T8	1527	1374	0	0
T25	1970	1902	0	0
T26	2214	2126	0	0
T27	2563	2442	0	0
T28	1873	1810	0	0
T29	2012	1966	0	0
T30	2418	2343	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T4,T35,T36
1	0	Covered	T5,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	92815926	113526	0	0
DstReqKnown_A	169488888	168570299	0	0
SrcAckBusyChk_A	92815926	22316	0	0
SrcBusyKnown_A	92815926	90652215	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92815926	113526	0	0
T1	97408	195	0	0
T2	0	284	0	0
T3	0	1340	0	0
T4	0	486	0	0
T5	5144	13	0	0
T11	0	107	0	0
T12	0	99	0	0
T18	1507	0	0	0
T26	2214	0	0	0
T27	2563	0	0	0
T28	1873	0	0	0
T29	2012	0	0	0
T30	2418	0	0	0
T34	0	54	0	0
T35	0	40	0	0
T36	0	68	0	0
T37	1411	0	0	0
T38	1772	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169488888	168570299	0	0
T5	17641	17620	0	0
T6	1539	1512	0	0
T7	551	496	0	0
T8	596	575	0	0
T25	2015	1960	0	0
T26	2407	2338	0	0
T27	1352	1318	0	0
T28	3545	3476	0	0
T29	2029	2008	0	0
T30	2350	2295	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92815926	22316	0	0
T1	97408	52	0	0
T2	0	34	0	0
T3	0	166	0	0
T4	0	60	0	0
T5	5144	6	0	0
T11	0	30	0	0
T12	0	12	0	0
T18	1507	0	0	0
T26	2214	0	0	0
T27	2563	0	0	0
T28	1873	0	0	0
T29	2012	0	0	0
T30	2418	0	0	0
T34	0	6	0	0
T35	0	16	0	0
T36	0	8	0	0
T37	1411	0	0	0
T38	1772	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92815926	90652215	0	0
T5	5144	5126	0	0
T6	832	787	0	0
T7	1169	970	0	0
T8	1527	1374	0	0
T25	1970	1902	0	0
T26	2214	2126	0	0
T27	2563	2442	0	0
T28	1873	1810	0	0
T29	2012	1966	0	0
T30	2418	2343	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T4,T35,T36
1	0	Covered	T5,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	92815926	181487	0	0
DstReqKnown_A	84743993	84284802	0	0
SrcAckBusyChk_A	92815926	22331	0	0
SrcBusyKnown_A	92815926	90652215	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92815926	181487	0	0
T1	97408	286	0	0
T2	0	512	0	0
T3	0	2402	0	0
T4	0	852	0	0
T5	5144	19	0	0
T11	0	159	0	0
T12	0	165	0	0
T18	1507	0	0	0
T26	2214	0	0	0
T27	2563	0	0	0
T28	1873	0	0	0
T29	2012	0	0	0
T30	2418	0	0	0
T34	0	93	0	0
T35	0	54	0	0
T36	0	123	0	0
T37	1411	0	0	0
T38	1772	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84743993	84284802	0	0
T5	8821	8811	0	0
T6	770	756	0	0
T7	275	247	0	0
T8	298	288	0	0
T25	1006	978	0	0
T26	1203	1169	0	0
T27	676	659	0	0
T28	1773	1739	0	0
T29	1015	1005	0	0
T30	1175	1147	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92815926	22331	0	0
T1	97408	52	0	0
T2	0	34	0	0
T3	0	166	0	0
T4	0	60	0	0
T5	5144	6	0	0
T11	0	30	0	0
T12	0	12	0	0
T18	1507	0	0	0
T26	2214	0	0	0
T27	2563	0	0	0
T28	1873	0	0	0
T29	2012	0	0	0
T30	2418	0	0	0
T34	0	6	0	0
T35	0	16	0	0
T36	0	8	0	0
T37	1411	0	0	0
T38	1772	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92815926	90652215	0	0
T5	5144	5126	0	0
T6	832	787	0	0
T7	1169	970	0	0
T8	1527	1374	0	0
T25	1970	1902	0	0
T26	2214	2126	0	0
T27	2563	2442	0	0
T28	1873	1810	0	0
T29	2012	1966	0	0
T30	2418	2343	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T4,T35,T36
1	0	Covered	T5,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	92815926	78432	0	0
DstReqKnown_A	362040064	358134493	0	0
SrcAckBusyChk_A	92815926	22434	0	0
SrcBusyKnown_A	92815926	90652215	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92815926	78432	0	0
T1	97408	137	0	0
T2	0	171	0	0
T3	0	829	0	0
T4	0	354	0	0
T5	5144	13	0	0
T11	0	78	0	0
T12	0	54	0	0
T18	1507	0	0	0
T26	2214	0	0	0
T27	2563	0	0	0
T28	1873	0	0	0
T29	2012	0	0	0
T30	2418	0	0	0
T34	0	32	0	0
T35	0	40	0	0
T36	0	41	0	0
T37	1411	0	0	0
T38	1772	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362040064	358134493	0	0
T5	36865	36710	0	0
T6	3333	3150	0	0
T7	1243	1032	0	0
T8	1419	1265	0	0
T25	4020	3880	0	0
T26	4612	4429	0	0
T27	2670	2544	0	0
T28	7497	7243	0	0
T29	4282	4185	0	0
T30	4935	4780	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92815926	22434	0	0
T1	97408	52	0	0
T2	0	34	0	0
T3	0	166	0	0
T4	0	60	0	0
T5	5144	6	0	0
T11	0	30	0	0
T12	0	12	0	0
T18	1507	0	0	0
T26	2214	0	0	0
T27	2563	0	0	0
T28	1873	0	0	0
T29	2012	0	0	0
T30	2418	0	0	0
T34	0	6	0	0
T35	0	16	0	0
T36	0	8	0	0
T37	1411	0	0	0
T38	1772	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92815926	90652215	0	0
T5	5144	5126	0	0
T6	832	787	0	0
T7	1169	970	0	0
T8	1527	1374	0	0
T25	1970	1902	0	0
T26	2214	2126	0	0
T27	2563	2442	0	0
T28	1873	1810	0	0
T29	2012	1966	0	0
T30	2418	2343	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T4,T35,T36
1	0	Covered	T5,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	92815926	111425	0	0
DstReqKnown_A	173732217	171861458	0	0
SrcAckBusyChk_A	92815926	21870	0	0
SrcBusyKnown_A	92815926	90652215	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92815926	111425	0	0
T1	97408	196	0	0
T2	0	287	0	0
T3	0	1353	0	0
T4	0	402	0	0
T5	5144	13	0	0
T11	0	109	0	0
T12	0	93	0	0
T18	1507	0	0	0
T26	2214	0	0	0
T27	2563	0	0	0
T28	1873	0	0	0
T29	2012	0	0	0
T30	2418	0	0	0
T34	0	55	0	0
T35	0	40	0	0
T36	0	52	0	0
T37	1411	0	0	0
T38	1772	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173732217	171861458	0	0
T5	20575	20501	0	0
T6	1599	1512	0	0
T7	597	496	0	0
T8	693	619	0	0
T25	1930	1863	0	0
T26	2214	2126	0	0
T27	1282	1221	0	0
T28	3598	3476	0	0
T29	2055	2008	0	0
T30	2369	2295	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92815926	21870	0	0
T1	97408	52	0	0
T2	0	34	0	0
T3	0	166	0	0
T4	0	45	0	0
T5	5144	6	0	0
T11	0	30	0	0
T12	0	12	0	0
T18	1507	0	0	0
T26	2214	0	0	0
T27	2563	0	0	0
T28	1873	0	0	0
T29	2012	0	0	0
T30	2418	0	0	0
T34	0	6	0	0
T35	0	16	0	0
T36	0	6	0	0
T37	1411	0	0	0
T38	1772	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92815926	90652215	0	0
T5	5144	5126	0	0
T6	832	787	0	0
T7	1169	970	0	0
T8	1527	1374	0	0
T25	1970	1902	0	0
T26	2214	2126	0	0
T27	2563	2442	0	0
T28	1873	1810	0	0
T29	2012	1966	0	0
T30	2418	2343	0	0