Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	292161	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1289233

1

T7

24

T10

20

T11

28

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	406893	1			T7	8		T10	19		T11	42
values[0x0]	543420	1			T7	27		T10	15		T11	21
values[0x1]	631081	1			T7	17		T10	24		T11	18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	176429	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1404965

1

T7

28

T10

24

T11

33

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5192	1			T10	1		T42	1		T5	5
valid_sources[0x01]	5784	1			T8	3		T5	4		T6	2
valid_sources[0x02]	7518	1			T8	4		T44	1		T24	1
valid_sources[0x03]	4852	1			T10	1		T8	3		T103	10
valid_sources[0x04]	6658	1			T28	5		T97	1		T5	1
valid_sources[0x05]	6092	1			T5	3		T6	4		T25	1
valid_sources[0x06]	6133	1			T10	2		T8	4		T5	8
valid_sources[0x07]	5884	1			T8	1		T46	1		T102	1
valid_sources[0x08]	6286	1			T11	1		T8	2		T5	2
valid_sources[0x09]	6698	1			T28	3		T8	1		T5	7
valid_sources[0x0a]	5843	1			T28	1		T103	4		T5	3
valid_sources[0x0b]	6545	1			T33	16		T5	7		T6	1
valid_sources[0x0c]	5930	1			T8	1		T50	3		T4	37
valid_sources[0x0d]	6539	1			T8	4		T42	1		T5	4
valid_sources[0x0e]	5987	1			T8	1		T5	4		T6	3
valid_sources[0x0f]	6364	1			T10	1		T8	3		T99	12
valid_sources[0x10]	6428	1			T5	4		T6	5		T24	1
valid_sources[0x11]	6498	1			T5	4		T6	2		T27	2
valid_sources[0x12]	5782	1			T10	1		T30	1		T5	2
valid_sources[0x13]	5539	1			T28	5		T29	3		T8	1
valid_sources[0x14]	8094	1			T8	3		T5	2		T6	3
valid_sources[0x15]	5874	1			T46	1		T102	1		T5	3
valid_sources[0x16]	6466	1			T8	3		T5	3		T24	2
valid_sources[0x17]	5705	1			T29	22		T101	6		T102	1
valid_sources[0x18]	5872	1			T43	1		T5	4		T6	1
valid_sources[0x19]	7117	1			T8	1		T102	1		T5	3
valid_sources[0x1a]	6595	1			T28	1		T30	1		T8	6
valid_sources[0x1b]	6420	1			T8	2		T5	7		T6	3
valid_sources[0x1c]	6417	1			T10	1		T8	2		T5	2
valid_sources[0x1d]	5566	1			T10	1		T11	2		T8	1
valid_sources[0x1e]	6242	1			T8	4		T5	3		T26	7
valid_sources[0x1f]	6508	1			T28	2		T8	2		T102	1
valid_sources[0x20]	6285	1			T8	4		T158	1		T46	2
valid_sources[0x21]	5819	1			T10	1		T8	2		T43	1
valid_sources[0x22]	5875	1			T10	1		T5	6		T6	2
valid_sources[0x23]	6359	1			T102	1		T6	1		T14	229
valid_sources[0x24]	5153	1			T8	3		T102	1		T5	5
valid_sources[0x25]	6672	1			T8	3		T42	1		T46	1
valid_sources[0x26]	5808	1			T28	1		T6	3		T141	2
valid_sources[0x27]	6092	1			T4	20		T5	4		T6	1
valid_sources[0x28]	6954	1			T8	3		T5	2		T6	6
valid_sources[0x29]	7725	1			T11	2		T5	4		T6	3
valid_sources[0x2a]	6194	1			T46	2		T5	4		T6	2
valid_sources[0x2b]	8365	1			T10	1		T8	2		T43	1
valid_sources[0x2c]	6621	1			T10	1		T28	1		T8	1
valid_sources[0x2d]	5931	1			T5	1		T6	4		T184	1
valid_sources[0x2e]	5124	1			T10	1		T8	3		T42	1
valid_sources[0x2f]	6114	1			T8	3		T5	1		T6	3
valid_sources[0x30]	7717	1			T10	2		T29	1		T102	1
valid_sources[0x31]	6539	1			T11	1		T8	1		T5	8
valid_sources[0x32]	5975	1			T28	1		T8	2		T42	1
valid_sources[0x33]	5308	1			T10	1		T8	1		T97	1
valid_sources[0x34]	7273	1			T5	3		T27	1		T141	2
valid_sources[0x35]	6406	1			T10	1		T8	1		T46	1
valid_sources[0x36]	6582	1			T11	1		T28	1		T4	14
valid_sources[0x37]	5502	1			T8	1		T158	1		T46	2
valid_sources[0x38]	6424	1			T5	3		T6	2		T14	142
valid_sources[0x39]	6871	1			T10	2		T11	1		T28	2
valid_sources[0x3a]	5806	1			T8	1		T5	4		T6	1
valid_sources[0x3b]	6230	1			T8	6		T5	1		T6	3
valid_sources[0x3c]	6384	1			T42	1		T5	3		T6	2
valid_sources[0x3d]	5932	1			T8	1		T99	1		T103	8
valid_sources[0x3e]	5530	1			T8	7		T5	6		T26	2
valid_sources[0x3f]	5984	1			T11	1		T8	1		T50	1
valid_sources[0x40]	6581	1			T10	1		T11	1		T8	3
valid_sources[0x41]	5803	1			T10	1		T42	1		T46	1
valid_sources[0x42]	6350	1			T5	5		T6	1		T24	2
valid_sources[0x43]	6102	1			T8	4		T5	4		T6	2
valid_sources[0x44]	6833	1			T11	3		T8	2		T5	3
valid_sources[0x45]	4968	1			T42	1		T46	3		T5	1
valid_sources[0x46]	6239	1			T5	3		T27	1		T184	1
valid_sources[0x47]	5800	1			T8	2		T158	1		T46	1
valid_sources[0x48]	5541	1			T102	2		T5	4		T6	4
valid_sources[0x49]	6496	1			T8	3		T5	2		T27	1
valid_sources[0x4a]	7237	1			T6	2		T184	1		T14	154
valid_sources[0x4b]	6191	1			T5	5		T6	3		T140	1
valid_sources[0x4c]	5891	1			T28	1		T8	1		T103	16
valid_sources[0x4d]	5751	1			T11	2		T158	1		T5	8
valid_sources[0x4e]	6609	1			T46	6		T97	4		T102	1
valid_sources[0x4f]	4825	1			T10	3		T8	1		T102	1
valid_sources[0x50]	5935	1			T5	3		T6	2		T21	1
valid_sources[0x51]	5743	1			T11	1		T8	4		T158	1
valid_sources[0x52]	5283	1			T97	1		T102	1		T5	5
valid_sources[0x53]	5875	1			T10	1		T8	4		T5	3
valid_sources[0x54]	5659	1			T101	1		T5	2		T6	2
valid_sources[0x55]	5679	1			T46	1		T102	2		T5	2
valid_sources[0x56]	6152	1			T8	2		T44	2		T5	3
valid_sources[0x57]	7314	1			T11	1		T28	1		T5	2
valid_sources[0x58]	6034	1			T8	1		T43	2		T4	13
valid_sources[0x59]	5530	1			T29	6		T8	2		T46	1
valid_sources[0x5a]	5968	1			T8	2		T50	3		T103	5
valid_sources[0x5b]	5887	1			T28	3		T8	6		T102	1
valid_sources[0x5c]	6606	1			T28	4		T8	1		T97	1
valid_sources[0x5d]	5106	1			T8	4		T5	3		T6	4
valid_sources[0x5e]	5719	1			T28	1		T46	4		T5	4
valid_sources[0x5f]	6004	1			T10	1		T29	1		T50	4
valid_sources[0x60]	6266	1			T10	2		T8	3		T5	2
valid_sources[0x61]	6277	1			T8	1		T99	1		T5	5
valid_sources[0x62]	6034	1			T11	2		T103	4		T5	3
valid_sources[0x63]	5655	1			T8	1		T46	1		T184	3
valid_sources[0x64]	5800	1			T29	10		T8	1		T46	1
valid_sources[0x65]	5624	1			T11	1		T8	2		T50	4
valid_sources[0x66]	6143	1			T8	4		T103	5		T5	7
valid_sources[0x67]	6329	1			T8	1		T42	1		T102	1
valid_sources[0x68]	5961	1			T5	6		T6	2		T185	1
valid_sources[0x69]	5596	1			T28	3		T8	1		T46	1
valid_sources[0x6a]	6387	1			T8	1		T31	3		T42	1
valid_sources[0x6b]	6672	1			T28	1		T42	1		T103	2
valid_sources[0x6c]	6663	1			T11	1		T8	2		T5	7
valid_sources[0x6d]	6032	1			T10	2		T28	3		T158	1
valid_sources[0x6e]	6238	1			T8	2		T5	3		T6	2
valid_sources[0x6f]	5863	1			T30	1		T5	8		T6	2
valid_sources[0x70]	6041	1			T8	2		T5	4		T6	3
valid_sources[0x71]	5943	1			T10	1		T46	1		T5	1
valid_sources[0x72]	5689	1			T5	11		T6	3		T24	2
valid_sources[0x73]	5645	1			T102	1		T5	3		T6	4
valid_sources[0x74]	6678	1			T28	3		T8	3		T158	1
valid_sources[0x75]	7724	1			T10	1		T11	2		T29	1
valid_sources[0x76]	5818	1			T29	27		T158	1		T102	1
valid_sources[0x77]	6784	1			T46	1		T5	3		T6	1
valid_sources[0x78]	5743	1			T8	6		T5	6		T27	1
valid_sources[0x79]	6381	1			T42	2		T5	3		T6	3
valid_sources[0x7a]	6461	1			T11	1		T28	1		T8	3
valid_sources[0x7b]	5129	1			T8	11		T46	3		T102	1
valid_sources[0x7c]	5607	1			T46	1		T102	1		T5	1
valid_sources[0x7d]	6141	1			T28	1		T102	1		T5	3
valid_sources[0x7e]	5923	1			T8	2		T46	1		T6	1
valid_sources[0x7f]	5747	1			T8	1		T103	3		T6	1
valid_sources[0x80]	6948	1			T11	1		T8	5		T46	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

332388

1

T7

4

T10

11

T11

19

values[0x0]

all_enables

biggest_size

491980

1

T7

12

T10

4

T11

6

values[0x1]

all_enables

biggest_size

464865

1

T7

8

T10

5

T11

3