Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T11,T30,T32
0	1	Covered	T30,T158,T101
1	0	Covered	T7,T10,T11

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T30,T32
1	0	Covered	T47,T48,T49
1	1	Covered	T7,T10,T11

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	508021827	7237	0	0
GateOpen_A	508021827	13354	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508021827	7237	0	0
T8	410736	0	0	0
T11	4689	4	0	0
T21	0	5	0	0
T22	0	4	0	0
T25	0	34	0	0
T28	6011	0	0	0
T29	6746	0	0	0
T30	4347	5	0	0
T31	16777	0	0	0
T32	14776	4	0	0
T33	5415	0	0	0
T42	3566	0	0	0
T46	0	4	0	0
T50	7881	0	0	0
T101	0	11	0	0
T158	0	14	0	0
T163	0	10	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508021827	13354	0	0
T7	43313	4	0	0
T8	410736	0	0	0
T10	11800	4	0	0
T11	4689	4	0	0
T28	6011	4	0	0
T29	6746	0	0	0
T30	4347	9	0	0
T31	16777	0	0	0
T32	14776	8	0	0
T33	5415	0	0	0
T46	0	4	0	0
T50	0	4	0	0
T99	0	4	0	0
T158	0	18	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T11,T30,T32
0	1	Covered	T30,T158,T101
1	0	Covered	T7,T10,T11

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T30,T32
1	0	Covered	T47,T48,T49
1	1	Covered	T7,T10,T11

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	55900434	1736	0	0
GateOpen_A	55900434	3264	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55900434	1736	0	0
T8	41471	0	0	0
T11	506	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T25	0	9	0	0
T28	697	0	0	0
T29	795	0	0	0
T30	470	2	0	0
T31	1965	0	0	0
T32	1626	1	0	0
T33	607	0	0	0
T42	390	0	0	0
T46	0	1	0	0
T50	872	0	0	0
T101	0	2	0	0
T158	0	3	0	0
T163	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55900434	3264	0	0
T7	4804	1	0	0
T8	41471	0	0	0
T10	1431	1	0	0
T11	506	1	0	0
T28	697	1	0	0
T29	795	0	0	0
T30	470	3	0	0
T31	1965	0	0	0
T32	1626	2	0	0
T33	607	0	0	0
T46	0	1	0	0
T50	0	1	0	0
T99	0	1	0	0
T158	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T11,T30,T32
0	1	Covered	T30,T158,T101
1	0	Covered	T7,T10,T11

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T30,T32
1	0	Covered	T47,T48,T49
1	1	Covered	T7,T10,T11

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	111801211	1863	0	0
GateOpen_A	111801211	3391	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111801211	1863	0	0
T8	82941	0	0	0
T11	1011	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T25	0	8	0	0
T28	1396	0	0	0
T29	1592	0	0	0
T30	940	1	0	0
T31	3931	0	0	0
T32	3252	1	0	0
T33	1215	0	0	0
T42	780	0	0	0
T46	0	1	0	0
T50	1744	0	0	0
T101	0	3	0	0
T158	0	4	0	0
T163	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111801211	3391	0	0
T7	9608	1	0	0
T8	82941	0	0	0
T10	2862	1	0	0
T11	1011	1	0	0
T28	1396	1	0	0
T29	1592	0	0	0
T30	940	2	0	0
T31	3931	0	0	0
T32	3252	2	0	0
T33	1215	0	0	0
T46	0	1	0	0
T50	0	1	0	0
T99	0	1	0	0
T158	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T11,T30,T32
0	1	Covered	T30,T158,T101
1	0	Covered	T7,T10,T11

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T30,T32
1	0	Covered	T47,T48,T49
1	1	Covered	T7,T10,T11

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	225074271	1818	0	0
GateOpen_A	225074271	3348	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225074271	1818	0	0
T8	165920	0	0	0
T11	2115	1	0	0
T21	0	2	0	0
T22	0	1	0	0
T25	0	9	0	0
T28	2612	0	0	0
T29	2906	0	0	0
T30	1958	1	0	0
T31	7254	0	0	0
T32	6598	1	0	0
T33	2395	0	0	0
T42	1598	0	0	0
T46	0	1	0	0
T50	3510	0	0	0
T101	0	3	0	0
T158	0	3	0	0
T163	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225074271	3348	0	0
T7	19267	1	0	0
T8	165920	0	0	0
T10	5005	1	0	0
T11	2115	1	0	0
T28	2612	1	0	0
T29	2906	0	0	0
T30	1958	2	0	0
T31	7254	0	0	0
T32	6598	2	0	0
T33	2395	0	0	0
T46	0	1	0	0
T50	0	1	0	0
T99	0	1	0	0
T158	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T11,T30,T32
0	1	Covered	T30,T158,T101
1	0	Covered	T7,T10,T11

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T30,T32
1	0	Covered	T47,T48,T49
1	1	Covered	T7,T10,T11

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	115245911	1820	0	0
GateOpen_A	115245911	3351	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115245911	1820	0	0
T8	120404	0	0	0
T11	1057	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T25	0	8	0	0
T28	1306	0	0	0
T29	1453	0	0	0
T30	979	1	0	0
T31	3627	0	0	0
T32	3300	1	0	0
T33	1198	0	0	0
T42	798	0	0	0
T46	0	1	0	0
T50	1755	0	0	0
T101	0	3	0	0
T158	0	4	0	0
T163	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115245911	3351	0	0
T7	9634	1	0	0
T8	120404	0	0	0
T10	2502	1	0	0
T11	1057	1	0	0
T28	1306	1	0	0
T29	1453	0	0	0
T30	979	2	0	0
T31	3627	0	0	0
T32	3300	2	0	0
T33	1198	0	0	0
T46	0	1	0	0
T50	0	1	0	0
T99	0	1	0	0
T158	0	5	0	0