Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	351405805	42860	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	351405805	42860	0	0
T1	1037965	284	0	0
T2	79795	72	0	0
T3	80435	32	0	0
T14	0	676	0	0
T15	0	205	0	0
T16	0	979	0	0
T17	0	183	0	0
T18	0	336	0	0
T19	0	78	0	0
T20	0	397	0	0
T21	7205	0	0	0
T22	9310	0	0	0
T23	15555	0	0	0
T24	6270	0	0	0
T25	4945	0	0	0
T26	8905	0	0	0
T27	10330	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	70281161	6333	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70281161	6333	0	0
T1	207593	37	0	0
T2	15959	14	0	0
T3	16087	6	0	0
T14	0	110	0	0
T15	0	28	0	0
T16	0	129	0	0
T17	0	26	0	0
T18	0	43	0	0
T19	0	11	0	0
T20	0	64	0	0
T21	1441	0	0	0
T22	1862	0	0	0
T23	3111	0	0	0
T24	1254	0	0	0
T25	989	0	0	0
T26	1781	0	0	0
T27	2066	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	70281161	6172	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70281161	6172	0	0
T1	207593	36	0	0
T2	15959	14	0	0
T3	16087	6	0	0
T14	0	109	0	0
T15	0	27	0	0
T16	0	125	0	0
T17	0	25	0	0
T18	0	49	0	0
T19	0	12	0	0
T20	0	63	0	0
T21	1441	0	0	0
T22	1862	0	0	0
T23	3111	0	0	0
T24	1254	0	0	0
T25	989	0	0	0
T26	1781	0	0	0
T27	2066	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	70281161	8635	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70281161	8635	0	0
T1	207593	59	0	0
T2	15959	14	0	0
T3	16087	6	0	0
T14	0	136	0	0
T15	0	40	0	0
T16	0	200	0	0
T17	0	36	0	0
T18	0	68	0	0
T19	0	15	0	0
T20	0	81	0	0
T21	1441	0	0	0
T22	1862	0	0	0
T23	3111	0	0	0
T24	1254	0	0	0
T25	989	0	0	0
T26	1781	0	0	0
T27	2066	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	70281161	8660	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70281161	8660	0	0
T1	207593	59	0	0
T2	15959	14	0	0
T3	16087	6	0	0
T14	0	136	0	0
T15	0	41	0	0
T16	0	199	0	0
T17	0	37	0	0
T18	0	68	0	0
T19	0	15	0	0
T20	0	81	0	0
T21	1441	0	0	0
T22	1862	0	0	0
T23	3111	0	0	0
T24	1254	0	0	0
T25	989	0	0	0
T26	1781	0	0	0
T27	2066	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	70281161	13060	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70281161	13060	0	0
T1	207593	93	0	0
T2	15959	16	0	0
T3	16087	8	0	0
T14	0	185	0	0
T15	0	69	0	0
T16	0	326	0	0
T17	0	59	0	0
T18	0	108	0	0
T19	0	25	0	0
T20	0	108	0	0
T21	1441	0	0	0
T22	1862	0	0	0
T23	3111	0	0	0
T24	1254	0	0	0
T25	989	0	0	0
T26	1781	0	0	0
T27	2066	0	0	0