Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Unreachable
1	0	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	70281161	68034347	0	0
AllClkBypReqTrue_A	70281161	74928	0	0
IoClkBypReqFalse_A	70281161	67982101	0	2316
IoClkBypReqTrue_A	70281161	123030	0	0
LcClkBypAckFalse_A	70281161	68040756	0	0
LcClkBypAckTrue_A	70281161	68519	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70281161	68034347	0	0
T7	19670	19489	0	0
T8	27592	27581	0	0
T10	2398	2011	0	0
T11	2202	2075	0	0
T28	2720	2250	0	0
T29	3025	2421	0	0
T30	1080	1013	0	0
T31	1812	1561	0	0
T32	1649	1618	0	0
T33	1321	1207	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70281161	74928	0	0
T8	27592	0	0	0
T10	2398	355	0	0
T11	2202	0	0	0
T28	2720	271	0	0
T29	3025	349	0	0
T30	1080	0	0	0
T31	1812	200	0	0
T32	1649	0	0	0
T33	1321	39	0	0
T42	1663	0	0	0
T50	0	89	0	0
T97	0	40	0	0
T99	0	211	0	0
T102	0	438	0	0
T139	0	12	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70281161	67982101	0	2316
T7	19670	19487	0	3
T8	27592	27579	0	3
T10	2398	1914	0	3
T11	2202	2073	0	3
T28	2720	2210	0	3
T29	3025	2257	0	3
T30	1080	1011	0	3
T31	1812	1642	0	3
T32	1649	1616	0	3
T33	1321	1077	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70281161	123030	0	0
T8	27592	0	0	0
T10	2398	450	0	0
T11	2202	0	0	0
T28	2720	309	0	0
T29	3025	511	0	0
T30	1080	0	0	0
T31	1812	117	0	0
T32	1649	0	0	0
T33	1321	167	0	0
T42	1663	0	0	0
T50	0	64	0	0
T97	0	63	0	0
T102	0	624	0	0
T139	0	34	0	0
T140	0	304	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70281161	68040756	0	0
T7	19670	19489	0	0
T8	27592	27581	0	0
T10	2398	2067	0	0
T11	2202	2075	0	0
T28	2720	2370	0	0
T29	3025	2520	0	0
T30	1080	1013	0	0
T31	1812	1649	0	0
T32	1649	1618	0	0
T33	1321	1210	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70281161	68519	0	0
T8	27592	0	0	0
T10	2398	299	0	0
T11	2202	0	0	0
T14	0	997	0	0
T28	2720	151	0	0
T29	3025	250	0	0
T30	1080	0	0	0
T31	1812	112	0	0
T32	1649	0	0	0
T33	1321	36	0	0
T42	1663	0	0	0
T97	0	5	0	0
T102	0	457	0	0
T139	0	30	0	0
T140	0	188	0	0