Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	960064880	8205	0	0
TransStop_A	960064880	4459	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	960064880	8205	0	0
T8	955348	0	0	0
T11	8812	4	0	0
T22	0	4	0	0
T23	0	42	0	0
T26	0	4	0	0
T27	0	4	0	0
T28	10884	0	0	0
T29	12104	0	0	0
T30	8160	0	0	0
T31	30224	0	0	0
T32	27492	4	0	0
T33	9980	0	0	0
T42	6656	0	0	0
T46	0	4	0	0
T50	14624	0	0	0
T98	0	35	0	0
T100	0	33	0	0
T103	0	26	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	960064880	4459	0	0
T8	955348	0	0	0
T11	8812	4	0	0
T22	0	4	0	0
T23	0	15	0	0
T26	0	4	0	0
T27	0	4	0	0
T28	10884	0	0	0
T29	12104	0	0	0
T30	8160	0	0	0
T31	30224	0	0	0
T32	27492	4	0	0
T33	9980	0	0	0
T42	6656	0	0	0
T46	0	4	0	0
T50	14624	0	0	0
T98	0	17	0	0
T100	0	16	0	0
T103	0	12	0	0
T141	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	240016220	2044	0	0
TransStop_A	240016220	1101	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240016220	2044	0	0
T8	238837	0	0	0
T11	2203	1	0	0
T22	0	1	0	0
T23	0	11	0	0
T26	0	1	0	0
T27	0	1	0	0
T28	2721	0	0	0
T29	3026	0	0	0
T30	2040	0	0	0
T31	7556	0	0	0
T32	6873	1	0	0
T33	2495	0	0	0
T42	1664	0	0	0
T46	0	1	0	0
T50	3656	0	0	0
T98	0	5	0	0
T100	0	7	0	0
T103	0	9	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240016220	1101	0	0
T8	238837	0	0	0
T11	2203	1	0	0
T22	0	1	0	0
T23	0	2	0	0
T26	0	1	0	0
T27	0	1	0	0
T28	2721	0	0	0
T29	3026	0	0	0
T30	2040	0	0	0
T31	7556	0	0	0
T32	6873	1	0	0
T33	2495	0	0	0
T42	1664	0	0	0
T46	0	1	0	0
T50	3656	0	0	0
T98	0	3	0	0
T100	0	3	0	0
T103	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	240016220	2118	0	0
TransStop_A	240016220	1145	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240016220	2118	0	0
T8	238837	0	0	0
T11	2203	1	0	0
T22	0	1	0	0
T23	0	9	0	0
T26	0	1	0	0
T27	0	1	0	0
T28	2721	0	0	0
T29	3026	0	0	0
T30	2040	0	0	0
T31	7556	0	0	0
T32	6873	1	0	0
T33	2495	0	0	0
T42	1664	0	0	0
T46	0	1	0	0
T50	3656	0	0	0
T98	0	9	0	0
T100	0	5	0	0
T103	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240016220	1145	0	0
T8	238837	0	0	0
T11	2203	1	0	0
T22	0	1	0	0
T23	0	2	0	0
T26	0	1	0	0
T27	0	1	0	0
T28	2721	0	0	0
T29	3026	0	0	0
T30	2040	0	0	0
T31	7556	0	0	0
T32	6873	1	0	0
T33	2495	0	0	0
T42	1664	0	0	0
T46	0	1	0	0
T50	3656	0	0	0
T98	0	3	0	0
T100	0	2	0	0
T103	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	240016220	2021	0	0
TransStop_A	240016220	1103	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240016220	2021	0	0
T8	238837	0	0	0
T11	2203	1	0	0
T22	0	1	0	0
T23	0	10	0	0
T26	0	1	0	0
T27	0	1	0	0
T28	2721	0	0	0
T29	3026	0	0	0
T30	2040	0	0	0
T31	7556	0	0	0
T32	6873	1	0	0
T33	2495	0	0	0
T42	1664	0	0	0
T46	0	1	0	0
T50	3656	0	0	0
T98	0	12	0	0
T100	0	10	0	0
T103	0	8	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240016220	1103	0	0
T8	238837	0	0	0
T11	2203	1	0	0
T22	0	1	0	0
T23	0	6	0	0
T26	0	1	0	0
T27	0	1	0	0
T28	2721	0	0	0
T29	3026	0	0	0
T30	2040	0	0	0
T31	7556	0	0	0
T32	6873	1	0	0
T33	2495	0	0	0
T42	1664	0	0	0
T46	0	1	0	0
T50	3656	0	0	0
T98	0	5	0	0
T100	0	5	0	0
T103	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	240016220	2022	0	0
TransStop_A	240016220	1110	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240016220	2022	0	0
T8	238837	0	0	0
T11	2203	1	0	0
T22	0	1	0	0
T23	0	12	0	0
T26	0	1	0	0
T27	0	1	0	0
T28	2721	0	0	0
T29	3026	0	0	0
T30	2040	0	0	0
T31	7556	0	0	0
T32	6873	1	0	0
T33	2495	0	0	0
T42	1664	0	0	0
T46	0	1	0	0
T50	3656	0	0	0
T98	0	9	0	0
T100	0	11	0	0
T103	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240016220	1110	0	0
T8	238837	0	0	0
T11	2203	1	0	0
T22	0	1	0	0
T23	0	5	0	0
T26	0	1	0	0
T27	0	1	0	0
T28	2721	0	0	0
T29	3026	0	0	0
T30	2040	0	0	0
T31	7556	0	0	0
T32	6873	1	0	0
T33	2495	0	0	0
T42	1664	0	0	0
T46	0	1	0	0
T50	3656	0	0	0
T98	0	6	0	0
T100	0	6	0	0
T141	0	1	0	0