Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	70281161	10009526	0	56

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70281161	10009526	0	56
T1	0	36594	0	1
T2	0	3114	0	1
T3	0	2017	0	1
T7	19670	1018	0	1
T8	27592	0	0	0
T10	2398	0	0	0
T11	2202	0	0	0
T14	0	44977	0	0
T15	0	23708	0	1
T16	0	121942	0	1
T17	0	18690	0	1
T18	0	36733	0	0
T19	0	0	0	1
T28	2720	0	0	0
T29	3025	0	0	0
T30	1080	0	0	0
T31	1812	0	0	0
T32	1649	0	0	0
T33	1321	0	0	0
T34	0	0	0	1
T38	0	980	0	1