Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	529293	0	0
SrcPulseCheck_M	2147483647	527999	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	529293
T1	0	468
T2	0	398
T3	0	401
T4	0	50
T5	0	180
T6	0	110
T7	92636	64
T8	722642	870
T9	0	180
T10	22631	0
T11	10053	0
T14	0	5951
T15	0	88
T16	0	1036
T28	12937	0
T29	14526	0
T30	8365	0
T31	30376	0
T32	26501	0
T33	10462	0
T38	0	96
T39	0	100
T74	7066	1
T78	15772	3
T81	14972	2
T82	6067	1
T83	10556	0
T143	29920	2
T144	21658	2
T145	17570	4
T146	12500	0
T147	15660	0
T148	12058	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	527999
T1	0	468
T2	0	398
T3	0	401
T4	0	50
T5	0	180
T6	0	110
T7	49184	64
T8	139725	870
T9	0	180
T10	9114	0
T11	6026	0
T14	0	5951
T15	0	88
T16	0	1036
T28	7596	0
T29	8486	0
T30	3667	0
T31	9666	0
T32	8474	0
T33	4553	0
T38	0	96
T39	0	100
T74	2835	1
T78	14340	3
T81	6054	2
T82	12232	1
T83	4398	0
T143	12630	2
T144	8650	2
T145	7586	4
T146	23560	0
T147	14126	0
T148	21370	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	228117875	13817	0	0
SrcPulseCheck_M	71256824	13817	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	228117875	13817
T1	0	36
T2	0	26
T3	0	24
T4	0	10
T5	0	36
T6	0	22
T7	19267	4
T8	165920	36
T9	0	8
T10	5004	0
T11	2114	0
T28	2612	0
T29	2905	0
T30	1958	0
T31	7253	0
T32	6597	0
T33	2395	0
T39	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	71256824	13817
T1	0	36
T2	0	26
T3	0	24
T4	0	10
T5	0	36
T6	0	22
T7	19670	4
T8	27592	36
T9	0	8
T10	2398	0
T11	2202	0
T28	2720	0
T29	3025	0
T30	1080	0
T31	1812	0
T32	1649	0
T33	1321	0
T39	0	20

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	228117875	19569	0	0
SrcPulseCheck_M	71256824	19592	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	228117875	19569
T1	0	36
T2	0	26
T3	0	24
T4	0	20
T5	0	72
T6	0	44
T7	19267	4
T8	165920	36
T9	0	8
T10	5004	0
T11	2114	0
T28	2612	0
T29	2905	0
T30	1958	0
T31	7253	0
T32	6597	0
T33	2395	0
T39	0	40

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	71256824	19592
T1	0	36
T2	0	26
T3	0	24
T4	0	20
T5	0	72
T6	0	44
T7	19670	4
T8	27592	36
T9	0	8
T10	2398	0
T11	2202	0
T28	2720	0
T29	3025	0
T30	1080	0
T31	1812	0
T32	1649	0
T33	1321	0
T39	0	40

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	71256824	19558	0	0
SrcPulseCheck_M	228117875	19577	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	71256824	19558
T1	0	36
T2	0	26
T3	0	24
T4	0	20
T5	0	72
T6	0	44
T7	19670	4
T8	27592	36
T9	0	8
T10	2398	0
T11	2202	0
T28	2720	0
T29	3025	0
T30	1080	0
T31	1812	0
T32	1649	0
T33	1321	0
T39	0	40

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	228117875	19577
T1	0	36
T2	0	26
T3	0	24
T4	0	20
T5	0	72
T6	0	44
T7	19267	4
T8	165920	36
T9	0	8
T10	5004	0
T11	2114	0
T28	2612	0
T29	2905	0
T30	1958	0
T31	7253	0
T32	6597	0
T33	2395	0
T39	0	40

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	113276091	13817	0	0
SrcPulseCheck_M	71256824	13817	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	113276091	13817
T1	0	36
T2	0	26
T3	0	24
T4	0	10
T5	0	36
T6	0	22
T7	9608	4
T8	82941	36
T9	0	8
T10	2862	0
T11	1010	0
T28	1396	0
T29	1592	0
T30	939	0
T31	3930	0
T32	3252	0
T33	1215	0
T39	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	71256824	13817
T1	0	36
T2	0	26
T3	0	24
T4	0	10
T5	0	36
T6	0	22
T7	19670	4
T8	27592	36
T9	0	8
T10	2398	0
T11	2202	0
T28	2720	0
T29	3025	0
T30	1080	0
T31	1812	0
T32	1649	0
T33	1321	0
T39	0	20

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	113276091	19459	0	0
SrcPulseCheck_M	71256824	19488	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	113276091	19459
T1	0	36
T2	0	26
T3	0	24
T4	0	20
T5	0	72
T6	0	44
T7	9608	4
T8	82941	36
T9	0	8
T10	2862	0
T11	1010	0
T28	1396	0
T29	1592	0
T30	939	0
T31	3930	0
T32	3252	0
T33	1215	0
T39	0	40

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	71256824	19488
T1	0	36
T2	0	26
T3	0	24
T4	0	20
T5	0	72
T6	0	44
T7	19670	4
T8	27592	36
T9	0	8
T10	2398	0
T11	2202	0
T28	2720	0
T29	3025	0
T30	1080	0
T31	1812	0
T32	1649	0
T33	1321	0
T39	0	40

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	71256824	19456	0	0
SrcPulseCheck_M	113276091	19461	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	71256824	19456
T1	0	36
T2	0	26
T3	0	24
T4	0	20
T5	0	72
T6	0	44
T7	19670	4
T8	27592	36
T9	0	8
T10	2398	0
T11	2202	0
T28	2720	0
T29	3025	0
T30	1080	0
T31	1812	0
T32	1649	0
T33	1321	0
T39	0	40

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	113276091	19461
T1	0	36
T2	0	26
T3	0	24
T4	0	20
T5	0	72
T6	0	44
T7	9608	4
T8	82941	36
T9	0	8
T10	2862	0
T11	1010	0
T28	1396	0
T29	1592	0
T30	939	0
T31	3930	0
T32	3252	0
T33	1215	0
T39	0	40

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	56637693	13817	0	0
SrcPulseCheck_M	71256824	13817	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	56637693	13817
T1	0	36
T2	0	26
T3	0	24
T4	0	10
T5	0	36
T6	0	22
T7	4804	4
T8	41470	36
T9	0	8
T10	1430	0
T11	505	0
T28	697	0
T29	795	0
T30	470	0
T31	1965	0
T32	1626	0
T33	607	0
T39	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	71256824	13817
T1	0	36
T2	0	26
T3	0	24
T4	0	10
T5	0	36
T6	0	22
T7	19670	4
T8	27592	36
T9	0	8
T10	2398	0
T11	2202	0
T28	2720	0
T29	3025	0
T30	1080	0
T31	1812	0
T32	1649	0
T33	1321	0
T39	0	20

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	56637693	19548	0	0
SrcPulseCheck_M	71256824	19589	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	56637693	19548
T1	0	36
T2	0	26
T3	0	24
T4	0	20
T5	0	72
T6	0	44
T7	4804	4
T8	41470	36
T9	0	8
T10	1430	0
T11	505	0
T28	697	0
T29	795	0
T30	470	0
T31	1965	0
T32	1626	0
T33	607	0
T39	0	40

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	71256824	19589
T1	0	36
T2	0	26
T3	0	24
T4	0	20
T5	0	72
T6	0	44
T7	19670	4
T8	27592	36
T9	0	8
T10	2398	0
T11	2202	0
T28	2720	0
T29	3025	0
T30	1080	0
T31	1812	0
T32	1649	0
T33	1321	0
T39	0	40

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	71256824	19543	0	0
SrcPulseCheck_M	56637693	19554	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	71256824	19543
T1	0	36
T2	0	26
T3	0	24
T4	0	20
T5	0	72
T6	0	44
T7	19670	4
T8	27592	36
T9	0	8
T10	2398	0
T11	2202	0
T28	2720	0
T29	3025	0
T30	1080	0
T31	1812	0
T32	1649	0
T33	1321	0
T39	0	40

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	56637693	19554
T1	0	36
T2	0	26
T3	0	24
T4	0	20
T5	0	72
T6	0	44
T7	4804	4
T8	41470	36
T9	0	8
T10	1430	0
T11	505	0
T28	697	0
T29	795	0
T30	470	0
T31	1965	0
T32	1626	0
T33	607	0
T39	0	40

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	243186787	13817	0	0
SrcPulseCheck_M	71256824	13817	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	243186787	13817
T1	0	36
T2	0	26
T3	0	24
T4	0	10
T5	0	36
T6	0	22
T7	20071	4
T8	238837	36
T9	0	8
T10	5213	0
T11	2202	0
T28	2720	0
T29	3025	0
T30	2040	0
T31	7556	0
T32	6873	0
T33	2494	0
T39	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	71256824	13817
T1	0	36
T2	0	26
T3	0	24
T4	0	10
T5	0	36
T6	0	22
T7	19670	4
T8	27592	36
T9	0	8
T10	2398	0
T11	2202	0
T28	2720	0
T29	3025	0
T30	1080	0
T31	1812	0
T32	1649	0
T33	1321	0
T39	0	20

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	243186787	19564	0	0
SrcPulseCheck_M	71256824	19577	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	243186787	19564
T1	0	36
T2	0	26
T3	0	24
T4	0	20
T5	0	72
T6	0	44
T7	20071	4
T8	238837	36
T9	0	8
T10	5213	0
T11	2202	0
T28	2720	0
T29	3025	0
T30	2040	0
T31	7556	0
T32	6873	0
T33	2494	0
T39	0	40

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	71256824	19577
T1	0	36
T2	0	26
T3	0	24
T4	0	20
T5	0	72
T6	0	44
T7	19670	4
T8	27592	36
T9	0	8
T10	2398	0
T11	2202	0
T28	2720	0
T29	3025	0
T30	1080	0
T31	1812	0
T32	1649	0
T33	1321	0
T39	0	40

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	71256824	19556	0	0
SrcPulseCheck_M	243186787	19567	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	71256824	19556
T1	0	36
T2	0	26
T3	0	24
T4	0	20
T5	0	72
T6	0	44
T7	19670	4
T8	27592	36
T9	0	8
T10	2398	0
T11	2202	0
T28	2720	0
T29	3025	0
T30	1080	0
T31	1812	0
T32	1649	0
T33	1321	0
T39	0	40

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	243186787	19567
T1	0	36
T2	0	26
T3	0	24
T4	0	20
T5	0	72
T6	0	44
T7	20071	4
T8	238837	36
T9	0	8
T10	5213	0
T11	2202	0
T28	2720	0
T29	3025	0
T30	2040	0
T31	7556	0
T32	6873	0
T33	2494	0
T39	0	40

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	116767562	13353	0	0
SrcPulseCheck_M	71256824	13817	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	116767562	13353
T1	0	36
T2	0	26
T3	0	24
T4	0	5
T5	0	29
T6	0	11
T7	9633	4
T8	120403	36
T9	0	8
T10	2501	0
T11	1057	0
T28	1305	0
T29	1453	0
T30	979	0
T31	3626	0
T32	3299	0
T33	1197	0
T39	0	10

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	71256824	13817
T1	0	36
T2	0	26
T3	0	24
T4	0	10
T5	0	36
T6	0	22
T7	19670	4
T8	27592	36
T9	0	8
T10	2398	0
T11	2202	0
T28	2720	0
T29	3025	0
T30	1080	0
T31	1812	0
T32	1649	0
T33	1321	0
T39	0	20

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	116767562	19319	0	0
SrcPulseCheck_M	71256824	19499	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	116767562	19319
T1	0	36
T2	0	26
T3	0	24
T4	0	20
T5	0	72
T6	0	33
T7	9633	4
T8	120403	36
T9	0	8
T10	2501	0
T11	1057	0
T28	1305	0
T29	1453	0
T30	979	0
T31	3626	0
T32	3299	0
T33	1197	0
T39	0	40

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	71256824	19499
T1	0	36
T2	0	26
T3	0	24
T4	0	20
T5	0	72
T6	0	44
T7	19670	4
T8	27592	36
T9	0	8
T10	2398	0
T11	2202	0
T28	2720	0
T29	3025	0
T30	1080	0
T31	1812	0
T32	1649	0
T33	1321	0
T39	0	40

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	71256824	19130	0	0
SrcPulseCheck_M	116767562	19343	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	71256824	19130
T1	0	36
T2	0	26
T3	0	24
T4	0	20
T5	0	71
T6	0	33
T7	19670	4
T8	27592	36
T9	0	8
T10	2398	0
T11	2202	0
T28	2720	0
T29	3025	0
T30	1080	0
T31	1812	0
T32	1649	0
T33	1321	0
T39	0	30

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	116767562	19343
T1	0	36
T2	0	26
T3	0	24
T4	0	20
T5	0	72
T6	0	33
T7	9633	4
T8	120403	36
T9	0	8
T10	2501	0
T11	1057	0
T28	1305	0
T29	1453	0
T30	979	0
T31	3626	0
T32	3299	0
T33	1197	0
T39	0	40

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T75,T79,T78
1	0	Covered	T75,T79,T78
1	1	Covered	T79,T78,T145

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T75,T79,T78
1	0	Covered	T79,T78,T145
1	1	Covered	T75,T79,T78

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	71256824	43	0	0
SrcPulseCheck_M	228117875	43	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	71256824	43
T75	2915	1
T78	7886	3
T79	5518	2
T80	3298	1
T83	10556	1
T144	10829	2
T145	8785	3
T146	6250	4
T149	6214	1
T150	7823	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	228117875	43
T75	11658	1
T78	15772	3
T79	9630	2
T80	12666	1
T83	10556	1
T144	10395	2
T145	8604	3
T146	24999	4
T149	25936	1
T150	25899	1

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T75,T78,T80
1	0	Covered	T75,T78,T80
1	1	Covered	T75,T145,T146

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T75,T78,T80
1	0	Covered	T75,T145,T146
1	1	Covered	T75,T78,T80

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	71256824	45	0	0
SrcPulseCheck_M	228117875	45	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	71256824	45
T75	2915	2
T78	7886	1
T80	3298	1
T83	10556	2
T144	10829	1
T145	8785	3
T146	6250	4
T147	7830	1
T148	6029	1
T151	7947	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	228117875	45
T75	11658	2
T78	15772	1
T80	12666	1
T83	10556	2
T144	10395	1
T145	8604	3
T146	24999	4
T147	15035	1
T148	23152	1
T151	29342	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T74,T82,T81
1	0	Covered	T74,T82,T81
1	1	Covered	T78,T143,T145

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T74,T82,T81
1	0	Covered	T78,T143,T145
1	1	Covered	T74,T82,T81

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	71256824	36	0	0
SrcPulseCheck_M	113276091	36	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	71256824	36
T74	7066	1
T78	7886	3
T81	7486	2
T82	6067	1
T143	14960	2
T144	10829	2
T145	8785	4
T146	6250	1
T147	7830	1
T148	6029	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	113276091	36
T74	2835	1
T78	7170	3
T81	3027	2
T82	12232	1
T143	6315	2
T144	4325	2
T145	3793	4
T146	11780	1
T147	7063	1
T148	10685	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T81,T78,T83
1	0	Covered	T81,T78,T83
1	1	Covered	T78,T143,T145

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T81,T78,T83
1	0	Covered	T78,T143,T145
1	1	Covered	T81,T78,T83

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	71256824	35	0	0
SrcPulseCheck_M	113276091	35	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	71256824	35
T78	7886	2
T81	7486	2
T83	10556	1
T143	14960	3
T144	10829	1
T145	8785	3
T146	6250	2
T147	7830	1
T148	6029	2
T151	7947	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	113276091	35
T78	7170	2
T81	3027	2
T83	4398	1
T143	6315	3
T144	4325	1
T145	3793	3
T146	11780	2
T147	7063	1
T148	10685	2
T151	13799	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T74,T75,T82
1	0	Covered	T74,T75,T82
1	1	Covered	T74,T82,T151

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T74,T75,T82
1	0	Covered	T74,T82,T151
1	1	Covered	T74,T75,T82

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	71256824	41	0	0
SrcPulseCheck_M	56637693	41	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	71256824	41
T74	7066	3
T75	2915	1
T76	7511	2
T80	3298	1
T81	7486	1
T82	6067	2
T144	10829	1
T145	8785	1
T151	7947	4
T152	2438	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	56637693	41
T74	1420	3
T75	2711	1
T76	3228	2
T80	2926	1
T81	1514	1
T82	6117	2
T144	2162	1
T145	1896	1
T151	6902	4
T152	2208	2

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T74,T82,T76
1	0	Covered	T74,T82,T76
1	1	Covered	T152,T144,T153

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T74,T82,T76
1	0	Covered	T152,T144,T153
1	1	Covered	T74,T82,T76

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	71256824	34	0	0
SrcPulseCheck_M	56637693	34	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	71256824	34
T74	7066	2
T76	7511	1
T81	7486	1
T82	6067	1
T144	10829	2
T145	8785	1
T146	6250	1
T149	6214	1
T151	7947	2
T152	2438	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	56637693	34
T74	1420	2
T76	3228	1
T81	1514	1
T82	6117	1
T144	2162	2
T145	1896	1
T146	5890	1
T149	6269	1
T151	6902	2
T152	2208	2

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T77,T75,T78
1	0	Covered	T77,T75,T78
1	1	Covered	T149,T151,T145

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T77,T75,T78
1	0	Covered	T149,T151,T145
1	1	Covered	T77,T75,T78

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	71256824	26	0	0
SrcPulseCheck_M	243186787	26	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	71256824	26
T75	2915	1
T77	6715	1
T78	7886	1
T80	3298	1
T83	10556	1
T145	8785	2
T149	6214	2
T150	7823	1
T151	7947	4
T152	2438	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	243186787	26
T75	12145	1
T77	6715	1
T78	16430	1
T80	13195	1
T83	10997	1
T145	8963	2
T149	27018	2
T150	26979	1
T151	30566	4
T152	10161	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T77,T75,T78
1	0	Covered	T77,T75,T78
1	1	Covered	T77,T75,T151

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T77,T75,T78
1	0	Covered	T77,T75,T151
1	1	Covered	T77,T75,T78

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	71256824	32	0	0
SrcPulseCheck_M	243186787	32	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	71256824	32
T75	2915	2
T77	6715	2
T78	7886	1
T80	3298	1
T83	10556	1
T145	8785	3
T146	6250	1
T149	6214	1
T150	7823	2
T151	7947	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	243186787	32
T75	12145	2
T77	6715	2
T78	16430	1
T80	13195	1
T83	10997	1
T145	8963	3
T146	26042	1
T149	27018	1
T150	26979	2
T151	30566	5

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T74,T76,T81
1	0	Covered	T74,T76,T81
1	1	Covered	T83,T145,T154

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T74,T76,T81
1	0	Covered	T83,T145,T154
1	1	Covered	T74,T76,T81

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	71256824	40	0	0
SrcPulseCheck_M	116767562	40	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	71256824	40
T74	7066	1
T76	7511	1
T78	7886	2
T79	5518	1
T81	7486	1
T83	10556	3
T143	14960	1
T145	8785	3
T151	7947	1
T152	2438	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	116767562	40
T74	3425	1
T76	7211	1
T78	7886	2
T79	4815	1
T81	3593	1
T83	5278	3
T143	7326	1
T145	4303	3
T151	14672	1
T152	4877	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T74,T75,T76
1	0	Covered	T74,T75,T76
1	1	Covered	T78,T145,T146

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T74,T75,T76
1	0	Covered	T78,T145,T146
1	1	Covered	T74,T75,T76

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	71256824	37	0	0
SrcPulseCheck_M	116767562	37	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	71256824	37
T74	7066	1
T75	2915	1
T76	7511	1
T78	7886	2
T79	5518	1
T81	7486	1
T83	10556	2
T149	6214	1
T151	7947	1
T152	2438	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	116767562	37
T74	3425	1
T75	5830	1
T76	7211	1
T78	7886	2
T79	4815	1
T81	3593	1
T83	5278	2
T149	12968	1
T151	14672	1
T152	4877	2

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11

Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	225073845	49519	0	0
SrcPulseCheck_M	7112361	48872	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	225073845	49519
T1	0	90
T2	0	86
T3	0	88
T7	19267	13
T8	165920	172
T9	0	30
T10	5004	0
T11	2114	0
T14	0	1459
T15	0	22
T16	0	259
T28	2612	0
T29	2905	0
T30	1958	0
T31	7253	0
T32	6597	0
T33	2395	0
T38	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7112361	48872
T1	0	90
T2	0	86
T3	0	88
T7	59	13
T8	367	172
T9	0	30
T10	364	0
T11	153	0
T14	0	1459
T15	0	22
T16	0	259
T28	190	0
T29	211	0
T30	142	0
T31	528	0
T32	481	0
T33	174	0
T38	0	24

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	111800817	49328	0	0
SrcPulseCheck_M	7112361	48688	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	111800817	49328
T1	0	90
T2	0	79
T3	0	84
T7	9608	13
T8	82941	160
T9	0	30
T10	2862	0
T11	1010	0
T14	0	1443
T15	0	22
T16	0	259
T28	1396	0
T29	1592	0
T30	939	0
T31	3930	0
T32	3252	0
T33	1215	0
T38	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7112361	48688
T1	0	90
T2	0	79
T3	0	84
T7	59	13
T8	367	160
T9	0	30
T10	364	0
T11	153	0
T14	0	1443
T15	0	22
T16	0	259
T28	190	0
T29	211	0
T30	142	0
T31	528	0
T32	481	0
T33	174	0
T38	0	24

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	55900042	48865	0	0
SrcPulseCheck_M	7112361	48232	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	55900042	48865
T1	0	90
T2	0	80
T3	0	78
T7	4804	13
T8	41470	154
T9	0	30
T10	1430	0
T11	505	0
T14	0	1386
T15	0	22
T16	0	259
T28	697	0
T29	795	0
T30	470	0
T31	1965	0
T32	1626	0
T33	607	0
T38	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7112361	48232
T1	0	90
T2	0	80
T3	0	78
T7	59	13
T8	367	154
T9	0	30
T10	364	0
T11	153	0
T14	0	1386
T15	0	22
T16	0	259
T28	190	0
T29	211	0
T30	142	0
T31	528	0
T32	481	0
T33	174	0
T38	0	24

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11

Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	240015796	59192	0	0
SrcPulseCheck_M	7137656	58809	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	240015796	59192
T1	0	90
T2	0	75
T3	0	79
T7	20071	13
T8	238837	276
T9	0	66
T10	5213	0
T11	2202	0
T14	0	1663
T15	0	22
T16	0	259
T28	2720	0
T29	3025	0
T30	2040	0
T31	7556	0
T32	6873	0
T33	2494	0
T38	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7137656	58809
T1	0	90
T2	0	75
T3	0	79
T7	59	13
T8	499	276
T9	0	66
T10	364	0
T11	153	0
T14	0	1663
T15	0	22
T16	0	259
T28	190	0
T29	211	0
T30	142	0
T31	528	0
T32	481	0
T33	174	0
T38	0	24

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T7,T10,T11

Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	115245515	58697	0	0
SrcPulseCheck_M	7140714	58697	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	115245515	58697
T1	0	90
T2	0	75
T3	0	77
T7	9633	13
T8	120403	302
T9	0	66
T10	2501	0
T11	1057	0
T14	0	1582
T15	0	22
T16	0	259
T28	1305	0
T29	1453	0
T30	979	0
T31	3626	0
T32	3299	0
T33	1197	0
T38	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7140714	58697
T1	0	90
T2	0	75
T3	0	77
T7	59	13
T8	523	302
T9	0	66
T10	364	0
T11	153	0
T14	0	1582
T15	0	22
T16	0	259
T28	190	0
T29	211	0
T30	142	0
T31	528	0
T32	481	0
T33	174	0
T38	0	24

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_io_meas_ctrl_en_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	91.67			100.00	100.00	u_io_meas_ctrl_shadowed_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb