Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	71256824	1803638	0	0
clk_enables_rd_A	71256824	19421	0	0
clk_hints_rd_A	71256824	17341	0	0
extclk_ctrl_rd_A	71256824	21499	0	0
extclk_ctrl_regwen_rd_A	71256824	16524	0	0
jitter_enable_rd_A	71256824	25004	0	0
jitter_regwen_rd_A	71256824	17402	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71256824	1803638	0	0
T14	221176	69770	0	0
T15	64026	0	0	0
T35	0	124729	0	0
T38	21581	0	0	0
T48	1165	0	0	0
T51	0	37024	0	0
T84	0	97786	0	0
T85	0	141711	0	0
T86	0	145801	0	0
T87	0	52447	0	0
T88	0	45696	0	0
T89	0	145108	0	0
T90	0	93438	0	0
T91	2868	0	0	0
T92	2157	0	0	0
T93	2285	0	0	0
T94	1415	0	0	0
T95	1713	0	0	0
T96	1196	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71256824	19421	0	0
T9	6161	0	0	0
T14	0	1421	0	0
T22	0	4	0	0
T26	0	2	0	0
T32	1649	2	0	0
T33	1321	0	0	0
T35	0	2437	0	0
T42	1663	0	0	0
T43	1599	0	0	0
T46	1183	0	0	0
T50	1827	0	0	0
T51	0	729	0	0
T57	0	3	0	0
T97	1379	0	0	0
T98	2979	0	0	0
T155	0	5	0	0
T156	0	9	0	0
T157	0	4	0	0
T158	1143	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71256824	17341	0	0
T9	6161	0	0	0
T14	0	1274	0	0
T22	0	1	0	0
T26	0	2	0	0
T32	1649	2	0	0
T33	1321	0	0	0
T35	0	2038	0	0
T42	1663	0	0	0
T43	1599	0	0	0
T46	1183	0	0	0
T50	1827	0	0	0
T51	0	734	0	0
T57	0	4	0	0
T97	1379	0	0	0
T98	2979	0	0	0
T155	0	2	0	0
T156	0	3	0	0
T157	0	3	0	0
T158	1143	0	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71256824	21499	0	0
T4	0	35	0	0
T5	0	126	0	0
T8	27592	0	0	0
T29	3025	61	0	0
T30	1080	0	0	0
T31	1812	42	0	0
T32	1649	0	0	0
T33	1321	0	0	0
T40	0	38	0	0
T42	1663	0	0	0
T43	1599	0	0	0
T50	1827	0	0	0
T99	0	33	0	0
T102	0	63	0	0
T142	0	38	0	0
T158	1143	0	0	0
T159	0	21	0	0
T160	0	38	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71256824	16524	0	0
T4	26745	21	0	0
T5	62977	85	0	0
T6	60279	0	0	0
T14	0	1167	0	0
T35	0	2317	0	0
T40	0	18	0	0
T44	1051	0	0	0
T51	0	715	0	0
T73	0	39	0	0
T100	2660	0	0	0
T101	1203	0	0	0
T102	2791	0	0	0
T103	1687	0	0	0
T139	840	0	0	0
T159	0	29	0	0
T161	0	46	0	0
T162	0	7	0	0
T163	838	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71256824	25004	0	0
T9	6161	0	0	0
T14	0	1996	0	0
T22	0	133	0	0
T26	0	127	0	0
T32	1649	92	0	0
T33	1321	0	0	0
T35	0	3129	0	0
T42	1663	0	0	0
T43	1599	0	0	0
T46	1183	0	0	0
T50	1827	0	0	0
T51	0	803	0	0
T93	0	60	0	0
T97	1379	0	0	0
T98	2979	0	0	0
T155	0	104	0	0
T156	0	112	0	0
T158	1143	0	0	0
T164	0	124	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71256824	17402	0	0
T14	221176	1233	0	0
T15	64026	0	0	0
T35	0	2489	0	0
T38	21581	0	0	0
T48	1165	0	0	0
T51	0	779	0	0
T84	0	3806	0	0
T85	0	5033	0	0
T91	2868	0	0	0
T92	2157	0	0	0
T93	2285	0	0	0
T94	1415	0	0	0
T95	1713	0	0	0
T96	1196	0	0	0
T129	0	11	0	0
T130	0	8	0	0
T165	0	1530	0	0
T166	0	2	0	0
T167	0	230	0	0