Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T28
1	0	Covered	T10,T28,T29
1	1	Covered	T10,T28,T29

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	225074271	2714	0	0
g_div2.Div2Whole_A	225074271	3264	0	0
g_div4.Div4Stepped_A	111801211	2661	0	0
g_div4.Div4Whole_A	111801211	3117	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225074271	2714	0	0
T8	165920	0	0	0
T10	5005	10	0	0
T11	2115	0	0	0
T28	2612	3	0	0
T29	2906	7	0	0
T30	1958	0	0	0
T31	7254	5	0	0
T32	6598	0	0	0
T33	2395	3	0	0
T42	1598	0	0	0
T50	0	1	0	0
T99	0	8	0	0
T102	0	13	0	0
T139	0	2	0	0
T142	0	4	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225074271	3264	0	0
T8	165920	0	0	0
T10	5005	12	0	0
T11	2115	0	0	0
T28	2612	13	0	0
T29	2906	8	0	0
T30	1958	0	0	0
T31	7254	5	0	0
T32	6598	0	0	0
T33	2395	3	0	0
T42	1598	0	0	0
T50	0	5	0	0
T97	0	2	0	0
T99	0	8	0	0
T102	0	15	0	0
T139	0	1	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111801211	2661	0	0
T8	82941	0	0	0
T10	2862	10	0	0
T11	1011	0	0	0
T28	1396	3	0	0
T29	1592	7	0	0
T30	940	0	0	0
T31	3931	5	0	0
T32	3252	0	0	0
T33	1215	3	0	0
T42	780	0	0	0
T50	0	1	0	0
T99	0	8	0	0
T102	0	12	0	0
T139	0	2	0	0
T142	0	3	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111801211	3117	0	0
T8	82941	0	0	0
T10	2862	12	0	0
T11	1011	0	0	0
T28	1396	12	0	0
T29	1592	8	0	0
T30	940	0	0	0
T31	3931	5	0	0
T32	3252	0	0	0
T33	1215	3	0	0
T42	780	0	0	0
T50	0	5	0	0
T97	0	2	0	0
T99	0	8	0	0
T102	0	13	0	0
T139	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T28
1	0	Covered	T10,T28,T29
1	1	Covered	T10,T28,T29

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	225074271	2714	0	0
g_div2.Div2Whole_A	225074271	3264	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225074271	2714	0	0
T8	165920	0	0	0
T10	5005	10	0	0
T11	2115	0	0	0
T28	2612	3	0	0
T29	2906	7	0	0
T30	1958	0	0	0
T31	7254	5	0	0
T32	6598	0	0	0
T33	2395	3	0	0
T42	1598	0	0	0
T50	0	1	0	0
T99	0	8	0	0
T102	0	13	0	0
T139	0	2	0	0
T142	0	4	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225074271	3264	0	0
T8	165920	0	0	0
T10	5005	12	0	0
T11	2115	0	0	0
T28	2612	13	0	0
T29	2906	8	0	0
T30	1958	0	0	0
T31	7254	5	0	0
T32	6598	0	0	0
T33	2395	3	0	0
T42	1598	0	0	0
T50	0	5	0	0
T97	0	2	0	0
T99	0	8	0	0
T102	0	15	0	0
T139	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T28
1	0	Covered	T10,T28,T29
1	1	Covered	T10,T28,T29

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	111801211	2661	0	0
g_div4.Div4Whole_A	111801211	3117	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111801211	2661	0	0
T8	82941	0	0	0
T10	2862	10	0	0
T11	1011	0	0	0
T28	1396	3	0	0
T29	1592	7	0	0
T30	940	0	0	0
T31	3931	5	0	0
T32	3252	0	0	0
T33	1215	3	0	0
T42	780	0	0	0
T50	0	1	0	0
T99	0	8	0	0
T102	0	12	0	0
T139	0	2	0	0
T142	0	3	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111801211	3117	0	0
T8	82941	0	0	0
T10	2862	12	0	0
T11	1011	0	0	0
T28	1396	12	0	0
T29	1592	8	0	0
T30	940	0	0	0
T31	3931	5	0	0
T32	3252	0	0	0
T33	1215	3	0	0
T42	780	0	0	0
T50	0	5	0	0
T97	0	2	0	0
T99	0	8	0	0
T102	0	13	0	0
T139	0	1	0	0