Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	210843483	434	0	0
StatusRise_A	210843483	434	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210843483	434	0	0
T14	663528	0	0	0
T38	64743	0	0	0
T47	3681	18	0	0
T48	0	11	0	0
T49	0	9	0	0
T69	0	5	0	0
T91	8604	0	0	0
T140	4560	0	0	0
T142	7122	0	0	0
T155	6051	0	0	0
T159	24129	0	0	0
T160	6945	0	0	0
T168	0	8	0	0
T169	0	2	0	0
T170	0	3	0	0
T171	0	5	0	0
T172	0	7	0	0
T173	0	9	0	0
T174	0	4	0	0
T175	3207	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210843483	434	0	0
T14	663528	0	0	0
T38	64743	0	0	0
T47	3681	18	0	0
T48	0	11	0	0
T49	0	9	0	0
T69	0	5	0	0
T91	8604	0	0	0
T140	4560	0	0	0
T142	7122	0	0	0
T155	6051	0	0	0
T159	24129	0	0	0
T160	6945	0	0	0
T168	0	8	0	0
T169	0	2	0	0
T170	0	3	0	0
T171	0	5	0	0
T172	0	7	0	0
T173	0	9	0	0
T174	0	4	0	0
T175	3207	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	70281161	143	0	0
StatusRise_A	70281161	143	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70281161	143	0	0
T14	221176	0	0	0
T38	21581	0	0	0
T47	1227	6	0	0
T48	0	3	0	0
T49	0	4	0	0
T69	0	2	0	0
T91	2868	0	0	0
T140	1520	0	0	0
T142	2374	0	0	0
T155	2017	0	0	0
T159	8043	0	0	0
T160	2315	0	0	0
T168	0	4	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	2	0	0
T172	0	2	0	0
T173	0	4	0	0
T175	1069	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70281161	143	0	0
T14	221176	0	0	0
T38	21581	0	0	0
T47	1227	6	0	0
T48	0	3	0	0
T49	0	4	0	0
T69	0	2	0	0
T91	2868	0	0	0
T140	1520	0	0	0
T142	2374	0	0	0
T155	2017	0	0	0
T159	8043	0	0	0
T160	2315	0	0	0
T168	0	4	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	2	0	0
T172	0	2	0	0
T173	0	4	0	0
T175	1069	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	70281161	150	0	0
StatusRise_A	70281161	150	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70281161	150	0	0
T14	221176	0	0	0
T38	21581	0	0	0
T47	1227	7	0	0
T48	0	4	0	0
T49	0	2	0	0
T69	0	2	0	0
T91	2868	0	0	0
T140	1520	0	0	0
T142	2374	0	0	0
T155	2017	0	0	0
T159	8043	0	0	0
T160	2315	0	0	0
T168	0	3	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	3	0	0
T173	0	3	0	0
T175	1069	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70281161	150	0	0
T14	221176	0	0	0
T38	21581	0	0	0
T47	1227	7	0	0
T48	0	4	0	0
T49	0	2	0	0
T69	0	2	0	0
T91	2868	0	0	0
T140	1520	0	0	0
T142	2374	0	0	0
T155	2017	0	0	0
T159	8043	0	0	0
T160	2315	0	0	0
T168	0	3	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	3	0	0
T173	0	3	0	0
T175	1069	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	70281161	141	0	0
StatusRise_A	70281161	141	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70281161	141	0	0
T14	221176	0	0	0
T38	21581	0	0	0
T47	1227	5	0	0
T48	0	4	0	0
T49	0	3	0	0
T69	0	1	0	0
T91	2868	0	0	0
T140	1520	0	0	0
T142	2374	0	0	0
T155	2017	0	0	0
T159	8043	0	0	0
T160	2315	0	0	0
T168	0	1	0	0
T170	0	1	0	0
T171	0	2	0	0
T172	0	2	0	0
T173	0	2	0	0
T174	0	4	0	0
T175	1069	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70281161	141	0	0
T14	221176	0	0	0
T38	21581	0	0	0
T47	1227	5	0	0
T48	0	4	0	0
T49	0	3	0	0
T69	0	1	0	0
T91	2868	0	0	0
T140	1520	0	0	0
T142	2374	0	0	0
T155	2017	0	0	0
T159	8043	0	0	0
T160	2315	0	0	0
T168	0	1	0	0
T170	0	1	0	0
T171	0	2	0	0
T172	0	2	0	0
T173	0	2	0	0
T174	0	4	0	0
T175	1069	0	0	0