Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T7,T10,T11
1	1	Covered	T7,T10,T11

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	29484	0	0
CgEnOn_A	2147483647	21202	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	29484	0	0
T7	33679	3	0	0
T8	529168	3	0	0
T10	9296	3	0	0
T11	5831	7	0	0
T14	2025927	0	0	0
T28	7425	3	0	0
T29	8317	3	0	0
T30	5407	10	0	0
T31	20704	3	0	0
T32	18348	7	0	0
T33	6711	3	0	0
T38	97058	0	0	0
T42	1663	0	0	0
T46	0	1	0	0
T47	14955	35	0	0
T48	0	20	0	0
T49	0	10	0	0
T69	0	10	0	0
T91	13002	0	0	0
T140	35177	0	0	0
T142	5331	0	0	0
T155	18770	0	0	0
T159	111270	0	0	0
T160	5221	0	0	0
T168	0	15	0	0
T169	0	5	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	15	0	0
T173	0	15	0	0
T175	9575	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21202	0	0
T8	1366082	0	0	0
T11	13494	4	0	0
T14	4392056	0	0	0
T21	0	17	0	0
T22	0	4	0	0
T25	0	42	0	0
T28	16890	0	0	0
T29	18845	0	0	0
T30	12506	7	0	0
T31	46998	0	0	0
T32	42266	4	0	0
T33	15390	0	0	0
T38	208557	0	0	0
T42	10216	0	0	0
T46	0	4	0	0
T47	31003	35	0	0
T48	0	20	0	0
T49	0	10	0	0
T50	22503	0	0	0
T69	0	10	0	0
T91	27232	0	0	0
T98	0	5	0	0
T101	0	12	0	0
T140	72903	0	0	0
T142	11399	0	0	0
T155	40512	0	0	0
T158	0	14	0	0
T159	264707	0	0	0
T160	11203	0	0	0
T163	0	8	0	0
T168	0	15	0	0
T169	0	5	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	15	0	0
T173	0	15	0	0
T175	20631	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T7,T10,T11

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	111800817	154	0	0
CgEnOn_A	111800817	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111800817	154	0	0
T14	450333	0	0	0
T38	21560	0	0	0
T47	3297	7	0	0
T48	0	4	0	0
T49	0	2	0	0
T69	0	2	0	0
T91	3000	0	0	0
T140	8232	0	0	0
T142	1194	0	0	0
T155	4141	0	0	0
T159	20750	0	0	0
T160	1163	0	0	0
T168	0	3	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	3	0	0
T173	0	3	0	0
T175	2118	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111800817	154	0	0
T14	450333	0	0	0
T38	21560	0	0	0
T47	3297	7	0	0
T48	0	4	0	0
T49	0	2	0	0
T69	0	2	0	0
T91	3000	0	0	0
T140	8232	0	0	0
T142	1194	0	0	0
T155	4141	0	0	0
T159	20750	0	0	0
T160	1163	0	0	0
T168	0	3	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	3	0	0
T173	0	3	0	0
T175	2118	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T7,T10,T11

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	55900042	154	0	0
CgEnOn_A	55900042	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55900042	154	0	0
T14	225166	0	0	0
T38	10780	0	0	0
T47	1648	7	0	0
T48	0	4	0	0
T49	0	2	0	0
T69	0	2	0	0
T91	1498	0	0	0
T140	4114	0	0	0
T142	596	0	0	0
T155	2071	0	0	0
T159	10376	0	0	0
T160	581	0	0	0
T168	0	3	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	3	0	0
T173	0	3	0	0
T175	1059	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55900042	154	0	0
T14	225166	0	0	0
T38	10780	0	0	0
T47	1648	7	0	0
T48	0	4	0	0
T49	0	2	0	0
T69	0	2	0	0
T91	1498	0	0	0
T140	4114	0	0	0
T142	596	0	0	0
T155	2071	0	0	0
T159	10376	0	0	0
T160	581	0	0	0
T168	0	3	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	3	0	0
T173	0	3	0	0
T175	1059	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T7,T10,T11

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	55900042	154	0	0
CgEnOn_A	55900042	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55900042	154	0	0
T14	225166	0	0	0
T38	10780	0	0	0
T47	1648	7	0	0
T48	0	4	0	0
T49	0	2	0	0
T69	0	2	0	0
T91	1498	0	0	0
T140	4114	0	0	0
T142	596	0	0	0
T155	2071	0	0	0
T159	10376	0	0	0
T160	581	0	0	0
T168	0	3	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	3	0	0
T173	0	3	0	0
T175	1059	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55900042	154	0	0
T14	225166	0	0	0
T38	10780	0	0	0
T47	1648	7	0	0
T48	0	4	0	0
T49	0	2	0	0
T69	0	2	0	0
T91	1498	0	0	0
T140	4114	0	0	0
T142	596	0	0	0
T155	2071	0	0	0
T159	10376	0	0	0
T160	581	0	0	0
T168	0	3	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	3	0	0
T173	0	3	0	0
T175	1059	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T7,T10,T11

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	55900042	154	0	0
CgEnOn_A	55900042	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55900042	154	0	0
T14	225166	0	0	0
T38	10780	0	0	0
T47	1648	7	0	0
T48	0	4	0	0
T49	0	2	0	0
T69	0	2	0	0
T91	1498	0	0	0
T140	4114	0	0	0
T142	596	0	0	0
T155	2071	0	0	0
T159	10376	0	0	0
T160	581	0	0	0
T168	0	3	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	3	0	0
T173	0	3	0	0
T175	1059	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55900042	154	0	0
T14	225166	0	0	0
T38	10780	0	0	0
T47	1648	7	0	0
T48	0	4	0	0
T49	0	2	0	0
T69	0	2	0	0
T91	1498	0	0	0
T140	4114	0	0	0
T142	596	0	0	0
T155	2071	0	0	0
T159	10376	0	0	0
T160	581	0	0	0
T168	0	3	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	3	0	0
T173	0	3	0	0
T175	1059	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T7,T10,T11

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	225073845	154	0	0
CgEnOn_A	225073845	151	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225073845	154	0	0
T14	900096	0	0	0
T38	43158	0	0	0
T47	6714	7	0	0
T48	0	4	0	0
T49	0	2	0	0
T69	0	2	0	0
T91	5508	0	0	0
T140	14603	0	0	0
T142	2349	0	0	0
T155	8416	0	0	0
T159	59392	0	0	0
T160	2315	0	0	0
T168	0	3	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	3	0	0
T173	0	3	0	0
T175	4280	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225073845	151	0	0
T14	900096	0	0	0
T38	43158	0	0	0
T47	6714	7	0	0
T48	0	4	0	0
T49	0	2	0	0
T69	0	2	0	0
T91	5508	0	0	0
T140	14603	0	0	0
T142	2349	0	0	0
T155	8416	0	0	0
T159	59392	0	0	0
T160	2315	0	0	0
T168	0	3	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	3	0	0
T173	0	3	0	0
T175	4280	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T7,T10,T11

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	240015796	143	0	0
CgEnOn_A	240015796	143	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240015796	143	0	0
T14	954430	0	0	0
T38	44959	0	0	0
T47	6338	6	0	0
T48	0	3	0	0
T49	0	4	0	0
T69	0	2	0	0
T91	5738	0	0	0
T140	15212	0	0	0
T142	2447	0	0	0
T155	8767	0	0	0
T159	61870	0	0	0
T160	2412	0	0	0
T168	0	4	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	2	0	0
T172	0	2	0	0
T173	0	4	0	0
T175	4458	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240015796	143	0	0
T14	954430	0	0	0
T38	44959	0	0	0
T47	6338	6	0	0
T48	0	3	0	0
T49	0	4	0	0
T69	0	2	0	0
T91	5738	0	0	0
T140	15212	0	0	0
T142	2447	0	0	0
T155	8767	0	0	0
T159	61870	0	0	0
T160	2412	0	0	0
T168	0	4	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	2	0	0
T172	0	2	0	0
T173	0	4	0	0
T175	4458	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T7,T10,T11

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	240015796	143	0	0
CgEnOn_A	240015796	143	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240015796	143	0	0
T14	954430	0	0	0
T38	44959	0	0	0
T47	6338	6	0	0
T48	0	3	0	0
T49	0	4	0	0
T69	0	2	0	0
T91	5738	0	0	0
T140	15212	0	0	0
T142	2447	0	0	0
T155	8767	0	0	0
T159	61870	0	0	0
T160	2412	0	0	0
T168	0	4	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	2	0	0
T172	0	2	0	0
T173	0	4	0	0
T175	4458	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240015796	143	0	0
T14	954430	0	0	0
T38	44959	0	0	0
T47	6338	6	0	0
T48	0	3	0	0
T49	0	4	0	0
T69	0	2	0	0
T91	5738	0	0	0
T140	15212	0	0	0
T142	2447	0	0	0
T155	8767	0	0	0
T159	61870	0	0	0
T160	2412	0	0	0
T168	0	4	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	2	0	0
T172	0	2	0	0
T173	0	4	0	0
T175	4458	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T7,T10,T11

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	115245515	141	0	0
CgEnOn_A	115245515	141	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115245515	141	0	0
T14	457269	0	0	0
T38	21581	0	0	0
T47	3372	5	0	0
T48	0	4	0	0
T49	0	3	0	0
T69	0	1	0	0
T91	2754	0	0	0
T140	7302	0	0	0
T142	1174	0	0	0
T155	4208	0	0	0
T159	29697	0	0	0
T160	1158	0	0	0
T168	0	1	0	0
T170	0	1	0	0
T171	0	2	0	0
T172	0	2	0	0
T173	0	2	0	0
T174	0	4	0	0
T175	2140	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115245515	141	0	0
T14	457269	0	0	0
T38	21581	0	0	0
T47	3372	5	0	0
T48	0	4	0	0
T49	0	3	0	0
T69	0	1	0	0
T91	2754	0	0	0
T140	7302	0	0	0
T142	1174	0	0	0
T155	4208	0	0	0
T159	29697	0	0	0
T160	1158	0	0	0
T168	0	1	0	0
T170	0	1	0	0
T171	0	2	0	0
T172	0	2	0	0
T173	0	2	0	0
T174	0	4	0	0
T175	2140	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T47,T48,T49
1	0	Covered	T7,T10,T11
1	1	Covered	T7,T10,T11

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	55900042	4862	0	0
CgEnOn_A	55900042	2794	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55900042	4862	0	0
T7	4804	1	0	0
T8	41470	1	0	0
T10	1430	1	0	0
T11	505	2	0	0
T28	697	1	0	0
T29	795	1	0	0
T30	470	4	0	0
T31	1965	1	0	0
T32	1626	2	0	0
T33	607	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55900042	2794	0	0
T8	41470	0	0	0
T11	505	1	0	0
T21	0	5	0	0
T22	0	1	0	0
T25	0	16	0	0
T28	697	0	0	0
T29	795	0	0	0
T30	470	3	0	0
T31	1965	0	0	0
T32	1626	1	0	0
T33	607	0	0	0
T42	390	0	0	0
T46	0	1	0	0
T50	871	0	0	0
T101	0	3	0	0
T158	0	5	0	0
T163	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T47,T48,T49
1	0	Covered	T7,T10,T11
1	1	Covered	T7,T10,T11

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	111800817	4908	0	0
CgEnOn_A	111800817	2840	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111800817	4908	0	0
T7	9608	1	0	0
T8	82941	1	0	0
T10	2862	1	0	0
T11	1010	2	0	0
T28	1396	1	0	0
T29	1592	1	0	0
T30	939	3	0	0
T31	3930	1	0	0
T32	3252	2	0	0
T33	1215	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111800817	2840	0	0
T8	82941	0	0	0
T11	1010	1	0	0
T21	0	6	0	0
T22	0	1	0	0
T25	0	12	0	0
T28	1396	0	0	0
T29	1592	0	0	0
T30	939	2	0	0
T31	3930	0	0	0
T32	3252	1	0	0
T33	1215	0	0	0
T42	779	0	0	0
T46	0	1	0	0
T50	1744	0	0	0
T101	0	5	0	0
T158	0	5	0	0
T163	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T47,T48,T49
1	0	Covered	T7,T10,T11
1	1	Covered	T7,T10,T11

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	225073845	4881	0	0
CgEnOn_A	225073845	2810	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225073845	4881	0	0
T7	19267	1	0	0
T8	165920	1	0	0
T10	5004	1	0	0
T11	2114	2	0	0
T28	2612	1	0	0
T29	2905	1	0	0
T30	1958	3	0	0
T31	7253	1	0	0
T32	6597	2	0	0
T33	2395	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225073845	2810	0	0
T8	165920	0	0	0
T11	2114	1	0	0
T21	0	6	0	0
T22	0	1	0	0
T25	0	14	0	0
T28	2612	0	0	0
T29	2905	0	0	0
T30	1958	2	0	0
T31	7253	0	0	0
T32	6597	1	0	0
T33	2395	0	0	0
T42	1597	0	0	0
T46	0	1	0	0
T50	3509	0	0	0
T101	0	4	0	0
T158	0	4	0	0
T163	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T47,T48,T49
1	0	Covered	T7,T10,T11
1	1	Covered	T7,T10,T11

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	115245515	4859	0	0
CgEnOn_A	115245515	2787	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115245515	4859	0	0
T7	9633	1	0	0
T8	120403	1	0	0
T10	2501	1	0	0
T11	1057	2	0	0
T28	1305	1	0	0
T29	1453	1	0	0
T30	979	3	0	0
T31	3626	1	0	0
T32	3299	2	0	0
T33	1197	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115245515	2787	0	0
T8	120403	0	0	0
T11	1057	1	0	0
T21	0	6	0	0
T22	0	1	0	0
T25	0	13	0	0
T28	1305	0	0	0
T29	1453	0	0	0
T30	979	2	0	0
T31	3626	0	0	0
T32	3299	1	0	0
T33	1197	0	0	0
T42	798	0	0	0
T46	0	1	0	0
T50	1755	0	0	0
T101	0	3	0	0
T158	0	6	0	0
T163	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T11,T32,T46
1	1	Covered	T7,T10,T11

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	240015796	2187	0	0
CgEnOn_A	240015796	2187	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240015796	2187	0	0
T8	238837	0	0	0
T11	2202	1	0	0
T22	0	1	0	0
T23	0	11	0	0
T26	0	1	0	0
T27	0	1	0	0
T28	2720	0	0	0
T29	3025	0	0	0
T30	2040	0	0	0
T31	7556	0	0	0
T32	6873	1	0	0
T33	2494	0	0	0
T42	1663	0	0	0
T46	0	1	0	0
T50	3656	0	0	0
T98	0	5	0	0
T100	0	7	0	0
T103	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240015796	2187	0	0
T8	238837	0	0	0
T11	2202	1	0	0
T22	0	1	0	0
T23	0	11	0	0
T26	0	1	0	0
T27	0	1	0	0
T28	2720	0	0	0
T29	3025	0	0	0
T30	2040	0	0	0
T31	7556	0	0	0
T32	6873	1	0	0
T33	2494	0	0	0
T42	1663	0	0	0
T46	0	1	0	0
T50	3656	0	0	0
T98	0	5	0	0
T100	0	7	0	0
T103	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T11,T32,T46
1	1	Covered	T7,T10,T11

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	240015796	2261	0	0
CgEnOn_A	240015796	2261	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240015796	2261	0	0
T8	238837	0	0	0
T11	2202	1	0	0
T22	0	1	0	0
T23	0	9	0	0
T26	0	1	0	0
T27	0	1	0	0
T28	2720	0	0	0
T29	3025	0	0	0
T30	2040	0	0	0
T31	7556	0	0	0
T32	6873	1	0	0
T33	2494	0	0	0
T42	1663	0	0	0
T46	0	1	0	0
T50	3656	0	0	0
T98	0	9	0	0
T100	0	5	0	0
T103	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240015796	2261	0	0
T8	238837	0	0	0
T11	2202	1	0	0
T22	0	1	0	0
T23	0	9	0	0
T26	0	1	0	0
T27	0	1	0	0
T28	2720	0	0	0
T29	3025	0	0	0
T30	2040	0	0	0
T31	7556	0	0	0
T32	6873	1	0	0
T33	2494	0	0	0
T42	1663	0	0	0
T46	0	1	0	0
T50	3656	0	0	0
T98	0	9	0	0
T100	0	5	0	0
T103	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T11,T32,T46
1	1	Covered	T7,T10,T11

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	240015796	2164	0	0
CgEnOn_A	240015796	2164	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240015796	2164	0	0
T8	238837	0	0	0
T11	2202	1	0	0
T22	0	1	0	0
T23	0	10	0	0
T26	0	1	0	0
T27	0	1	0	0
T28	2720	0	0	0
T29	3025	0	0	0
T30	2040	0	0	0
T31	7556	0	0	0
T32	6873	1	0	0
T33	2494	0	0	0
T42	1663	0	0	0
T46	0	1	0	0
T50	3656	0	0	0
T98	0	12	0	0
T100	0	10	0	0
T103	0	8	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240015796	2164	0	0
T8	238837	0	0	0
T11	2202	1	0	0
T22	0	1	0	0
T23	0	10	0	0
T26	0	1	0	0
T27	0	1	0	0
T28	2720	0	0	0
T29	3025	0	0	0
T30	2040	0	0	0
T31	7556	0	0	0
T32	6873	1	0	0
T33	2494	0	0	0
T42	1663	0	0	0
T46	0	1	0	0
T50	3656	0	0	0
T98	0	12	0	0
T100	0	10	0	0
T103	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T11,T32,T46
1	1	Covered	T7,T10,T11

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	240015796	2165	0	0
CgEnOn_A	240015796	2165	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240015796	2165	0	0
T8	238837	0	0	0
T11	2202	1	0	0
T22	0	1	0	0
T23	0	12	0	0
T26	0	1	0	0
T27	0	1	0	0
T28	2720	0	0	0
T29	3025	0	0	0
T30	2040	0	0	0
T31	7556	0	0	0
T32	6873	1	0	0
T33	2494	0	0	0
T42	1663	0	0	0
T46	0	1	0	0
T50	3656	0	0	0
T98	0	9	0	0
T100	0	11	0	0
T103	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240015796	2165	0	0
T8	238837	0	0	0
T11	2202	1	0	0
T22	0	1	0	0
T23	0	12	0	0
T26	0	1	0	0
T27	0	1	0	0
T28	2720	0	0	0
T29	3025	0	0	0
T30	2040	0	0	0
T31	7556	0	0	0
T32	6873	1	0	0
T33	2494	0	0	0
T42	1663	0	0	0
T46	0	1	0	0
T50	3656	0	0	0
T98	0	9	0	0
T100	0	11	0	0
T103	0	2	0	0