Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T4 |
1 | 0 | Covered | T6,T7,T4 |
1 | 1 | Covered | T6,T7,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T4 |
1 | 0 | Covered | T6,T7,T4 |
1 | 1 | Covered | T6,T7,T4 |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
Assert Coverage for Module :
prim_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
476854 |
0 |
0 |
T1 |
0 |
334 |
0 |
0 |
T2 |
0 |
1228 |
0 |
0 |
T3 |
0 |
1104 |
0 |
0 |
T4 |
174902 |
70 |
0 |
0 |
T5 |
0 |
196 |
0 |
0 |
T6 |
251136 |
339 |
0 |
0 |
T7 |
240552 |
304 |
0 |
0 |
T18 |
0 |
322 |
0 |
0 |
T24 |
5842 |
0 |
0 |
0 |
T25 |
8612 |
0 |
0 |
0 |
T26 |
33223 |
0 |
0 |
0 |
T27 |
897736 |
934 |
0 |
0 |
T28 |
21551 |
0 |
0 |
0 |
T29 |
56051 |
0 |
0 |
0 |
T30 |
0 |
130 |
0 |
0 |
T35 |
9746 |
0 |
0 |
0 |
T47 |
0 |
15 |
0 |
0 |
T54 |
13340 |
2 |
0 |
0 |
T55 |
4394 |
1 |
0 |
0 |
T59 |
22748 |
1 |
0 |
0 |
T61 |
13068 |
2 |
0 |
0 |
T62 |
7266 |
1 |
0 |
0 |
T63 |
12935 |
0 |
0 |
0 |
T81 |
0 |
208 |
0 |
0 |
T126 |
10220 |
1 |
0 |
0 |
T127 |
29066 |
1 |
0 |
0 |
T128 |
7148 |
2 |
0 |
0 |
T129 |
11248 |
2 |
0 |
0 |
T130 |
15386 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
477648 |
0 |
0 |
T1 |
0 |
334 |
0 |
0 |
T2 |
0 |
1228 |
0 |
0 |
T3 |
0 |
1104 |
0 |
0 |
T4 |
43136 |
70 |
0 |
0 |
T5 |
0 |
196 |
0 |
0 |
T6 |
70598 |
339 |
0 |
0 |
T7 |
67524 |
304 |
0 |
0 |
T18 |
0 |
322 |
0 |
0 |
T24 |
3646 |
0 |
0 |
0 |
T25 |
5052 |
0 |
0 |
0 |
T26 |
9302 |
0 |
0 |
0 |
T27 |
543636 |
934 |
0 |
0 |
T28 |
6885 |
0 |
0 |
0 |
T29 |
13854 |
0 |
0 |
0 |
T30 |
0 |
130 |
0 |
0 |
T35 |
5731 |
0 |
0 |
0 |
T47 |
0 |
15 |
0 |
0 |
T54 |
79306 |
2 |
0 |
0 |
T55 |
29182 |
1 |
0 |
0 |
T59 |
40596 |
1 |
0 |
0 |
T61 |
35348 |
2 |
0 |
0 |
T62 |
6424 |
1 |
0 |
0 |
T63 |
24162 |
0 |
0 |
0 |
T81 |
0 |
208 |
0 |
0 |
T126 |
18774 |
1 |
0 |
0 |
T127 |
27056 |
1 |
0 |
0 |
T128 |
14750 |
2 |
0 |
0 |
T129 |
4646 |
2 |
0 |
0 |
T130 |
6975 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T4 |
1 | 0 | Covered | T6,T7,T4 |
1 | 1 | Covered | T6,T7,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T4 |
1 | 0 | Covered | T6,T7,T4 |
1 | 1 | Covered | T6,T7,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
186696540 |
12491 |
0 |
0 |
T1 |
0 |
26 |
0 |
0 |
T2 |
0 |
72 |
0 |
0 |
T3 |
0 |
72 |
0 |
0 |
T4 |
53774 |
14 |
0 |
0 |
T5 |
0 |
38 |
0 |
0 |
T6 |
62775 |
12 |
0 |
0 |
T7 |
56801 |
12 |
0 |
0 |
T18 |
0 |
18 |
0 |
0 |
T24 |
1208 |
0 |
0 |
0 |
T25 |
1845 |
0 |
0 |
0 |
T26 |
8002 |
0 |
0 |
0 |
T27 |
163406 |
38 |
0 |
0 |
T28 |
5343 |
0 |
0 |
0 |
T29 |
14489 |
0 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T35 |
1997 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
77786784 |
12491 |
0 |
0 |
T1 |
0 |
26 |
0 |
0 |
T2 |
0 |
72 |
0 |
0 |
T3 |
0 |
72 |
0 |
0 |
T4 |
14003 |
14 |
0 |
0 |
T5 |
0 |
38 |
0 |
0 |
T6 |
19347 |
12 |
0 |
0 |
T7 |
19292 |
12 |
0 |
0 |
T18 |
0 |
18 |
0 |
0 |
T24 |
1340 |
0 |
0 |
0 |
T25 |
1827 |
0 |
0 |
0 |
T26 |
1249 |
0 |
0 |
0 |
T27 |
230218 |
38 |
0 |
0 |
T28 |
1335 |
0 |
0 |
0 |
T29 |
1206 |
0 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T35 |
2060 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T4 |
1 | 0 | Covered | T6,T7,T4 |
1 | 1 | Covered | T6,T7,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T4 |
1 | 0 | Covered | T6,T7,T4 |
1 | 1 | Covered | T6,T7,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
186696540 |
18072 |
0 |
0 |
T1 |
0 |
26 |
0 |
0 |
T2 |
0 |
72 |
0 |
0 |
T3 |
0 |
72 |
0 |
0 |
T4 |
53774 |
28 |
0 |
0 |
T5 |
0 |
76 |
0 |
0 |
T6 |
62775 |
12 |
0 |
0 |
T7 |
56801 |
12 |
0 |
0 |
T18 |
0 |
18 |
0 |
0 |
T24 |
1208 |
0 |
0 |
0 |
T25 |
1845 |
0 |
0 |
0 |
T26 |
8002 |
0 |
0 |
0 |
T27 |
163406 |
38 |
0 |
0 |
T28 |
5343 |
0 |
0 |
0 |
T29 |
14489 |
0 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T35 |
1997 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
77786784 |
18087 |
0 |
0 |
T1 |
0 |
26 |
0 |
0 |
T2 |
0 |
72 |
0 |
0 |
T3 |
0 |
72 |
0 |
0 |
T4 |
14003 |
28 |
0 |
0 |
T5 |
0 |
76 |
0 |
0 |
T6 |
19347 |
12 |
0 |
0 |
T7 |
19292 |
12 |
0 |
0 |
T18 |
0 |
18 |
0 |
0 |
T24 |
1340 |
0 |
0 |
0 |
T25 |
1827 |
0 |
0 |
0 |
T26 |
1249 |
0 |
0 |
0 |
T27 |
230218 |
38 |
0 |
0 |
T28 |
1335 |
0 |
0 |
0 |
T29 |
1206 |
0 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T35 |
2060 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T4 |
1 | 0 | Covered | T6,T7,T4 |
1 | 1 | Covered | T6,T7,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T4 |
1 | 0 | Covered | T6,T7,T4 |
1 | 1 | Covered | T6,T7,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
77786784 |
18064 |
0 |
0 |
T1 |
0 |
26 |
0 |
0 |
T2 |
0 |
72 |
0 |
0 |
T3 |
0 |
72 |
0 |
0 |
T4 |
14003 |
28 |
0 |
0 |
T5 |
0 |
76 |
0 |
0 |
T6 |
19347 |
12 |
0 |
0 |
T7 |
19292 |
12 |
0 |
0 |
T18 |
0 |
18 |
0 |
0 |
T24 |
1340 |
0 |
0 |
0 |
T25 |
1827 |
0 |
0 |
0 |
T26 |
1249 |
0 |
0 |
0 |
T27 |
230218 |
38 |
0 |
0 |
T28 |
1335 |
0 |
0 |
0 |
T29 |
1206 |
0 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T35 |
2060 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
186696540 |
18076 |
0 |
0 |
T1 |
0 |
26 |
0 |
0 |
T2 |
0 |
72 |
0 |
0 |
T3 |
0 |
72 |
0 |
0 |
T4 |
53774 |
28 |
0 |
0 |
T5 |
0 |
76 |
0 |
0 |
T6 |
62775 |
12 |
0 |
0 |
T7 |
56801 |
12 |
0 |
0 |
T18 |
0 |
18 |
0 |
0 |
T24 |
1208 |
0 |
0 |
0 |
T25 |
1845 |
0 |
0 |
0 |
T26 |
8002 |
0 |
0 |
0 |
T27 |
163406 |
38 |
0 |
0 |
T28 |
5343 |
0 |
0 |
0 |
T29 |
14489 |
0 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T35 |
1997 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T4 |
1 | 0 | Covered | T6,T7,T4 |
1 | 1 | Covered | T6,T7,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T4 |
1 | 0 | Covered | T6,T7,T4 |
1 | 1 | Covered | T6,T7,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
92583401 |
12491 |
0 |
0 |
T1 |
0 |
26 |
0 |
0 |
T2 |
0 |
72 |
0 |
0 |
T3 |
0 |
72 |
0 |
0 |
T4 |
14602 |
14 |
0 |
0 |
T5 |
0 |
38 |
0 |
0 |
T6 |
31320 |
12 |
0 |
0 |
T7 |
28368 |
12 |
0 |
0 |
T18 |
0 |
18 |
0 |
0 |
T24 |
578 |
0 |
0 |
0 |
T25 |
862 |
0 |
0 |
0 |
T26 |
4468 |
0 |
0 |
0 |
T27 |
81684 |
38 |
0 |
0 |
T28 |
2659 |
0 |
0 |
0 |
T29 |
7218 |
0 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T35 |
1031 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
77786784 |
12491 |
0 |
0 |
T1 |
0 |
26 |
0 |
0 |
T2 |
0 |
72 |
0 |
0 |
T3 |
0 |
72 |
0 |
0 |
T4 |
14003 |
14 |
0 |
0 |
T5 |
0 |
38 |
0 |
0 |
T6 |
19347 |
12 |
0 |
0 |
T7 |
19292 |
12 |
0 |
0 |
T18 |
0 |
18 |
0 |
0 |
T24 |
1340 |
0 |
0 |
0 |
T25 |
1827 |
0 |
0 |
0 |
T26 |
1249 |
0 |
0 |
0 |
T27 |
230218 |
38 |
0 |
0 |
T28 |
1335 |
0 |
0 |
0 |
T29 |
1206 |
0 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T35 |
2060 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T4 |
1 | 0 | Covered | T6,T7,T4 |
1 | 1 | Covered | T6,T7,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T4 |
1 | 0 | Covered | T6,T7,T4 |
1 | 1 | Covered | T6,T7,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
92583401 |
17874 |
0 |
0 |
T1 |
0 |
26 |
0 |
0 |
T2 |
0 |
72 |
0 |
0 |
T3 |
0 |
72 |
0 |
0 |
T4 |
14602 |
28 |
0 |
0 |
T5 |
0 |
76 |
0 |
0 |
T6 |
31320 |
12 |
0 |
0 |
T7 |
28368 |
12 |
0 |
0 |
T18 |
0 |
18 |
0 |
0 |
T24 |
578 |
0 |
0 |
0 |
T25 |
862 |
0 |
0 |
0 |
T26 |
4468 |
0 |
0 |
0 |
T27 |
81684 |
38 |
0 |
0 |
T28 |
2659 |
0 |
0 |
0 |
T29 |
7218 |
0 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T35 |
1031 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
77786784 |
17896 |
0 |
0 |
T1 |
0 |
26 |
0 |
0 |
T2 |
0 |
72 |
0 |
0 |
T3 |
0 |
72 |
0 |
0 |
T4 |
14003 |
28 |
0 |
0 |
T5 |
0 |
76 |
0 |
0 |
T6 |
19347 |
12 |
0 |
0 |
T7 |
19292 |
12 |
0 |
0 |
T18 |
0 |
18 |
0 |
0 |
T24 |
1340 |
0 |
0 |
0 |
T25 |
1827 |
0 |
0 |
0 |
T26 |
1249 |
0 |
0 |
0 |
T27 |
230218 |
38 |
0 |
0 |
T28 |
1335 |
0 |
0 |
0 |
T29 |
1206 |
0 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T35 |
2060 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T4 |
1 | 0 | Covered | T6,T7,T4 |
1 | 1 | Covered | T6,T7,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T4 |
1 | 0 | Covered | T6,T7,T4 |
1 | 1 | Covered | T6,T7,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
77786784 |
17868 |
0 |
0 |
T1 |
0 |
26 |
0 |
0 |
T2 |
0 |
72 |
0 |
0 |
T3 |
0 |
72 |
0 |
0 |
T4 |
14003 |
28 |
0 |
0 |
T5 |
0 |
76 |
0 |
0 |
T6 |
19347 |
12 |
0 |
0 |
T7 |
19292 |
12 |
0 |
0 |
T18 |
0 |
18 |
0 |
0 |
T24 |
1340 |
0 |
0 |
0 |
T25 |
1827 |
0 |
0 |
0 |
T26 |
1249 |
0 |
0 |
0 |
T27 |
230218 |
38 |
0 |
0 |
T28 |
1335 |
0 |
0 |
0 |
T29 |
1206 |
0 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T35 |
2060 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
92583401 |
17875 |
0 |
0 |
T1 |
0 |
26 |
0 |
0 |
T2 |
0 |
72 |
0 |
0 |
T3 |
0 |
72 |
0 |
0 |
T4 |
14602 |
28 |
0 |
0 |
T5 |
0 |
76 |
0 |
0 |
T6 |
31320 |
12 |
0 |
0 |
T7 |
28368 |
12 |
0 |
0 |
T18 |
0 |
18 |
0 |
0 |
T24 |
578 |
0 |
0 |
0 |
T25 |
862 |
0 |
0 |
0 |
T26 |
4468 |
0 |
0 |
0 |
T27 |
81684 |
38 |
0 |
0 |
T28 |
2659 |
0 |
0 |
0 |
T29 |
7218 |
0 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T35 |
1031 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T4 |
1 | 0 | Covered | T6,T7,T4 |
1 | 1 | Covered | T6,T7,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T4 |
1 | 0 | Covered | T6,T7,T4 |
1 | 1 | Covered | T6,T7,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
46291339 |
12491 |
0 |
0 |
T1 |
0 |
26 |
0 |
0 |
T2 |
0 |
72 |
0 |
0 |
T3 |
0 |
72 |
0 |
0 |
T4 |
7303 |
14 |
0 |
0 |
T5 |
0 |
38 |
0 |
0 |
T6 |
15660 |
12 |
0 |
0 |
T7 |
14184 |
12 |
0 |
0 |
T18 |
0 |
18 |
0 |
0 |
T24 |
289 |
0 |
0 |
0 |
T25 |
431 |
0 |
0 |
0 |
T26 |
2232 |
0 |
0 |
0 |
T27 |
40842 |
38 |
0 |
0 |
T28 |
1330 |
0 |
0 |
0 |
T29 |
3609 |
0 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T35 |
515 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
77786784 |
12491 |
0 |
0 |
T1 |
0 |
26 |
0 |
0 |
T2 |
0 |
72 |
0 |
0 |
T3 |
0 |
72 |
0 |
0 |
T4 |
14003 |
14 |
0 |
0 |
T5 |
0 |
38 |
0 |
0 |
T6 |
19347 |
12 |
0 |
0 |
T7 |
19292 |
12 |
0 |
0 |
T18 |
0 |
18 |
0 |
0 |
T24 |
1340 |
0 |
0 |
0 |
T25 |
1827 |
0 |
0 |
0 |
T26 |
1249 |
0 |
0 |
0 |
T27 |
230218 |
38 |
0 |
0 |
T28 |
1335 |
0 |
0 |
0 |
T29 |
1206 |
0 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T35 |
2060 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T4 |
1 | 0 | Covered | T6,T7,T4 |
1 | 1 | Covered | T6,T7,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T4 |
1 | 0 | Covered | T6,T7,T4 |
1 | 1 | Covered | T6,T7,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
46291339 |
17968 |
0 |
0 |
T1 |
0 |
26 |
0 |
0 |
T2 |
0 |
72 |
0 |
0 |
T3 |
0 |
72 |
0 |
0 |
T4 |
7303 |
28 |
0 |
0 |
T5 |
0 |
76 |
0 |
0 |
T6 |
15660 |
12 |
0 |
0 |
T7 |
14184 |
12 |
0 |
0 |
T18 |
0 |
18 |
0 |
0 |
T24 |
289 |
0 |
0 |
0 |
T25 |
431 |
0 |
0 |
0 |
T26 |
2232 |
0 |
0 |
0 |
T27 |
40842 |
38 |
0 |
0 |
T28 |
1330 |
0 |
0 |
0 |
T29 |
3609 |
0 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T35 |
515 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
77786784 |
18007 |
0 |
0 |
T1 |
0 |
26 |
0 |
0 |
T2 |
0 |
72 |
0 |
0 |
T3 |
0 |
72 |
0 |
0 |
T4 |
14003 |
28 |
0 |
0 |
T5 |
0 |
76 |
0 |
0 |
T6 |
19347 |
12 |
0 |
0 |
T7 |
19292 |
12 |
0 |
0 |
T18 |
0 |
18 |
0 |
0 |
T24 |
1340 |
0 |
0 |
0 |
T25 |
1827 |
0 |
0 |
0 |
T26 |
1249 |
0 |
0 |
0 |
T27 |
230218 |
38 |
0 |
0 |
T28 |
1335 |
0 |
0 |
0 |
T29 |
1206 |
0 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T35 |
2060 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T4 |
1 | 0 | Covered | T6,T7,T4 |
1 | 1 | Covered | T6,T7,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T4 |
1 | 0 | Covered | T6,T7,T4 |
1 | 1 | Covered | T6,T7,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
77786784 |
17967 |
0 |
0 |
T1 |
0 |
26 |
0 |
0 |
T2 |
0 |
72 |
0 |
0 |
T3 |
0 |
72 |
0 |
0 |
T4 |
14003 |
28 |
0 |
0 |
T5 |
0 |
76 |
0 |
0 |
T6 |
19347 |
12 |
0 |
0 |
T7 |
19292 |
12 |
0 |
0 |
T18 |
0 |
18 |
0 |
0 |
T24 |
1340 |
0 |
0 |
0 |
T25 |
1827 |
0 |
0 |
0 |
T26 |
1249 |
0 |
0 |
0 |
T27 |
230218 |
38 |
0 |
0 |
T28 |
1335 |
0 |
0 |
0 |
T29 |
1206 |
0 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T35 |
2060 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
46291339 |
17974 |
0 |
0 |
T1 |
0 |
26 |
0 |
0 |
T2 |
0 |
72 |
0 |
0 |
T3 |
0 |
72 |
0 |
0 |
T4 |
7303 |
28 |
0 |
0 |
T5 |
0 |
76 |
0 |
0 |
T6 |
15660 |
12 |
0 |
0 |
T7 |
14184 |
12 |
0 |
0 |
T18 |
0 |
18 |
0 |
0 |
T24 |
289 |
0 |
0 |
0 |
T25 |
431 |
0 |
0 |
0 |
T26 |
2232 |
0 |
0 |
0 |
T27 |
40842 |
38 |
0 |
0 |
T28 |
1330 |
0 |
0 |
0 |
T29 |
3609 |
0 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T35 |
515 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T4 |
1 | 0 | Covered | T6,T7,T4 |
1 | 1 | Covered | T6,T7,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T4 |
1 | 0 | Covered | T6,T7,T4 |
1 | 1 | Covered | T6,T7,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
199441479 |
12491 |
0 |
0 |
T1 |
0 |
26 |
0 |
0 |
T2 |
0 |
72 |
0 |
0 |
T3 |
0 |
72 |
0 |
0 |
T4 |
56016 |
14 |
0 |
0 |
T5 |
0 |
38 |
0 |
0 |
T6 |
59394 |
12 |
0 |
0 |
T7 |
65171 |
12 |
0 |
0 |
T18 |
0 |
18 |
0 |
0 |
T24 |
1271 |
0 |
0 |
0 |
T25 |
1923 |
0 |
0 |
0 |
T26 |
8336 |
0 |
0 |
0 |
T27 |
218218 |
38 |
0 |
0 |
T28 |
5566 |
0 |
0 |
0 |
T29 |
15093 |
0 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T35 |
2081 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
77786784 |
12491 |
0 |
0 |
T1 |
0 |
26 |
0 |
0 |
T2 |
0 |
72 |
0 |
0 |
T3 |
0 |
72 |
0 |
0 |
T4 |
14003 |
14 |
0 |
0 |
T5 |
0 |
38 |
0 |
0 |
T6 |
19347 |
12 |
0 |
0 |
T7 |
19292 |
12 |
0 |
0 |
T18 |
0 |
18 |
0 |
0 |
T24 |
1340 |
0 |
0 |
0 |
T25 |
1827 |
0 |
0 |
0 |
T26 |
1249 |
0 |
0 |
0 |
T27 |
230218 |
38 |
0 |
0 |
T28 |
1335 |
0 |
0 |
0 |
T29 |
1206 |
0 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T35 |
2060 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T4 |
1 | 0 | Covered | T6,T7,T4 |
1 | 1 | Covered | T6,T7,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T4 |
1 | 0 | Covered | T6,T7,T4 |
1 | 1 | Covered | T6,T7,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
199441479 |
17859 |
0 |
0 |
T1 |
0 |
26 |
0 |
0 |
T2 |
0 |
72 |
0 |
0 |
T3 |
0 |
72 |
0 |
0 |
T4 |
56016 |
28 |
0 |
0 |
T5 |
0 |
76 |
0 |
0 |
T6 |
59394 |
12 |
0 |
0 |
T7 |
65171 |
12 |
0 |
0 |
T18 |
0 |
18 |
0 |
0 |
T24 |
1271 |
0 |
0 |
0 |
T25 |
1923 |
0 |
0 |
0 |
T26 |
8336 |
0 |
0 |
0 |
T27 |
218218 |
38 |
0 |
0 |
T28 |
5566 |
0 |
0 |
0 |
T29 |
15093 |
0 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T35 |
2081 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
77786784 |
17870 |
0 |
0 |
T1 |
0 |
26 |
0 |
0 |
T2 |
0 |
72 |
0 |
0 |
T3 |
0 |
72 |
0 |
0 |
T4 |
14003 |
28 |
0 |
0 |
T5 |
0 |
76 |
0 |
0 |
T6 |
19347 |
12 |
0 |
0 |
T7 |
19292 |
12 |
0 |
0 |
T18 |
0 |
18 |
0 |
0 |
T24 |
1340 |
0 |
0 |
0 |
T25 |
1827 |
0 |
0 |
0 |
T26 |
1249 |
0 |
0 |
0 |
T27 |
230218 |
38 |
0 |
0 |
T28 |
1335 |
0 |
0 |
0 |
T29 |
1206 |
0 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T35 |
2060 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T4 |
1 | 0 | Covered | T6,T7,T4 |
1 | 1 | Covered | T6,T7,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T4 |
1 | 0 | Covered | T6,T7,T4 |
1 | 1 | Covered | T6,T7,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
77786784 |
17852 |
0 |
0 |
T1 |
0 |
26 |
0 |
0 |
T2 |
0 |
72 |
0 |
0 |
T3 |
0 |
72 |
0 |
0 |
T4 |
14003 |
28 |
0 |
0 |
T5 |
0 |
76 |
0 |
0 |
T6 |
19347 |
12 |
0 |
0 |
T7 |
19292 |
12 |
0 |
0 |
T18 |
0 |
18 |
0 |
0 |
T24 |
1340 |
0 |
0 |
0 |
T25 |
1827 |
0 |
0 |
0 |
T26 |
1249 |
0 |
0 |
0 |
T27 |
230218 |
38 |
0 |
0 |
T28 |
1335 |
0 |
0 |
0 |
T29 |
1206 |
0 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T35 |
2060 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
199441479 |
17861 |
0 |
0 |
T1 |
0 |
26 |
0 |
0 |
T2 |
0 |
72 |
0 |
0 |
T3 |
0 |
72 |
0 |
0 |
T4 |
56016 |
28 |
0 |
0 |
T5 |
0 |
76 |
0 |
0 |
T6 |
59394 |
12 |
0 |
0 |
T7 |
65171 |
12 |
0 |
0 |
T18 |
0 |
18 |
0 |
0 |
T24 |
1271 |
0 |
0 |
0 |
T25 |
1923 |
0 |
0 |
0 |
T26 |
8336 |
0 |
0 |
0 |
T27 |
218218 |
38 |
0 |
0 |
T28 |
5566 |
0 |
0 |
0 |
T29 |
15093 |
0 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T35 |
2081 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T4 |
1 | 0 | Covered | T6,T7,T4 |
1 | 1 | Covered | T6,T7,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T4 |
1 | 0 | Covered | T6,T7,T4 |
1 | 1 | Covered | T6,T7,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
95765597 |
12081 |
0 |
0 |
T1 |
0 |
26 |
0 |
0 |
T2 |
0 |
72 |
0 |
0 |
T3 |
0 |
72 |
0 |
0 |
T4 |
26888 |
7 |
0 |
0 |
T5 |
0 |
33 |
0 |
0 |
T6 |
37149 |
12 |
0 |
0 |
T7 |
34162 |
12 |
0 |
0 |
T18 |
0 |
18 |
0 |
0 |
T24 |
614 |
0 |
0 |
0 |
T25 |
923 |
0 |
0 |
0 |
T26 |
4001 |
0 |
0 |
0 |
T27 |
107626 |
38 |
0 |
0 |
T28 |
2671 |
0 |
0 |
0 |
T29 |
7244 |
0 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T35 |
998 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
77786784 |
12491 |
0 |
0 |
T1 |
0 |
26 |
0 |
0 |
T2 |
0 |
72 |
0 |
0 |
T3 |
0 |
72 |
0 |
0 |
T4 |
14003 |
14 |
0 |
0 |
T5 |
0 |
38 |
0 |
0 |
T6 |
19347 |
12 |
0 |
0 |
T7 |
19292 |
12 |
0 |
0 |
T18 |
0 |
18 |
0 |
0 |
T24 |
1340 |
0 |
0 |
0 |
T25 |
1827 |
0 |
0 |
0 |
T26 |
1249 |
0 |
0 |
0 |
T27 |
230218 |
38 |
0 |
0 |
T28 |
1335 |
0 |
0 |
0 |
T29 |
1206 |
0 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T35 |
2060 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T4 |
1 | 0 | Covered | T6,T7,T4 |
1 | 1 | Covered | T6,T7,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T4 |
1 | 0 | Covered | T6,T7,T4 |
1 | 1 | Covered | T6,T7,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
95765597 |
17954 |
0 |
0 |
T1 |
0 |
26 |
0 |
0 |
T2 |
0 |
72 |
0 |
0 |
T3 |
0 |
72 |
0 |
0 |
T4 |
26888 |
28 |
0 |
0 |
T5 |
0 |
76 |
0 |
0 |
T6 |
37149 |
12 |
0 |
0 |
T7 |
34162 |
12 |
0 |
0 |
T18 |
0 |
18 |
0 |
0 |
T24 |
614 |
0 |
0 |
0 |
T25 |
923 |
0 |
0 |
0 |
T26 |
4001 |
0 |
0 |
0 |
T27 |
107626 |
38 |
0 |
0 |
T28 |
2671 |
0 |
0 |
0 |
T29 |
7244 |
0 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T35 |
998 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
77786784 |
18060 |
0 |
0 |
T1 |
0 |
26 |
0 |
0 |
T2 |
0 |
72 |
0 |
0 |
T3 |
0 |
72 |
0 |
0 |
T4 |
14003 |
28 |
0 |
0 |
T5 |
0 |
76 |
0 |
0 |
T6 |
19347 |
12 |
0 |
0 |
T7 |
19292 |
12 |
0 |
0 |
T18 |
0 |
18 |
0 |
0 |
T24 |
1340 |
0 |
0 |
0 |
T25 |
1827 |
0 |
0 |
0 |
T26 |
1249 |
0 |
0 |
0 |
T27 |
230218 |
38 |
0 |
0 |
T28 |
1335 |
0 |
0 |
0 |
T29 |
1206 |
0 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T35 |
2060 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T4 |
1 | 0 | Covered | T6,T7,T4 |
1 | 1 | Covered | T6,T7,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T4 |
1 | 0 | Covered | T6,T7,T4 |
1 | 1 | Covered | T6,T7,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
77786784 |
17746 |
0 |
0 |
T1 |
0 |
26 |
0 |
0 |
T2 |
0 |
72 |
0 |
0 |
T3 |
0 |
72 |
0 |
0 |
T4 |
14003 |
21 |
0 |
0 |
T5 |
0 |
76 |
0 |
0 |
T6 |
19347 |
12 |
0 |
0 |
T7 |
19292 |
12 |
0 |
0 |
T18 |
0 |
18 |
0 |
0 |
T24 |
1340 |
0 |
0 |
0 |
T25 |
1827 |
0 |
0 |
0 |
T26 |
1249 |
0 |
0 |
0 |
T27 |
230218 |
38 |
0 |
0 |
T28 |
1335 |
0 |
0 |
0 |
T29 |
1206 |
0 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T35 |
2060 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
95765597 |
17974 |
0 |
0 |
T1 |
0 |
26 |
0 |
0 |
T2 |
0 |
72 |
0 |
0 |
T3 |
0 |
72 |
0 |
0 |
T4 |
26888 |
28 |
0 |
0 |
T5 |
0 |
76 |
0 |
0 |
T6 |
37149 |
12 |
0 |
0 |
T7 |
34162 |
12 |
0 |
0 |
T18 |
0 |
18 |
0 |
0 |
T24 |
614 |
0 |
0 |
0 |
T25 |
923 |
0 |
0 |
0 |
T26 |
4001 |
0 |
0 |
0 |
T27 |
107626 |
38 |
0 |
0 |
T28 |
2671 |
0 |
0 |
0 |
T29 |
7244 |
0 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T35 |
998 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T57,T55,T56 |
1 | 0 | Covered | T57,T55,T56 |
1 | 1 | Covered | T57,T55,T126 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T57,T55,T56 |
1 | 0 | Covered | T57,T55,T126 |
1 | 1 | Covered | T57,T55,T56 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
77786784 |
54 |
0 |
0 |
T55 |
2197 |
2 |
0 |
0 |
T56 |
6261 |
4 |
0 |
0 |
T57 |
4204 |
4 |
0 |
0 |
T59 |
11374 |
2 |
0 |
0 |
T60 |
7441 |
1 |
0 |
0 |
T62 |
3633 |
1 |
0 |
0 |
T126 |
5110 |
4 |
0 |
0 |
T127 |
14533 |
1 |
0 |
0 |
T129 |
11248 |
1 |
0 |
0 |
T131 |
12397 |
4 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
186696540 |
54 |
0 |
0 |
T55 |
30132 |
2 |
0 |
0 |
T56 |
10928 |
4 |
0 |
0 |
T57 |
19216 |
4 |
0 |
0 |
T59 |
41998 |
2 |
0 |
0 |
T60 |
14285 |
1 |
0 |
0 |
T62 |
7119 |
1 |
0 |
0 |
T126 |
20438 |
4 |
0 |
0 |
T127 |
29064 |
1 |
0 |
0 |
T129 |
10797 |
1 |
0 |
0 |
T131 |
49589 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T57,T55,T56 |
1 | 0 | Covered | T57,T55,T56 |
1 | 1 | Covered | T57,T131,T132 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T57,T55,T56 |
1 | 0 | Covered | T57,T131,T132 |
1 | 1 | Covered | T57,T55,T56 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
77786784 |
31 |
0 |
0 |
T55 |
2197 |
1 |
0 |
0 |
T56 |
6261 |
2 |
0 |
0 |
T57 |
4204 |
4 |
0 |
0 |
T59 |
11374 |
1 |
0 |
0 |
T60 |
7441 |
1 |
0 |
0 |
T62 |
3633 |
1 |
0 |
0 |
T129 |
11248 |
1 |
0 |
0 |
T130 |
15386 |
1 |
0 |
0 |
T131 |
12397 |
2 |
0 |
0 |
T133 |
4413 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
186696540 |
31 |
0 |
0 |
T55 |
30132 |
1 |
0 |
0 |
T56 |
10928 |
2 |
0 |
0 |
T57 |
19216 |
4 |
0 |
0 |
T59 |
41998 |
1 |
0 |
0 |
T60 |
14285 |
1 |
0 |
0 |
T62 |
7119 |
1 |
0 |
0 |
T129 |
10797 |
1 |
0 |
0 |
T130 |
15227 |
1 |
0 |
0 |
T131 |
49589 |
2 |
0 |
0 |
T133 |
19257 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T54,T55,T59 |
1 | 0 | Covered | T54,T55,T59 |
1 | 1 | Covered | T129,T134 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T54,T55,T59 |
1 | 0 | Covered | T129,T134 |
1 | 1 | Covered | T54,T55,T59 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
77786784 |
27 |
0 |
0 |
T54 |
6670 |
2 |
0 |
0 |
T55 |
2197 |
1 |
0 |
0 |
T59 |
11374 |
1 |
0 |
0 |
T61 |
6534 |
2 |
0 |
0 |
T62 |
3633 |
1 |
0 |
0 |
T126 |
5110 |
1 |
0 |
0 |
T127 |
14533 |
1 |
0 |
0 |
T128 |
3574 |
2 |
0 |
0 |
T129 |
11248 |
2 |
0 |
0 |
T130 |
15386 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
92583401 |
27 |
0 |
0 |
T54 |
39653 |
2 |
0 |
0 |
T55 |
14591 |
1 |
0 |
0 |
T59 |
20298 |
1 |
0 |
0 |
T61 |
17674 |
2 |
0 |
0 |
T62 |
3212 |
1 |
0 |
0 |
T126 |
9387 |
1 |
0 |
0 |
T127 |
13528 |
1 |
0 |
0 |
T128 |
7375 |
2 |
0 |
0 |
T129 |
4646 |
2 |
0 |
0 |
T130 |
6975 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T54,T55,T59 |
1 | 0 | Covered | T54,T55,T59 |
1 | 1 | Covered | T126,T134 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T54,T55,T59 |
1 | 0 | Covered | T126,T134 |
1 | 1 | Covered | T54,T55,T59 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
77786784 |
27 |
0 |
0 |
T54 |
6670 |
2 |
0 |
0 |
T55 |
2197 |
1 |
0 |
0 |
T59 |
11374 |
1 |
0 |
0 |
T61 |
6534 |
1 |
0 |
0 |
T62 |
3633 |
1 |
0 |
0 |
T63 |
12935 |
1 |
0 |
0 |
T126 |
5110 |
2 |
0 |
0 |
T127 |
14533 |
1 |
0 |
0 |
T128 |
3574 |
1 |
0 |
0 |
T135 |
3191 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
92583401 |
27 |
0 |
0 |
T54 |
39653 |
2 |
0 |
0 |
T55 |
14591 |
1 |
0 |
0 |
T59 |
20298 |
1 |
0 |
0 |
T61 |
17674 |
1 |
0 |
0 |
T62 |
3212 |
1 |
0 |
0 |
T63 |
24162 |
1 |
0 |
0 |
T126 |
9387 |
2 |
0 |
0 |
T127 |
13528 |
1 |
0 |
0 |
T128 |
7375 |
1 |
0 |
0 |
T135 |
6915 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T57,T58,T55 |
1 | 0 | Covered | T57,T58,T55 |
1 | 1 | Covered | T135,T129,T136 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T57,T58,T55 |
1 | 0 | Covered | T135,T129,T136 |
1 | 1 | Covered | T57,T58,T55 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
77786784 |
36 |
0 |
0 |
T55 |
2197 |
2 |
0 |
0 |
T56 |
6261 |
2 |
0 |
0 |
T57 |
4204 |
2 |
0 |
0 |
T58 |
5769 |
1 |
0 |
0 |
T59 |
11374 |
2 |
0 |
0 |
T128 |
3574 |
1 |
0 |
0 |
T129 |
11248 |
2 |
0 |
0 |
T131 |
12397 |
1 |
0 |
0 |
T135 |
3191 |
2 |
0 |
0 |
T137 |
8888 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
46291339 |
36 |
0 |
0 |
T55 |
7295 |
2 |
0 |
0 |
T56 |
2423 |
2 |
0 |
0 |
T57 |
4593 |
2 |
0 |
0 |
T58 |
2844 |
1 |
0 |
0 |
T59 |
10150 |
2 |
0 |
0 |
T128 |
3688 |
1 |
0 |
0 |
T129 |
2322 |
2 |
0 |
0 |
T131 |
12095 |
1 |
0 |
0 |
T135 |
3458 |
2 |
0 |
0 |
T137 |
3023 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T57,T58,T55 |
1 | 0 | Covered | T57,T58,T55 |
1 | 1 | Covered | T56,T128,T136 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T57,T58,T55 |
1 | 0 | Covered | T56,T128,T136 |
1 | 1 | Covered | T57,T58,T55 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
77786784 |
40 |
0 |
0 |
T55 |
2197 |
1 |
0 |
0 |
T56 |
6261 |
3 |
0 |
0 |
T57 |
4204 |
2 |
0 |
0 |
T58 |
5769 |
1 |
0 |
0 |
T59 |
11374 |
2 |
0 |
0 |
T62 |
3633 |
1 |
0 |
0 |
T126 |
5110 |
2 |
0 |
0 |
T128 |
3574 |
2 |
0 |
0 |
T135 |
3191 |
1 |
0 |
0 |
T137 |
8888 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
46291339 |
40 |
0 |
0 |
T55 |
7295 |
1 |
0 |
0 |
T56 |
2423 |
3 |
0 |
0 |
T57 |
4593 |
2 |
0 |
0 |
T58 |
2844 |
1 |
0 |
0 |
T59 |
10150 |
2 |
0 |
0 |
T62 |
1606 |
1 |
0 |
0 |
T126 |
4693 |
2 |
0 |
0 |
T128 |
3688 |
2 |
0 |
0 |
T135 |
3458 |
1 |
0 |
0 |
T137 |
3023 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T57,T58,T56 |
1 | 0 | Covered | T57,T58,T56 |
1 | 1 | Covered | T126,T130,T136 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T57,T58,T56 |
1 | 0 | Covered | T126,T130,T136 |
1 | 1 | Covered | T57,T58,T56 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
77786784 |
30 |
0 |
0 |
T56 |
6261 |
1 |
0 |
0 |
T57 |
4204 |
1 |
0 |
0 |
T58 |
5769 |
1 |
0 |
0 |
T59 |
11374 |
1 |
0 |
0 |
T63 |
12935 |
1 |
0 |
0 |
T126 |
5110 |
4 |
0 |
0 |
T128 |
3574 |
1 |
0 |
0 |
T131 |
12397 |
1 |
0 |
0 |
T138 |
6321 |
1 |
0 |
0 |
T139 |
7888 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
199441479 |
30 |
0 |
0 |
T56 |
11384 |
1 |
0 |
0 |
T57 |
20018 |
1 |
0 |
0 |
T58 |
12820 |
1 |
0 |
0 |
T59 |
43749 |
1 |
0 |
0 |
T63 |
51742 |
1 |
0 |
0 |
T126 |
21291 |
4 |
0 |
0 |
T128 |
16245 |
1 |
0 |
0 |
T131 |
51657 |
1 |
0 |
0 |
T138 |
12901 |
1 |
0 |
0 |
T139 |
8217 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T57,T58,T56 |
1 | 0 | Covered | T57,T58,T56 |
1 | 1 | Covered | T63,T130,T136 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T57,T58,T56 |
1 | 0 | Covered | T63,T130,T136 |
1 | 1 | Covered | T57,T58,T56 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
77786784 |
29 |
0 |
0 |
T56 |
6261 |
2 |
0 |
0 |
T57 |
4204 |
1 |
0 |
0 |
T58 |
5769 |
1 |
0 |
0 |
T59 |
11374 |
1 |
0 |
0 |
T60 |
7441 |
2 |
0 |
0 |
T63 |
12935 |
2 |
0 |
0 |
T126 |
5110 |
1 |
0 |
0 |
T128 |
3574 |
1 |
0 |
0 |
T138 |
6321 |
1 |
0 |
0 |
T139 |
7888 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
199441479 |
29 |
0 |
0 |
T56 |
11384 |
2 |
0 |
0 |
T57 |
20018 |
1 |
0 |
0 |
T58 |
12820 |
1 |
0 |
0 |
T59 |
43749 |
1 |
0 |
0 |
T60 |
14881 |
2 |
0 |
0 |
T63 |
51742 |
2 |
0 |
0 |
T126 |
21291 |
1 |
0 |
0 |
T128 |
16245 |
1 |
0 |
0 |
T138 |
12901 |
1 |
0 |
0 |
T139 |
8217 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T57,T56,T59 |
1 | 0 | Covered | T57,T56,T59 |
1 | 1 | Covered | T62,T129,T140 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T57,T56,T59 |
1 | 0 | Covered | T62,T129,T140 |
1 | 1 | Covered | T57,T56,T59 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
77786784 |
25 |
0 |
0 |
T56 |
6261 |
1 |
0 |
0 |
T57 |
4204 |
1 |
0 |
0 |
T59 |
11374 |
1 |
0 |
0 |
T61 |
6534 |
1 |
0 |
0 |
T62 |
3633 |
2 |
0 |
0 |
T127 |
14533 |
1 |
0 |
0 |
T128 |
3574 |
1 |
0 |
0 |
T129 |
11248 |
2 |
0 |
0 |
T133 |
4413 |
2 |
0 |
0 |
T136 |
10948 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
95765597 |
25 |
0 |
0 |
T56 |
5464 |
1 |
0 |
0 |
T57 |
9609 |
1 |
0 |
0 |
T59 |
20999 |
1 |
0 |
0 |
T61 |
18451 |
1 |
0 |
0 |
T62 |
3560 |
2 |
0 |
0 |
T127 |
14533 |
1 |
0 |
0 |
T128 |
7798 |
1 |
0 |
0 |
T129 |
5398 |
2 |
0 |
0 |
T133 |
9629 |
2 |
0 |
0 |
T136 |
5255 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T57,T56,T61 |
1 | 0 | Covered | T57,T56,T61 |
1 | 1 | Covered | T128,T129,T140 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T57,T56,T61 |
1 | 0 | Covered | T128,T129,T140 |
1 | 1 | Covered | T57,T56,T61 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
77786784 |
30 |
0 |
0 |
T56 |
6261 |
1 |
0 |
0 |
T57 |
4204 |
2 |
0 |
0 |
T61 |
6534 |
2 |
0 |
0 |
T62 |
3633 |
1 |
0 |
0 |
T127 |
14533 |
1 |
0 |
0 |
T128 |
3574 |
2 |
0 |
0 |
T129 |
11248 |
3 |
0 |
0 |
T132 |
3848 |
1 |
0 |
0 |
T133 |
4413 |
1 |
0 |
0 |
T141 |
5701 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
95765597 |
30 |
0 |
0 |
T56 |
5464 |
1 |
0 |
0 |
T57 |
9609 |
2 |
0 |
0 |
T61 |
18451 |
2 |
0 |
0 |
T62 |
3560 |
1 |
0 |
0 |
T127 |
14533 |
1 |
0 |
0 |
T128 |
7798 |
2 |
0 |
0 |
T129 |
5398 |
3 |
0 |
0 |
T132 |
7389 |
1 |
0 |
0 |
T133 |
9629 |
1 |
0 |
0 |
T141 |
7397 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T27 |
1 | 0 | Covered | T6,T7,T27 |
1 | 1 | Covered | T6,T7,T27 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T27 |
1 | 0 | Covered | T6,T7,T27 |
1 | 1 | Covered | T6,T7,T27 |
Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
183819188 |
43993 |
0 |
0 |
T1 |
0 |
64 |
0 |
0 |
T2 |
0 |
241 |
0 |
0 |
T3 |
0 |
213 |
0 |
0 |
T4 |
53774 |
0 |
0 |
0 |
T5 |
0 |
1 |
0 |
0 |
T6 |
62775 |
79 |
0 |
0 |
T7 |
56801 |
64 |
0 |
0 |
T18 |
0 |
52 |
0 |
0 |
T24 |
1208 |
0 |
0 |
0 |
T25 |
1845 |
0 |
0 |
0 |
T26 |
8002 |
0 |
0 |
0 |
T27 |
163406 |
181 |
0 |
0 |
T28 |
5343 |
0 |
0 |
0 |
T29 |
14489 |
0 |
0 |
0 |
T30 |
0 |
22 |
0 |
0 |
T35 |
1997 |
0 |
0 |
0 |
T81 |
0 |
52 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6904909 |
43985 |
0 |
0 |
T1 |
0 |
64 |
0 |
0 |
T2 |
0 |
241 |
0 |
0 |
T3 |
0 |
213 |
0 |
0 |
T4 |
132 |
0 |
0 |
0 |
T5 |
0 |
1 |
0 |
0 |
T6 |
149 |
79 |
0 |
0 |
T7 |
140 |
64 |
0 |
0 |
T18 |
0 |
52 |
0 |
0 |
T24 |
97 |
0 |
0 |
0 |
T25 |
134 |
0 |
0 |
0 |
T26 |
584 |
0 |
0 |
0 |
T27 |
355 |
181 |
0 |
0 |
T28 |
389 |
0 |
0 |
0 |
T29 |
1056 |
0 |
0 |
0 |
T30 |
0 |
22 |
0 |
0 |
T35 |
145 |
0 |
0 |
0 |
T81 |
0 |
52 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T27 |
1 | 0 | Covered | T6,T7,T27 |
1 | 1 | Covered | T6,T7,T27 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T27 |
1 | 0 | Covered | T6,T7,T27 |
1 | 1 | Covered | T6,T7,T27 |
Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
91188387 |
43743 |
0 |
0 |
T1 |
0 |
64 |
0 |
0 |
T2 |
0 |
241 |
0 |
0 |
T3 |
0 |
213 |
0 |
0 |
T4 |
14602 |
0 |
0 |
0 |
T5 |
0 |
4 |
0 |
0 |
T6 |
31320 |
79 |
0 |
0 |
T7 |
28368 |
64 |
0 |
0 |
T18 |
0 |
52 |
0 |
0 |
T24 |
578 |
0 |
0 |
0 |
T25 |
862 |
0 |
0 |
0 |
T26 |
4468 |
0 |
0 |
0 |
T27 |
81684 |
181 |
0 |
0 |
T28 |
2659 |
0 |
0 |
0 |
T29 |
7218 |
0 |
0 |
0 |
T30 |
0 |
22 |
0 |
0 |
T35 |
1031 |
0 |
0 |
0 |
T81 |
0 |
52 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6904909 |
43736 |
0 |
0 |
T1 |
0 |
64 |
0 |
0 |
T2 |
0 |
241 |
0 |
0 |
T3 |
0 |
213 |
0 |
0 |
T4 |
132 |
0 |
0 |
0 |
T5 |
0 |
4 |
0 |
0 |
T6 |
149 |
79 |
0 |
0 |
T7 |
140 |
64 |
0 |
0 |
T18 |
0 |
52 |
0 |
0 |
T24 |
97 |
0 |
0 |
0 |
T25 |
134 |
0 |
0 |
0 |
T26 |
584 |
0 |
0 |
0 |
T27 |
355 |
181 |
0 |
0 |
T28 |
389 |
0 |
0 |
0 |
T29 |
1056 |
0 |
0 |
0 |
T30 |
0 |
22 |
0 |
0 |
T35 |
145 |
0 |
0 |
0 |
T81 |
0 |
52 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T27 |
1 | 0 | Covered | T6,T7,T27 |
1 | 1 | Covered | T6,T7,T27 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T27 |
1 | 0 | Covered | T6,T7,T27 |
1 | 1 | Covered | T6,T7,T27 |
Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
45593821 |
43233 |
0 |
0 |
T1 |
0 |
64 |
0 |
0 |
T2 |
0 |
241 |
0 |
0 |
T3 |
0 |
213 |
0 |
0 |
T4 |
7303 |
0 |
0 |
0 |
T5 |
0 |
1 |
0 |
0 |
T6 |
15660 |
79 |
0 |
0 |
T7 |
14184 |
64 |
0 |
0 |
T18 |
0 |
52 |
0 |
0 |
T24 |
289 |
0 |
0 |
0 |
T25 |
431 |
0 |
0 |
0 |
T26 |
2232 |
0 |
0 |
0 |
T27 |
40842 |
181 |
0 |
0 |
T28 |
1330 |
0 |
0 |
0 |
T29 |
3609 |
0 |
0 |
0 |
T30 |
0 |
22 |
0 |
0 |
T35 |
515 |
0 |
0 |
0 |
T81 |
0 |
52 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6904909 |
43227 |
0 |
0 |
T1 |
0 |
64 |
0 |
0 |
T2 |
0 |
241 |
0 |
0 |
T3 |
0 |
213 |
0 |
0 |
T4 |
132 |
0 |
0 |
0 |
T5 |
0 |
1 |
0 |
0 |
T6 |
149 |
79 |
0 |
0 |
T7 |
140 |
64 |
0 |
0 |
T18 |
0 |
52 |
0 |
0 |
T24 |
97 |
0 |
0 |
0 |
T25 |
134 |
0 |
0 |
0 |
T26 |
584 |
0 |
0 |
0 |
T27 |
355 |
181 |
0 |
0 |
T28 |
389 |
0 |
0 |
0 |
T29 |
1056 |
0 |
0 |
0 |
T30 |
0 |
22 |
0 |
0 |
T35 |
145 |
0 |
0 |
0 |
T81 |
0 |
52 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T27 |
1 | 0 | Covered | T6,T7,T27 |
1 | 1 | Covered | T6,T7,T27 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T27 |
1 | 0 | Covered | T6,T7,T27 |
1 | 1 | Covered | T6,T7,T27 |
Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
196444110 |
52438 |
0 |
0 |
T1 |
0 |
64 |
0 |
0 |
T2 |
0 |
289 |
0 |
0 |
T3 |
0 |
249 |
0 |
0 |
T4 |
56016 |
0 |
0 |
0 |
T6 |
59394 |
66 |
0 |
0 |
T7 |
65171 |
76 |
0 |
0 |
T18 |
0 |
112 |
0 |
0 |
T24 |
1271 |
0 |
0 |
0 |
T25 |
1923 |
0 |
0 |
0 |
T26 |
8336 |
0 |
0 |
0 |
T27 |
218218 |
277 |
0 |
0 |
T28 |
5566 |
0 |
0 |
0 |
T29 |
15093 |
0 |
0 |
0 |
T30 |
0 |
46 |
0 |
0 |
T35 |
2081 |
0 |
0 |
0 |
T47 |
0 |
15 |
0 |
0 |
T81 |
0 |
52 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6917126 |
52422 |
0 |
0 |
T1 |
0 |
64 |
0 |
0 |
T2 |
0 |
289 |
0 |
0 |
T3 |
0 |
249 |
0 |
0 |
T4 |
132 |
0 |
0 |
0 |
T6 |
137 |
66 |
0 |
0 |
T7 |
152 |
76 |
0 |
0 |
T18 |
0 |
112 |
0 |
0 |
T24 |
97 |
0 |
0 |
0 |
T25 |
134 |
0 |
0 |
0 |
T26 |
584 |
0 |
0 |
0 |
T27 |
451 |
277 |
0 |
0 |
T28 |
389 |
0 |
0 |
0 |
T29 |
1056 |
0 |
0 |
0 |
T30 |
0 |
46 |
0 |
0 |
T35 |
145 |
0 |
0 |
0 |
T47 |
0 |
15 |
0 |
0 |
T81 |
0 |
52 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T27 |
1 | 0 | Covered | T6,T7,T27 |
1 | 1 | Covered | T6,T7,T27 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T9,T6 |
0 | 1 | Covered | T6,T7,T27 |
1 | 0 | Covered | T6,T7,T27 |
1 | 1 | Covered | T6,T7,T27 |
Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T9,T6 |
0 |
Covered |
T8,T9,T6 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
94326879 |
51849 |
0 |
0 |
T1 |
0 |
64 |
0 |
0 |
T2 |
0 |
265 |
0 |
0 |
T3 |
0 |
237 |
0 |
0 |
T4 |
26888 |
0 |
0 |
0 |
T6 |
37149 |
98 |
0 |
0 |
T7 |
34162 |
86 |
0 |
0 |
T18 |
0 |
124 |
0 |
0 |
T24 |
614 |
0 |
0 |
0 |
T25 |
923 |
0 |
0 |
0 |
T26 |
4001 |
0 |
0 |
0 |
T27 |
107626 |
289 |
0 |
0 |
T28 |
2671 |
0 |
0 |
0 |
T29 |
7244 |
0 |
0 |
0 |
T30 |
0 |
46 |
0 |
0 |
T35 |
998 |
0 |
0 |
0 |
T47 |
0 |
15 |
0 |
0 |
T81 |
0 |
52 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6918710 |
51814 |
0 |
0 |
T1 |
0 |
64 |
0 |
0 |
T2 |
0 |
265 |
0 |
0 |
T3 |
0 |
237 |
0 |
0 |
T4 |
132 |
0 |
0 |
0 |
T6 |
173 |
98 |
0 |
0 |
T7 |
164 |
86 |
0 |
0 |
T18 |
0 |
124 |
0 |
0 |
T24 |
97 |
0 |
0 |
0 |
T25 |
134 |
0 |
0 |
0 |
T26 |
584 |
0 |
0 |
0 |
T27 |
463 |
289 |
0 |
0 |
T28 |
389 |
0 |
0 |
0 |
T29 |
1056 |
0 |
0 |
0 |
T30 |
0 |
46 |
0 |
0 |
T35 |
145 |
0 |
0 |
0 |
T47 |
0 |
15 |
0 |
0 |
T81 |
0 |
52 |
0 |
0 |