Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T6
0	1	Covered	T4,T5,T36
1	0	Covered	T6,T7,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T6
1	0	Covered	T6,T7,T4
1	1	Covered	T6,T7,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T7,T4
1	1	Covered	T6,T7,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9,T6
0	1	-	Covered	T6,T7,T4
0	0	1	Covered	T6,T7,T4
0	0	0	Covered	T8,T9,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9,T6
0	1	-	Covered	T6,T7,T4
0	0	1	Covered	T6,T7,T4
0	0	0	Covered	T8,T9,T6

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	777867840	773946	0	0
DstReqKnown_A	1241556712	1219858962	0	0
SrcAckBusyChk_A	777867840	151524	0	0
SrcBusyKnown_A	777867840	762099900	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777867840	773946	0	0
T1	0	836	0	0
T2	0	2349	0	0
T3	0	3787	0	0
T4	140030	764	0	0
T5	0	1435	0	0
T6	193470	415	0	0
T7	192920	418	0	0
T18	0	1027	0	0
T24	13400	0	0	0
T25	18270	0	0	0
T26	12490	0	0	0
T27	2302180	3287	0	0
T28	13350	0	0	0
T29	12060	0	0	0
T30	0	218	0	0
T35	20600	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1241556712	1219858962	0	0
T4	317166	49150	0	0
T6	412596	411730	0	0
T7	397372	396226	0	0
T8	16846	15828	0	0
T9	15070	13618	0	0
T24	7920	7022	0	0
T25	11968	10988	0	0
T26	54078	53350	0	0
T27	1223552	1222542	0	0
T28	35138	34648	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777867840	151524	0	0
T1	0	260	0	0
T2	0	720	0	0
T3	0	720	0	0
T4	140030	196	0	0
T5	0	551	0	0
T6	193470	120	0	0
T7	192920	120	0	0
T18	0	180	0	0
T24	13400	0	0	0
T25	18270	0	0	0
T26	12490	0	0	0
T27	2302180	380	0	0
T28	13350	0	0	0
T29	12060	0	0	0
T30	0	60	0	0
T35	20600	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777867840	762099900	0	0
T4	140030	19500	0	0
T6	193470	193060	0	0
T7	192920	192430	0	0
T8	26200	24370	0	0
T9	11570	10350	0	0
T24	13400	11920	0	0
T25	18270	16530	0	0
T26	12490	12290	0	0
T27	2302180	2300490	0	0
T28	13350	13150	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T6
0	1	Unreachable
1	0	Covered	T6,T7,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T6
1	0	Covered	T6,T7,T4
1	1	Covered	T6,T7,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T7,T4
1	1	Covered	T6,T7,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9,T6
0	1	-	Covered	T6,T7,T4
0	0	1	Covered	T6,T7,T4
0	0	0	Covered	T8,T9,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9,T6
0	1	-	Covered	T6,T7,T4
0	0	1	Covered	T6,T7,T4
0	0	0	Covered	T8,T9,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	77786784	43925	0	0
DstReqKnown_A	186696540	182980079	0	0
SrcAckBusyChk_A	77786784	12491	0	0
SrcBusyKnown_A	77786784	76209990	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	43925	0	0
T1	0	64	0	0
T2	0	178	0	0
T3	0	253	0	0
T4	14003	38	0	0
T5	0	87	0	0
T6	19347	31	0	0
T7	19292	30	0	0
T18	0	68	0	0
T24	1340	0	0	0
T25	1827	0	0	0
T26	1249	0	0	0
T27	230218	200	0	0
T28	1335	0	0	0
T29	1206	0	0	0
T30	0	16	0	0
T35	2060	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186696540	182980079	0	0
T4	53774	7464	0	0
T6	62775	62613	0	0
T7	56801	56612	0	0
T8	2516	2340	0	0
T9	2313	2068	0	0
T24	1208	1060	0	0
T25	1845	1669	0	0
T26	8002	7867	0	0
T27	163406	163244	0	0
T28	5343	5263	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	12491	0	0
T1	0	26	0	0
T2	0	72	0	0
T3	0	72	0	0
T4	14003	14	0	0
T5	0	38	0	0
T6	19347	12	0	0
T7	19292	12	0	0
T18	0	18	0	0
T24	1340	0	0	0
T25	1827	0	0	0
T26	1249	0	0	0
T27	230218	38	0	0
T28	1335	0	0	0
T29	1206	0	0	0
T30	0	6	0	0
T35	2060	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	76209990	0	0
T4	14003	1950	0	0
T6	19347	19306	0	0
T7	19292	19243	0	0
T8	2620	2437	0	0
T9	1157	1035	0	0
T24	1340	1192	0	0
T25	1827	1653	0	0
T26	1249	1229	0	0
T27	230218	230049	0	0
T28	1335	1315	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T6
0	1	Unreachable
1	0	Covered	T6,T7,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T6
1	0	Covered	T6,T7,T4
1	1	Covered	T6,T7,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T7,T4
1	1	Covered	T6,T7,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9,T6
0	1	-	Covered	T6,T7,T4
0	0	1	Covered	T6,T7,T4
0	0	0	Covered	T8,T9,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9,T6
0	1	-	Covered	T6,T7,T4
0	0	1	Covered	T6,T7,T4
0	0	0	Covered	T8,T9,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	77786784	63361	0	0
DstReqKnown_A	92583401	91644357	0	0
SrcAckBusyChk_A	77786784	12491	0	0
SrcBusyKnown_A	77786784	76209990	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	63361	0	0
T1	0	87	0	0
T2	0	238	0	0
T3	0	364	0	0
T4	14003	55	0	0
T5	0	87	0	0
T6	19347	43	0	0
T7	19292	44	0	0
T18	0	100	0	0
T24	1340	0	0	0
T25	1827	0	0	0
T26	1249	0	0	0
T27	230218	323	0	0
T28	1335	0	0	0
T29	1206	0	0	0
T30	0	22	0	0
T35	2060	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92583401	91644357	0	0
T4	14602	3733	0	0
T6	31320	31306	0	0
T7	28368	28306	0	0
T8	1354	1312	0	0
T9	1103	1034	0	0
T24	578	530	0	0
T25	862	834	0	0
T26	4468	4454	0	0
T27	81684	81622	0	0
T28	2659	2631	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	12491	0	0
T1	0	26	0	0
T2	0	72	0	0
T3	0	72	0	0
T4	14003	14	0	0
T5	0	38	0	0
T6	19347	12	0	0
T7	19292	12	0	0
T18	0	18	0	0
T24	1340	0	0	0
T25	1827	0	0	0
T26	1249	0	0	0
T27	230218	38	0	0
T28	1335	0	0	0
T29	1206	0	0	0
T30	0	6	0	0
T35	2060	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	76209990	0	0
T4	14003	1950	0	0
T6	19347	19306	0	0
T7	19292	19243	0	0
T8	2620	2437	0	0
T9	1157	1035	0	0
T24	1340	1192	0	0
T25	1827	1653	0	0
T26	1249	1229	0	0
T27	230218	230049	0	0
T28	1335	1315	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T6
0	1	Unreachable
1	0	Covered	T6,T7,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T6
1	0	Covered	T6,T7,T4
1	1	Covered	T6,T7,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T7,T4
1	1	Covered	T6,T7,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9,T6
0	1	-	Covered	T6,T7,T4
0	0	1	Covered	T6,T7,T4
0	0	0	Covered	T8,T9,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9,T6
0	1	-	Covered	T6,T7,T4
0	0	1	Covered	T6,T7,T4
0	0	0	Covered	T8,T9,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	77786784	101453	0	0
DstReqKnown_A	46291339	45821940	0	0
SrcAckBusyChk_A	77786784	12491	0	0
SrcBusyKnown_A	77786784	76209990	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	101453	0	0
T1	0	120	0	0
T2	0	340	0	0
T3	0	584	0	0
T4	14003	77	0	0
T5	0	125	0	0
T6	19347	62	0	0
T7	19292	61	0	0
T18	0	158	0	0
T24	1340	0	0	0
T25	1827	0	0	0
T26	1249	0	0	0
T27	230218	561	0	0
T28	1335	0	0	0
T29	1206	0	0	0
T30	0	32	0	0
T35	2060	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46291339	45821940	0	0
T4	7303	1869	0	0
T6	15660	15653	0	0
T7	14184	14153	0	0
T8	676	655	0	0
T9	552	517	0	0
T24	289	265	0	0
T25	431	417	0	0
T26	2232	2225	0	0
T27	40842	40811	0	0
T28	1330	1316	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	12491	0	0
T1	0	26	0	0
T2	0	72	0	0
T3	0	72	0	0
T4	14003	14	0	0
T5	0	38	0	0
T6	19347	12	0	0
T7	19292	12	0	0
T18	0	18	0	0
T24	1340	0	0	0
T25	1827	0	0	0
T26	1249	0	0	0
T27	230218	38	0	0
T28	1335	0	0	0
T29	1206	0	0	0
T30	0	6	0	0
T35	2060	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	76209990	0	0
T4	14003	1950	0	0
T6	19347	19306	0	0
T7	19292	19243	0	0
T8	2620	2437	0	0
T9	1157	1035	0	0
T24	1340	1192	0	0
T25	1827	1653	0	0
T26	1249	1229	0	0
T27	230218	230049	0	0
T28	1335	1315	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T6
0	1	Unreachable
1	0	Covered	T6,T7,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T6
1	0	Covered	T6,T7,T4
1	1	Covered	T6,T7,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T7,T4
1	1	Covered	T6,T7,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9,T6
0	1	-	Covered	T6,T7,T4
0	0	1	Covered	T6,T7,T4
0	0	0	Covered	T8,T9,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9,T6
0	1	-	Covered	T6,T7,T4
0	0	1	Covered	T6,T7,T4
0	0	0	Covered	T8,T9,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	77786784	43884	0	0
DstReqKnown_A	199441479	195574798	0	0
SrcAckBusyChk_A	77786784	12491	0	0
SrcBusyKnown_A	77786784	76209990	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	43884	0	0
T1	0	64	0	0
T2	0	178	0	0
T3	0	251	0	0
T4	14003	37	0	0
T5	0	87	0	0
T6	19347	30	0	0
T7	19292	30	0	0
T18	0	68	0	0
T24	1340	0	0	0
T25	1827	0	0	0
T26	1249	0	0	0
T27	230218	232	0	0
T28	1335	0	0	0
T29	1206	0	0	0
T30	0	16	0	0
T35	2060	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199441479	195574798	0	0
T4	56016	7776	0	0
T6	59394	59225	0	0
T7	65171	64974	0	0
T8	2620	2437	0	0
T9	2410	2155	0	0
T24	1271	1116	0	0
T25	1923	1739	0	0
T26	8336	8195	0	0
T27	218218	218049	0	0
T28	5566	5482	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	12491	0	0
T1	0	26	0	0
T2	0	72	0	0
T3	0	72	0	0
T4	14003	14	0	0
T5	0	38	0	0
T6	19347	12	0	0
T7	19292	12	0	0
T18	0	18	0	0
T24	1340	0	0	0
T25	1827	0	0	0
T26	1249	0	0	0
T27	230218	38	0	0
T28	1335	0	0	0
T29	1206	0	0	0
T30	0	6	0	0
T35	2060	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	76209990	0	0
T4	14003	1950	0	0
T6	19347	19306	0	0
T7	19292	19243	0	0
T8	2620	2437	0	0
T9	1157	1035	0	0
T24	1340	1192	0	0
T25	1827	1653	0	0
T26	1249	1229	0	0
T27	230218	230049	0	0
T28	1335	1315	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T6
0	1	Unreachable
1	0	Covered	T6,T7,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T6
1	0	Covered	T6,T7,T4
1	1	Covered	T6,T7,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T7,T4
1	1	Covered	T6,T7,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9,T6
0	1	-	Covered	T6,T7,T4
0	0	1	Covered	T6,T7,T4
0	0	0	Covered	T8,T9,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9,T6
0	1	-	Covered	T6,T7,T4
0	0	1	Covered	T6,T7,T4
0	0	0	Covered	T8,T9,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	77786784	62692	0	0
DstReqKnown_A	95765597	93908307	0	0
SrcAckBusyChk_A	77786784	12007	0	0
SrcBusyKnown_A	77786784	76209990	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	62692	0	0
T1	0	87	0	0
T2	0	241	0	0
T3	0	436	0	0
T4	14003	34	0	0
T5	0	63	0	0
T6	19347	43	0	0
T7	19292	43	0	0
T18	0	118	0	0
T24	1340	0	0	0
T25	1827	0	0	0
T26	1249	0	0	0
T27	230218	321	0	0
T28	1335	0	0	0
T29	1206	0	0	0
T30	0	23	0	0
T35	2060	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95765597	93908307	0	0
T4	26888	3733	0	0
T6	37149	37068	0	0
T7	34162	34068	0	0
T8	1257	1170	0	0
T9	1157	1035	0	0
T24	614	540	0	0
T25	923	835	0	0
T26	4001	3934	0	0
T27	107626	107545	0	0
T28	2671	2632	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	12007	0	0
T1	0	26	0	0
T2	0	72	0	0
T3	0	72	0	0
T4	14003	7	0	0
T5	0	19	0	0
T6	19347	12	0	0
T7	19292	12	0	0
T18	0	18	0	0
T24	1340	0	0	0
T25	1827	0	0	0
T26	1249	0	0	0
T27	230218	38	0	0
T28	1335	0	0	0
T29	1206	0	0	0
T30	0	6	0	0
T35	2060	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	76209990	0	0
T4	14003	1950	0	0
T6	19347	19306	0	0
T7	19292	19243	0	0
T8	2620	2437	0	0
T9	1157	1035	0	0
T24	1340	1192	0	0
T25	1827	1653	0	0
T26	1249	1229	0	0
T27	230218	230049	0	0
T28	1335	1315	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T6
0	1	Covered	T4,T5,T36
1	0	Covered	T6,T7,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T6
1	0	Covered	T6,T7,T4
1	1	Covered	T6,T7,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T6
0	1	Unreachable
1	0	Covered	T6,T7,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T7,T4
1	1	Covered	T6,T7,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9,T6
0	1	-	Covered	T6,T7,T4
0	0	1	Covered	T6,T7,T4
0	0	0	Covered	T8,T9,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9,T6
0	1	-	Covered	T6,T7,T4
0	0	1	Covered	T6,T7,T4
0	0	0	Covered	T8,T9,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	77786784	64189	0	0
DstReqKnown_A	186696540	182980079	0	0
SrcAckBusyChk_A	77786784	18066	0	0
SrcBusyKnown_A	77786784	76209990	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	64189	0	0
T1	0	63	0	0
T2	0	177	0	0
T3	0	255	0	0
T4	14003	80	0	0
T5	0	182	0	0
T6	19347	30	0	0
T7	19292	32	0	0
T18	0	68	0	0
T24	1340	0	0	0
T25	1827	0	0	0
T26	1249	0	0	0
T27	230218	200	0	0
T28	1335	0	0	0
T29	1206	0	0	0
T30	0	16	0	0
T35	2060	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186696540	182980079	0	0
T4	53774	7464	0	0
T6	62775	62613	0	0
T7	56801	56612	0	0
T8	2516	2340	0	0
T9	2313	2068	0	0
T24	1208	1060	0	0
T25	1845	1669	0	0
T26	8002	7867	0	0
T27	163406	163244	0	0
T28	5343	5263	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	18066	0	0
T1	0	26	0	0
T2	0	72	0	0
T3	0	72	0	0
T4	14003	28	0	0
T5	0	76	0	0
T6	19347	12	0	0
T7	19292	12	0	0
T18	0	18	0	0
T24	1340	0	0	0
T25	1827	0	0	0
T26	1249	0	0	0
T27	230218	38	0	0
T28	1335	0	0	0
T29	1206	0	0	0
T30	0	6	0	0
T35	2060	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	76209990	0	0
T4	14003	1950	0	0
T6	19347	19306	0	0
T7	19292	19243	0	0
T8	2620	2437	0	0
T9	1157	1035	0	0
T24	1340	1192	0	0
T25	1827	1653	0	0
T26	1249	1229	0	0
T27	230218	230049	0	0
T28	1335	1315	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T6
0	1	Covered	T4,T5,T36
1	0	Covered	T6,T7,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T6
1	0	Covered	T6,T7,T4
1	1	Covered	T6,T7,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T6
0	1	Unreachable
1	0	Covered	T6,T7,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T7,T4
1	1	Covered	T6,T7,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9,T6
0	1	-	Covered	T6,T7,T4
0	0	1	Covered	T6,T7,T4
0	0	0	Covered	T8,T9,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9,T6
0	1	-	Covered	T6,T7,T4
0	0	1	Covered	T6,T7,T4
0	0	0	Covered	T8,T9,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	77786784	91497	0	0
DstReqKnown_A	92583401	91644357	0	0
SrcAckBusyChk_A	77786784	17869	0	0
SrcBusyKnown_A	77786784	76209990	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	91497	0	0
T1	0	84	0	0
T2	0	243	0	0
T3	0	366	0	0
T4	14003	109	0	0
T5	0	182	0	0
T6	19347	43	0	0
T7	19292	44	0	0
T18	0	100	0	0
T24	1340	0	0	0
T25	1827	0	0	0
T26	1249	0	0	0
T27	230218	323	0	0
T28	1335	0	0	0
T29	1206	0	0	0
T30	0	22	0	0
T35	2060	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92583401	91644357	0	0
T4	14602	3733	0	0
T6	31320	31306	0	0
T7	28368	28306	0	0
T8	1354	1312	0	0
T9	1103	1034	0	0
T24	578	530	0	0
T25	862	834	0	0
T26	4468	4454	0	0
T27	81684	81622	0	0
T28	2659	2631	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	17869	0	0
T1	0	26	0	0
T2	0	72	0	0
T3	0	72	0	0
T4	14003	28	0	0
T5	0	76	0	0
T6	19347	12	0	0
T7	19292	12	0	0
T18	0	18	0	0
T24	1340	0	0	0
T25	1827	0	0	0
T26	1249	0	0	0
T27	230218	38	0	0
T28	1335	0	0	0
T29	1206	0	0	0
T30	0	6	0	0
T35	2060	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	76209990	0	0
T4	14003	1950	0	0
T6	19347	19306	0	0
T7	19292	19243	0	0
T8	2620	2437	0	0
T9	1157	1035	0	0
T24	1340	1192	0	0
T25	1827	1653	0	0
T26	1249	1229	0	0
T27	230218	230049	0	0
T28	1335	1315	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T6
0	1	Covered	T4,T5,T36
1	0	Covered	T6,T7,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T6
1	0	Covered	T6,T7,T4
1	1	Covered	T6,T7,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T6
0	1	Unreachable
1	0	Covered	T6,T7,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T7,T4
1	1	Covered	T6,T7,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9,T6
0	1	-	Covered	T6,T7,T4
0	0	1	Covered	T6,T7,T4
0	0	0	Covered	T8,T9,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9,T6
0	1	-	Covered	T6,T7,T4
0	0	1	Covered	T6,T7,T4
0	0	0	Covered	T8,T9,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	77786784	147600	0	0
DstReqKnown_A	46291339	45821940	0	0
SrcAckBusyChk_A	77786784	17967	0	0
SrcBusyKnown_A	77786784	76209990	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	147600	0	0
T1	0	118	0	0
T2	0	335	0	0
T3	0	588	0	0
T4	14003	157	0	0
T5	0	258	0	0
T6	19347	61	0	0
T7	19292	61	0	0
T18	0	161	0	0
T24	1340	0	0	0
T25	1827	0	0	0
T26	1249	0	0	0
T27	230218	571	0	0
T28	1335	0	0	0
T29	1206	0	0	0
T30	0	33	0	0
T35	2060	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46291339	45821940	0	0
T4	7303	1869	0	0
T6	15660	15653	0	0
T7	14184	14153	0	0
T8	676	655	0	0
T9	552	517	0	0
T24	289	265	0	0
T25	431	417	0	0
T26	2232	2225	0	0
T27	40842	40811	0	0
T28	1330	1316	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	17967	0	0
T1	0	26	0	0
T2	0	72	0	0
T3	0	72	0	0
T4	14003	28	0	0
T5	0	76	0	0
T6	19347	12	0	0
T7	19292	12	0	0
T18	0	18	0	0
T24	1340	0	0	0
T25	1827	0	0	0
T26	1249	0	0	0
T27	230218	38	0	0
T28	1335	0	0	0
T29	1206	0	0	0
T30	0	6	0	0
T35	2060	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	76209990	0	0
T4	14003	1950	0	0
T6	19347	19306	0	0
T7	19292	19243	0	0
T8	2620	2437	0	0
T9	1157	1035	0	0
T24	1340	1192	0	0
T25	1827	1653	0	0
T26	1249	1229	0	0
T27	230218	230049	0	0
T28	1335	1315	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T6
0	1	Covered	T4,T5,T36
1	0	Covered	T6,T7,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T6
1	0	Covered	T6,T7,T4
1	1	Covered	T6,T7,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T6
0	1	Unreachable
1	0	Covered	T6,T7,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T7,T4
1	1	Covered	T6,T7,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9,T6
0	1	-	Covered	T6,T7,T4
0	0	1	Covered	T6,T7,T4
0	0	0	Covered	T8,T9,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9,T6
0	1	-	Covered	T6,T7,T4
0	0	1	Covered	T6,T7,T4
0	0	0	Covered	T8,T9,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	77786784	62710	0	0
DstReqKnown_A	199441479	195574798	0	0
SrcAckBusyChk_A	77786784	17854	0	0
SrcBusyKnown_A	77786784	76209990	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	62710	0	0
T1	0	63	0	0
T2	0	177	0	0
T3	0	252	0	0
T4	14003	76	0	0
T5	0	182	0	0
T6	19347	30	0	0
T7	19292	30	0	0
T18	0	68	0	0
T24	1340	0	0	0
T25	1827	0	0	0
T26	1249	0	0	0
T27	230218	232	0	0
T28	1335	0	0	0
T29	1206	0	0	0
T30	0	16	0	0
T35	2060	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199441479	195574798	0	0
T4	56016	7776	0	0
T6	59394	59225	0	0
T7	65171	64974	0	0
T8	2620	2437	0	0
T9	2410	2155	0	0
T24	1271	1116	0	0
T25	1923	1739	0	0
T26	8336	8195	0	0
T27	218218	218049	0	0
T28	5566	5482	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	17854	0	0
T1	0	26	0	0
T2	0	72	0	0
T3	0	72	0	0
T4	14003	28	0	0
T5	0	76	0	0
T6	19347	12	0	0
T7	19292	12	0	0
T18	0	18	0	0
T24	1340	0	0	0
T25	1827	0	0	0
T26	1249	0	0	0
T27	230218	38	0	0
T28	1335	0	0	0
T29	1206	0	0	0
T30	0	6	0	0
T35	2060	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	76209990	0	0
T4	14003	1950	0	0
T6	19347	19306	0	0
T7	19292	19243	0	0
T8	2620	2437	0	0
T9	1157	1035	0	0
T24	1340	1192	0	0
T25	1827	1653	0	0
T26	1249	1229	0	0
T27	230218	230049	0	0
T28	1335	1315	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T6
0	1	Covered	T4,T5,T36
1	0	Covered	T6,T7,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T6
1	0	Covered	T6,T7,T4
1	1	Covered	T6,T7,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T6
0	1	Unreachable
1	0	Covered	T6,T7,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T7,T4
1	1	Covered	T6,T7,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9,T6
0	1	-	Covered	T6,T7,T4
0	0	1	Covered	T6,T7,T4
0	0	0	Covered	T8,T9,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9,T6
0	1	-	Covered	T6,T7,T4
0	0	1	Covered	T6,T7,T4
0	0	0	Covered	T8,T9,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	77786784	92635	0	0
DstReqKnown_A	95765597	93908307	0	0
SrcAckBusyChk_A	77786784	17797	0	0
SrcBusyKnown_A	77786784	76209990	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	92635	0	0
T1	0	86	0	0
T2	0	242	0	0
T3	0	438	0	0
T4	14003	101	0	0
T5	0	182	0	0
T6	19347	42	0	0
T7	19292	43	0	0
T18	0	118	0	0
T24	1340	0	0	0
T25	1827	0	0	0
T26	1249	0	0	0
T27	230218	324	0	0
T28	1335	0	0	0
T29	1206	0	0	0
T30	0	22	0	0
T35	2060	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95765597	93908307	0	0
T4	26888	3733	0	0
T6	37149	37068	0	0
T7	34162	34068	0	0
T8	1257	1170	0	0
T9	1157	1035	0	0
T24	614	540	0	0
T25	923	835	0	0
T26	4001	3934	0	0
T27	107626	107545	0	0
T28	2671	2632	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	17797	0	0
T1	0	26	0	0
T2	0	72	0	0
T3	0	72	0	0
T4	14003	21	0	0
T5	0	76	0	0
T6	19347	12	0	0
T7	19292	12	0	0
T18	0	18	0	0
T24	1340	0	0	0
T25	1827	0	0	0
T26	1249	0	0	0
T27	230218	38	0	0
T28	1335	0	0	0
T29	1206	0	0	0
T30	0	6	0	0
T35	2060	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	76209990	0	0
T4	14003	1950	0	0
T6	19347	19306	0	0
T7	19292	19243	0	0
T8	2620	2437	0	0
T9	1157	1035	0	0
T24	1340	1192	0	0
T25	1827	1653	0	0
T26	1249	1229	0	0
T27	230218	230049	0	0
T28	1335	1315	0	0