Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	459196	0	0
SrcPulseCheck_M	2147483647	459838	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	459196
T1	0	1036
T2	0	3918
T3	0	468
T4	157853	60
T5	661416	796
T6	177727	120
T7	28239	0
T8	32881	0
T9	0	130
T12	0	8149
T13	0	362
T14	0	44
T15	0	12593
T21	0	74
T24	6942	0
T25	7756	0
T26	8124	0
T27	7063	0
T28	9273	0
T29	0	11
T58	6664	4
T60	2275	1
T61	27548	2
T64	27046	3
T65	7240	3
T66	11030	0
T68	14913	1
T114	15638	2
T115	5624	1
T116	14654	0
T117	4173	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	459838
T1	0	1036
T2	0	3918
T3	0	468
T4	94823	60
T5	251311	796
T6	44402	120
T7	8980	0
T8	10048	0
T9	0	130
T12	0	7944
T13	0	362
T14	0	44
T15	0	12593
T21	0	74
T24	4131	0
T25	3574	0
T26	4799	0
T27	4268	0
T28	3868	0
T29	0	11
T58	12722	4
T60	3994	1
T61	12026	2
T64	11534	3
T65	6496	3
T66	4602	0
T68	6887	1
T114	28256	2
T115	11516	1
T116	26212	0
T117	17406	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	327611579	11552	0	0
SrcPulseCheck_M	60995957	11552	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	327611579	11552
T1	0	56
T2	0	182
T3	0	32
T4	41032	12
T5	143527	28
T6	43990	8
T7	6684	0
T8	7870	0
T9	0	26
T12	0	372
T13	0	26
T21	0	14
T24	1453	0
T25	1807	0
T26	1720	0
T27	1505	0
T28	2092	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	60995957	11552
T1	0	56
T2	0	182
T3	0	32
T4	42743	12
T5	87962	28
T6	10997	8
T7	1670	0
T8	1722	0
T9	0	26
T12	0	372
T13	0	26
T21	0	14
T24	1500	0
T25	1055	0
T26	1739	0
T27	1568	0
T28	1068	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	327611579	17467	0	0
SrcPulseCheck_M	60995957	17479	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	327611579	17467
T1	0	56
T2	0	182
T3	0	32
T4	41032	24
T5	143527	28
T6	43990	8
T7	6684	0
T8	7870	0
T9	0	52
T12	0	377
T13	0	26
T21	0	28
T24	1453	0
T25	1807	0
T26	1720	0
T27	1505	0
T28	2092	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	60995957	17479
T1	0	56
T2	0	182
T3	0	32
T4	42743	24
T5	87962	28
T6	10997	8
T7	1670	0
T8	1722	0
T9	0	52
T12	0	377
T13	0	26
T21	0	28
T24	1500	0
T25	1055	0
T26	1739	0
T27	1568	0
T28	1068	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	60995957	17462	0	0
SrcPulseCheck_M	327611579	17468	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	60995957	17462
T1	0	56
T2	0	182
T3	0	32
T4	42743	24
T5	87962	28
T6	10997	8
T7	1670	0
T8	1722	0
T9	0	52
T12	0	377
T13	0	26
T21	0	28
T24	1500	0
T25	1055	0
T26	1739	0
T27	1568	0
T28	1068	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	327611579	17468
T1	0	56
T2	0	182
T3	0	32
T4	41032	24
T5	143527	28
T6	43990	8
T7	6684	0
T8	7870	0
T9	0	52
T12	0	377
T13	0	26
T21	0	28
T24	1453	0
T25	1807	0
T26	1720	0
T27	1505	0
T28	2092	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163046497	11552	0	0
SrcPulseCheck_M	60995957	11552	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163046497	11552
T1	0	56
T2	0	182
T3	0	32
T4	8953	12
T5	71547	28
T6	21976	8
T7	3692	0
T8	4312	0
T9	0	26
T12	0	372
T13	0	26
T21	0	14
T24	707	0
T25	864	0
T26	821	0
T27	692	0
T28	1124	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	60995957	11552
T1	0	56
T2	0	182
T3	0	32
T4	42743	12
T5	87962	28
T6	10997	8
T7	1670	0
T8	1722	0
T9	0	26
T12	0	372
T13	0	26
T21	0	14
T24	1500	0
T25	1055	0
T26	1739	0
T27	1568	0
T28	1068	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163046497	17318	0	0
SrcPulseCheck_M	60995957	17337	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163046497	17318
T1	0	56
T2	0	182
T3	0	32
T4	8953	24
T5	71547	28
T6	21976	8
T7	3692	0
T8	4312	0
T9	0	52
T12	0	377
T13	0	26
T21	0	28
T24	707	0
T25	864	0
T26	821	0
T27	692	0
T28	1124	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	60995957	17337
T1	0	56
T2	0	182
T3	0	32
T4	42743	24
T5	87962	28
T6	10997	8
T7	1670	0
T8	1722	0
T9	0	52
T12	0	377
T13	0	26
T21	0	28
T24	1500	0
T25	1055	0
T26	1739	0
T27	1568	0
T28	1068	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	60995957	17314	0	0
SrcPulseCheck_M	163046497	17319	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	60995957	17314
T1	0	56
T2	0	182
T3	0	32
T4	42743	24
T5	87962	28
T6	10997	8
T7	1670	0
T8	1722	0
T9	0	52
T12	0	377
T13	0	26
T21	0	28
T24	1500	0
T25	1055	0
T26	1739	0
T27	1568	0
T28	1068	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	163046497	17319
T1	0	56
T2	0	182
T3	0	32
T4	8953	24
T5	71547	28
T6	21976	8
T7	3692	0
T8	4312	0
T9	0	52
T12	0	377
T13	0	26
T21	0	28
T24	707	0
T25	864	0
T26	821	0
T27	692	0
T28	1124	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	81522924	11552	0	0
SrcPulseCheck_M	60995957	11552	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	81522924	11552
T1	0	56
T2	0	182
T3	0	32
T4	4476	12
T5	35773	28
T6	10988	8
T7	1846	0
T8	2156	0
T9	0	26
T12	0	372
T13	0	26
T21	0	14
T24	354	0
T25	432	0
T26	410	0
T27	346	0
T28	561	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	60995957	11552
T1	0	56
T2	0	182
T3	0	32
T4	42743	12
T5	87962	28
T6	10997	8
T7	1670	0
T8	1722	0
T9	0	26
T12	0	372
T13	0	26
T21	0	14
T24	1500	0
T25	1055	0
T26	1739	0
T27	1568	0
T28	1068	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	81522924	17346	0	0
SrcPulseCheck_M	60995957	17389	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	81522924	17346
T1	0	56
T2	0	182
T3	0	32
T4	4476	24
T5	35773	28
T6	10988	8
T7	1846	0
T8	2156	0
T9	0	52
T12	0	377
T13	0	26
T21	0	28
T24	354	0
T25	432	0
T26	410	0
T27	346	0
T28	561	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	60995957	17389
T1	0	56
T2	0	182
T3	0	32
T4	42743	24
T5	87962	28
T6	10997	8
T7	1670	0
T8	1722	0
T9	0	52
T12	0	377
T13	0	26
T21	0	28
T24	1500	0
T25	1055	0
T26	1739	0
T27	1568	0
T28	1068	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	60995957	17343	0	0
SrcPulseCheck_M	81522924	17350	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	60995957	17343
T1	0	56
T2	0	182
T3	0	32
T4	42743	24
T5	87962	28
T6	10997	8
T7	1670	0
T8	1722	0
T9	0	52
T12	0	377
T13	0	26
T21	0	28
T24	1500	0
T25	1055	0
T26	1739	0
T27	1568	0
T28	1068	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	81522924	17350
T1	0	56
T2	0	182
T3	0	32
T4	4476	24
T5	35773	28
T6	10988	8
T7	1846	0
T8	2156	0
T9	0	52
T12	0	377
T13	0	26
T21	0	28
T24	354	0
T25	432	0
T26	410	0
T27	346	0
T28	561	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	346015241	11552	0	0
SrcPulseCheck_M	60995957	11552	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	346015241	11552
T1	0	56
T2	0	182
T3	0	32
T4	42743	12
T5	179513	28
T6	45824	8
T7	6963	0
T8	8197	0
T9	0	26
T12	0	372
T13	0	26
T21	0	14
T24	1514	0
T25	1870	0
T26	1792	0
T27	1568	0
T28	2180	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	60995957	11552
T1	0	56
T2	0	182
T3	0	32
T4	42743	12
T5	87962	28
T6	10997	8
T7	1670	0
T8	1722	0
T9	0	26
T12	0	372
T13	0	26
T21	0	14
T24	1500	0
T25	1055	0
T26	1739	0
T27	1568	0
T28	1068	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	346015241	17428	0	0
SrcPulseCheck_M	60995957	17448	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	346015241	17428
T1	0	56
T2	0	182
T3	0	32
T4	42743	24
T5	179513	28
T6	45824	8
T7	6963	0
T8	8197	0
T9	0	52
T12	0	377
T13	0	26
T21	0	28
T24	1514	0
T25	1870	0
T26	1792	0
T27	1568	0
T28	2180	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	60995957	17448
T1	0	56
T2	0	182
T3	0	32
T4	42743	24
T5	87962	28
T6	10997	8
T7	1670	0
T8	1722	0
T9	0	52
T12	0	377
T13	0	26
T21	0	28
T24	1500	0
T25	1055	0
T26	1739	0
T27	1568	0
T28	1068	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	60995957	17422	0	0
SrcPulseCheck_M	346015241	17435	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	60995957	17422
T1	0	56
T2	0	182
T3	0	32
T4	42743	24
T5	87962	28
T6	10997	8
T7	1670	0
T8	1722	0
T9	0	52
T12	0	377
T13	0	26
T21	0	28
T24	1500	0
T25	1055	0
T26	1739	0
T27	1568	0
T28	1068	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	346015241	17435
T1	0	56
T2	0	182
T3	0	32
T4	42743	24
T5	179513	28
T6	45824	8
T7	6963	0
T8	8197	0
T9	0	52
T12	0	377
T13	0	26
T21	0	28
T24	1514	0
T25	1870	0
T26	1792	0
T27	1568	0
T28	2180	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T4,T6

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	166115166	11103	0	0
SrcPulseCheck_M	60995957	11552	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	166115166	11103
T1	0	56
T2	0	182
T3	0	32
T4	20517	6
T5	74648	28
T6	21996	8
T7	3342	0
T8	3935	0
T9	0	13
T12	0	372
T13	0	26
T21	0	14
T24	726	0
T25	850	0
T26	859	0
T27	753	0
T28	1046	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	60995957	11552
T1	0	56
T2	0	182
T3	0	32
T4	42743	12
T5	87962	28
T6	10997	8
T7	1670	0
T8	1722	0
T9	0	26
T12	0	372
T13	0	26
T21	0	14
T24	1500	0
T25	1055	0
T26	1739	0
T27	1568	0
T28	1068	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	166115166	17322	0	0
SrcPulseCheck_M	60995957	17541	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	166115166	17322
T1	0	56
T2	0	182
T3	0	32
T4	20517	18
T5	74648	28
T6	21996	8
T7	3342	0
T8	3935	0
T9	0	39
T12	0	377
T13	0	26
T21	0	28
T24	726	0
T25	850	0
T26	859	0
T27	753	0
T28	1046	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	60995957	17541
T1	0	56
T2	0	182
T3	0	32
T4	42743	24
T5	87962	28
T6	10997	8
T7	1670	0
T8	1722	0
T9	0	52
T12	0	377
T13	0	26
T21	0	28
T24	1500	0
T25	1055	0
T26	1739	0
T27	1568	0
T28	1068	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	60995957	17174	0	0
SrcPulseCheck_M	166115166	17357	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	60995957	17174
T1	0	56
T2	0	182
T3	0	32
T4	42743	18
T5	87962	28
T6	10997	8
T7	1670	0
T8	1722	0
T9	0	39
T12	0	377
T13	0	26
T21	0	28
T24	1500	0
T25	1055	0
T26	1739	0
T27	1568	0
T28	1068	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	166115166	17357
T1	0	56
T2	0	182
T3	0	32
T4	20517	18
T5	74648	28
T6	21996	8
T7	3342	0
T8	3935	0
T9	0	39
T12	0	377
T13	0	26
T21	0	28
T24	726	0
T25	850	0
T26	859	0
T27	753	0
T28	1046	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T57,T58,T61
1	0	Covered	T57,T58,T61
1	1	Covered	T57,T61,T65

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T57,T58,T61
1	0	Covered	T57,T61,T65
1	1	Covered	T57,T58,T61

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	60995957	44	0	0
SrcPulseCheck_M	327611579	44	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	60995957	44
T57	11555	3
T58	3332	2
T61	13774	3
T63	11338	1
T64	13523	2
T65	7240	3
T66	11030	2
T67	6869	1
T114	7819	4
T115	5624	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	327611579	44
T57	46220	3
T58	13330	2
T61	13222	3
T63	45350	1
T64	13523	2
T65	14184	3
T66	11030	2
T67	13188	1
T114	30024	4
T115	24541	1

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T57,T58,T61
1	0	Covered	T57,T58,T61
1	1	Covered	T61,T64,T114

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T57,T58,T61
1	0	Covered	T61,T64,T114
1	1	Covered	T57,T58,T61

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	60995957	36	0	0
SrcPulseCheck_M	327611579	36	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	60995957	36
T57	11555	2
T58	3332	2
T61	13774	2
T63	11338	1
T64	13523	2
T65	7240	2
T67	6869	1
T114	7819	4
T116	7327	1
T118	5592	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	327611579	36
T57	46220	2
T58	13330	2
T61	13222	2
T63	45350	1
T64	13523	2
T65	14184	2
T67	13188	1
T114	30024	4
T116	28135	1
T118	28258	2

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T58,T60,T61
1	0	Covered	T58,T60,T61
1	1	Covered	T58,T65,T64

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T58,T60,T61
1	0	Covered	T58,T65,T64
1	1	Covered	T58,T60,T61

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	60995957	39	0	0
SrcPulseCheck_M	163046497	39	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	60995957	39
T58	3332	4
T60	2275	1
T61	13774	2
T64	13523	3
T65	7240	3
T68	14913	1
T114	7819	2
T115	5624	1
T116	7327	2
T117	4173	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	163046497	39
T58	6361	4
T60	3994	1
T61	6013	2
T64	5767	3
T65	6496	3
T68	6887	1
T114	14128	2
T115	11516	1
T116	13106	2
T117	17406	2

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T58,T61,T64
1	0	Covered	T58,T61,T64
1	1	Covered	T58,T119,T120

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T58,T61,T64
1	0	Covered	T58,T119,T120
1	1	Covered	T58,T61,T64

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	60995957	30	0	0
SrcPulseCheck_M	163046497	30	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	60995957	30
T58	3332	3
T61	13774	1
T64	13523	2
T66	11030	1
T114	7819	2
T116	7327	3
T121	13341	1
T122	10425	1
T123	5120	1
T124	3074	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	163046497	30
T58	6361	3
T61	6013	1
T64	5767	2
T66	4602	1
T114	14128	2
T116	13106	3
T121	24629	1
T122	9881	1
T123	15008	1
T124	11908	2

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T60,T67,T65
1	0	Covered	T60,T67,T65
1	1	Covered	T65,T116,T117

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T60,T67,T65
1	0	Covered	T65,T116,T117
1	1	Covered	T60,T67,T65

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	60995957	37	0	0
SrcPulseCheck_M	81522924	37	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	60995957	37
T60	2275	1
T62	13089	1
T65	7240	4
T66	11030	1
T67	6869	1
T114	7819	2
T116	7327	2
T117	4173	4
T118	5592	1
T122	10425	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	81522924	37
T60	1997	1
T62	2935	1
T65	3249	4
T66	2301	1
T67	3106	1
T114	7063	2
T116	6553	2
T117	8701	4
T118	6883	1
T122	4941	2

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T60,T65,T64
1	0	Covered	T60,T65,T64
1	1	Covered	T65,T125,T126

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T60,T65,T64
1	0	Covered	T65,T125,T126
1	1	Covered	T60,T65,T64

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	60995957	35	0	0
SrcPulseCheck_M	81522924	35	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	60995957	35
T60	2275	1
T64	13523	1
T65	7240	4
T66	11030	1
T114	7819	1
T115	5624	1
T116	7327	2
T117	4173	2
T118	5592	1
T121	13341	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	81522924	35
T60	1997	1
T64	2882	1
T65	3249	4
T66	2301	1
T114	7063	1
T115	5757	1
T116	6553	2
T117	8701	2
T118	6883	1
T121	12311	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T57,T60,T61
1	0	Covered	T57,T60,T61
1	1	Covered	T61,T117,T119

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T57,T60,T61
1	0	Covered	T61,T117,T119
1	1	Covered	T57,T60,T61

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	60995957	27	0	0
SrcPulseCheck_M	346015241	27	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	60995957	27
T57	11555	1
T60	2275	1
T61	13774	3
T63	11338	1
T65	7240	1
T66	11030	1
T116	7327	1
T117	4173	3
T121	13341	1
T122	10425	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	346015241	27
T57	48148	1
T60	9100	1
T61	13774	3
T63	47242	1
T65	14776	1
T66	11491	1
T116	29309	1
T117	37937	3
T121	53364	1
T122	21720	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T57,T58,T60
1	0	Covered	T57,T58,T60
1	1	Covered	T61,T127,T128

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T57,T58,T60
1	0	Covered	T61,T127,T128
1	1	Covered	T57,T58,T60

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	60995957	26	0	0
SrcPulseCheck_M	346015241	26	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	60995957	26
T57	11555	1
T58	3332	1
T60	2275	1
T61	13774	2
T63	11338	1
T116	7327	2
T117	4173	1
T122	10425	1
T129	5883	1
T130	6334	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	346015241	26
T57	48148	1
T58	13887	1
T60	9100	1
T61	13774	2
T63	47242	1
T116	29309	2
T117	37937	1
T122	21720	1
T129	5883	1
T130	26393	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T59,T56,T58
1	0	Covered	T59,T56,T58
1	1	Covered	T58,T68,T62

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T59,T56,T58
1	0	Covered	T58,T68,T62
1	1	Covered	T59,T56,T58

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	60995957	40	0	0
SrcPulseCheck_M	166115166	40	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	60995957	40
T56	8441	1
T58	3332	2
T59	6445	1
T61	13774	2
T62	13089	2
T64	13523	2
T67	6869	1
T68	14913	4
T114	7819	1
T117	4173	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	166115166	40
T56	4453	1
T58	6665	2
T59	6445	1
T61	6612	2
T62	6283	2
T64	6762	2
T67	6594	1
T68	7535	4
T114	15013	1
T117	18210	2

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T59,T56,T58
1	0	Covered	T59,T56,T58
1	1	Covered	T59,T67,T62

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T59,T56,T58
1	0	Covered	T59,T67,T62
1	1	Covered	T59,T56,T58

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	60995957	37	0	0
SrcPulseCheck_M	166115166	37	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	60995957	37
T56	8441	1
T58	3332	1
T59	6445	2
T62	13089	3
T67	6869	2
T68	14913	2
T114	7819	2
T117	4173	2
T121	13341	2
T131	15897	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	166115166	37
T56	4453	1
T58	6665	1
T59	6445	2
T62	6283	3
T67	6594	2
T68	7535	2
T114	15013	2
T117	18210	2
T121	25615	2
T131	8032	1

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T6,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8

Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	324680234	43375	0	0
SrcPulseCheck_M	14124397	43262	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	324680234	43375
T1	0	202
T2	0	856
T3	0	93
T4	41032	0
T5	143527	163
T6	43990	24
T7	6684	0
T8	7870	0
T12	0	1785
T13	0	71
T14	0	11
T15	0	3295
T21	0	1
T24	1453	0
T25	1807	0
T26	1720	0
T27	1505	0
T28	2092	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	14124397	43262
T1	0	202
T2	0	856
T3	0	93
T4	96	0
T5	945	163
T6	108	24
T7	487	0
T8	573	0
T12	0	1715
T13	0	71
T14	0	11
T15	0	3295
T21	0	1
T24	106	0
T25	150	0
T26	125	0
T27	110	0
T28	152	0

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T6,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	161627409	42591	0	0
SrcPulseCheck_M	14124397	42479	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	161627409	42591
T1	0	202
T2	0	856
T3	0	93
T4	8953	0
T5	71547	163
T6	21976	24
T7	3692	0
T8	4312	0
T12	0	1718
T13	0	71
T14	0	11
T15	0	3107
T21	0	1
T24	707	0
T25	864	0
T26	821	0
T27	692	0
T28	1124	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	14124397	42479
T1	0	202
T2	0	856
T3	0	93
T4	96	0
T5	945	163
T6	108	24
T7	487	0
T8	573	0
T12	0	1649
T13	0	71
T14	0	11
T15	0	3107
T21	0	1
T24	106	0
T25	150	0
T26	125	0
T27	110	0
T28	152	0

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T6,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	80813395	41845	0	0
SrcPulseCheck_M	14124397	41736	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	80813395	41845
T1	0	202
T2	0	789
T3	0	93
T4	4476	0
T5	35773	163
T6	10988	24
T7	1846	0
T8	2156	0
T12	0	1634
T13	0	71
T14	0	11
T15	0	2993
T24	354	0
T25	432	0
T26	410	0
T27	346	0
T28	561	0
T29	0	11

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	14124397	41736
T1	0	202
T2	0	789
T3	0	93
T4	96	0
T5	945	163
T6	108	24
T7	487	0
T8	573	0
T12	0	1568
T13	0	71
T14	0	11
T15	0	2993
T24	106	0
T25	150	0
T26	125	0
T27	110	0
T28	152	0
T29	0	11

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T6,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8

Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	342961644	50390	0	0
SrcPulseCheck_M	14137555	50390	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	342961644	50390
T1	0	262
T2	0	871
T3	0	93
T4	42743	0
T5	179513	223
T6	45824	24
T7	6963	0
T8	8197	0
T12	0	1886
T13	0	71
T14	0	11
T15	0	3198
T21	0	2
T24	1514	0
T25	1870	0
T26	1792	0
T27	1568	0
T28	2180	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	14137555	50390
T1	0	262
T2	0	871
T3	0	93
T4	96	0
T5	1005	223
T6	108	24
T7	487	0
T8	573	0
T12	0	1886
T13	0	71
T14	0	11
T15	0	3198
T21	0	2
T24	106	0
T25	150	0
T26	125	0
T27	110	0
T28	152	0

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T6,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T5,T7,T8

Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	164649457	49737	0	0
SrcPulseCheck_M	14137663	49737	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	164649457	49737
T1	0	238
T2	0	824
T3	0	93
T4	20517	0
T5	74648	175
T6	21996	24
T7	3342	0
T8	3935	0
T12	0	1840
T13	0	71
T14	0	11
T15	0	3042
T24	726	0
T25	850	0
T26	859	0
T27	753	0
T28	1046	0
T29	0	11

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	14137663	49737
T1	0	238
T2	0	824
T3	0	93
T4	96	0
T5	957	175
T6	108	24
T7	487	0
T8	573	0
T12	0	1840
T13	0	71
T14	0	11
T15	0	3042
T24	106	0
T25	150	0
T26	125	0
T27	110	0
T28	152	0
T29	0	11

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_io_meas_ctrl_en_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	91.67			100.00	100.00	u_io_meas_ctrl_shadowed_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb