Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T4,T21,T12
1	0	Covered	T5,T4,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T4,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T5,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T5,T7,T8

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	609959570	708441	0	0
DstReqKnown_A	2147483647	2145875034	0	0
SrcAckBusyChk_A	609959570	143993	0	0
SrcBusyKnown_A	609959570	587422660	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609959570	708441	0	0
T1	0	2826	0	0
T2	0	4849	0	0
T3	0	2673	0	0
T4	427430	1473	0	0
T5	879620	1478	0	0
T6	109970	224	0	0
T7	16700	0	0	0
T8	17220	0	0	0
T9	0	3082	0	0
T12	0	10039	0	0
T13	0	1346	0	0
T21	0	507	0	0
T24	15000	0	0	0
T25	10550	0	0	0
T26	17390	0	0	0
T27	15680	0	0	0
T28	10680	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2145875034	0	0
T4	235442	16560	0	0
T5	1010016	1005266	0	0
T6	289548	288900	0	0
T7	45054	44678	0	0
T8	52940	51422	0	0
T24	9508	8592	0	0
T25	11646	10428	0	0
T26	11204	10078	0	0
T27	9728	8394	0	0
T28	14006	13446	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609959570	143993	0	0
T1	0	560	0	0
T2	0	1820	0	0
T3	0	320	0	0
T4	427430	168	0	0
T5	879620	280	0	0
T6	109970	80	0	0
T7	16700	0	0	0
T8	17220	0	0	0
T9	0	364	0	0
T12	0	3745	0	0
T13	0	260	0	0
T21	0	203	0	0
T24	15000	0	0	0
T25	10550	0	0	0
T26	17390	0	0	0
T27	15680	0	0	0
T28	10680	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609959570	587422660	0	0
T4	427430	26230	0	0
T5	879620	875440	0	0
T6	109970	109700	0	0
T7	16700	16540	0	0
T8	17220	16660	0	0
T24	15000	13460	0	0
T25	10550	9520	0	0
T26	17390	15470	0	0
T27	15680	13280	0	0
T28	10680	10210	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Unreachable
1	0	Covered	T5,T4,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T4,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T5,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	60995957	40550	0	0
DstReqKnown_A	327611579	323716145	0	0
SrcAckBusyChk_A	60995957	11552	0	0
SrcBusyKnown_A	60995957	58742266	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	40550	0	0
T1	0	197	0	0
T2	0	448	0	0
T3	0	161	0	0
T4	42743	61	0	0
T5	87962	102	0	0
T6	10997	16	0	0
T7	1670	0	0	0
T8	1722	0	0	0
T9	0	136	0	0
T12	0	922	0	0
T13	0	92	0	0
T21	0	34	0	0
T24	1500	0	0	0
T25	1055	0	0	0
T26	1739	0	0	0
T27	1568	0	0	0
T28	1068	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327611579	323716145	0	0
T4	41032	2514	0	0
T5	143527	142707	0	0
T6	43990	43883	0	0
T7	6684	6618	0	0
T8	7870	7612	0	0
T24	1453	1305	0	0
T25	1807	1604	0	0
T26	1720	1531	0	0
T27	1505	1275	0	0
T28	2092	1999	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	11552	0	0
T1	0	56	0	0
T2	0	182	0	0
T3	0	32	0	0
T4	42743	12	0	0
T5	87962	28	0	0
T6	10997	8	0	0
T7	1670	0	0	0
T8	1722	0	0	0
T9	0	26	0	0
T12	0	372	0	0
T13	0	26	0	0
T21	0	14	0	0
T24	1500	0	0	0
T25	1055	0	0	0
T26	1739	0	0	0
T27	1568	0	0	0
T28	1068	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	58742266	0	0
T4	42743	2623	0	0
T5	87962	87544	0	0
T6	10997	10970	0	0
T7	1670	1654	0	0
T8	1722	1666	0	0
T24	1500	1346	0	0
T25	1055	952	0	0
T26	1739	1547	0	0
T27	1568	1328	0	0
T28	1068	1021	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Unreachable
1	0	Covered	T5,T4,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T4,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T5,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	60995957	56376	0	0
DstReqKnown_A	163046497	162065568	0	0
SrcAckBusyChk_A	60995957	11552	0	0
SrcBusyKnown_A	60995957	58742266	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	56376	0	0
T1	0	283	0	0
T2	0	448	0	0
T3	0	263	0	0
T4	42743	101	0	0
T5	87962	149	0	0
T6	10997	24	0	0
T7	1670	0	0	0
T8	1722	0	0	0
T9	0	219	0	0
T12	0	922	0	0
T13	0	136	0	0
T21	0	34	0	0
T24	1500	0	0	0
T25	1055	0	0	0
T26	1739	0	0	0
T27	1568	0	0	0
T28	1068	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163046497	162065568	0	0
T4	8953	1259	0	0
T5	71547	71353	0	0
T6	21976	21941	0	0
T7	3692	3678	0	0
T8	4312	4243	0	0
T24	707	652	0	0
T25	864	802	0	0
T26	821	766	0	0
T27	692	637	0	0
T28	1124	1096	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	11552	0	0
T1	0	56	0	0
T2	0	182	0	0
T3	0	32	0	0
T4	42743	12	0	0
T5	87962	28	0	0
T6	10997	8	0	0
T7	1670	0	0	0
T8	1722	0	0	0
T9	0	26	0	0
T12	0	372	0	0
T13	0	26	0	0
T21	0	14	0	0
T24	1500	0	0	0
T25	1055	0	0	0
T26	1739	0	0	0
T27	1568	0	0	0
T28	1068	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	58742266	0	0
T4	42743	2623	0	0
T5	87962	87544	0	0
T6	10997	10970	0	0
T7	1670	1654	0	0
T8	1722	1666	0	0
T24	1500	1346	0	0
T25	1055	952	0	0
T26	1739	1547	0	0
T27	1568	1328	0	0
T28	1068	1021	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Unreachable
1	0	Covered	T5,T4,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T4,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T5,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	60995957	89719	0	0
DstReqKnown_A	81522924	81032560	0	0
SrcAckBusyChk_A	60995957	11552	0	0
SrcBusyKnown_A	60995957	58742266	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	89719	0	0
T1	0	455	0	0
T2	0	630	0	0
T3	0	466	0	0
T4	42743	175	0	0
T5	87962	242	0	0
T6	10997	32	0	0
T7	1670	0	0	0
T8	1722	0	0	0
T9	0	389	0	0
T12	0	1294	0	0
T13	0	213	0	0
T21	0	34	0	0
T24	1500	0	0	0
T25	1055	0	0	0
T26	1739	0	0	0
T27	1568	0	0	0
T28	1068	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81522924	81032560	0	0
T4	4476	629	0	0
T5	35773	35676	0	0
T6	10988	10971	0	0
T7	1846	1839	0	0
T8	2156	2122	0	0
T24	354	327	0	0
T25	432	401	0	0
T26	410	382	0	0
T27	346	319	0	0
T28	561	547	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	11552	0	0
T1	0	56	0	0
T2	0	182	0	0
T3	0	32	0	0
T4	42743	12	0	0
T5	87962	28	0	0
T6	10997	8	0	0
T7	1670	0	0	0
T8	1722	0	0	0
T9	0	26	0	0
T12	0	372	0	0
T13	0	26	0	0
T21	0	14	0	0
T24	1500	0	0	0
T25	1055	0	0	0
T26	1739	0	0	0
T27	1568	0	0	0
T28	1068	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	58742266	0	0
T4	42743	2623	0	0
T5	87962	87544	0	0
T6	10997	10970	0	0
T7	1670	1654	0	0
T8	1722	1666	0	0
T24	1500	1346	0	0
T25	1055	952	0	0
T26	1739	1547	0	0
T27	1568	1328	0	0
T28	1068	1021	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Unreachable
1	0	Covered	T5,T4,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T4,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T5,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	60995957	40085	0	0
DstReqKnown_A	346015241	341956278	0	0
SrcAckBusyChk_A	60995957	11552	0	0
SrcBusyKnown_A	60995957	58742266	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	40085	0	0
T1	0	194	0	0
T2	0	448	0	0
T3	0	191	0	0
T4	42743	72	0	0
T5	87962	101	0	0
T6	10997	16	0	0
T7	1670	0	0	0
T8	1722	0	0	0
T9	0	135	0	0
T12	0	922	0	0
T13	0	91	0	0
T21	0	34	0	0
T24	1500	0	0	0
T25	1055	0	0	0
T26	1739	0	0	0
T27	1568	0	0	0
T28	1068	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346015241	341956278	0	0
T4	42743	2623	0	0
T5	179513	178658	0	0
T6	45824	45712	0	0
T7	6963	6895	0	0
T8	8197	7928	0	0
T24	1514	1360	0	0
T25	1870	1658	0	0
T26	1792	1595	0	0
T27	1568	1328	0	0
T28	2180	2082	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	11552	0	0
T1	0	56	0	0
T2	0	182	0	0
T3	0	32	0	0
T4	42743	12	0	0
T5	87962	28	0	0
T6	10997	8	0	0
T7	1670	0	0	0
T8	1722	0	0	0
T9	0	26	0	0
T12	0	372	0	0
T13	0	26	0	0
T21	0	14	0	0
T24	1500	0	0	0
T25	1055	0	0	0
T26	1739	0	0	0
T27	1568	0	0	0
T28	1068	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	58742266	0	0
T4	42743	2623	0	0
T5	87962	87544	0	0
T6	10997	10970	0	0
T7	1670	1654	0	0
T8	1722	1666	0	0
T24	1500	1346	0	0
T25	1055	952	0	0
T26	1739	1547	0	0
T27	1568	1328	0	0
T28	1068	1021	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Unreachable
1	0	Covered	T5,T4,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T4,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T5,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	60995957	53701	0	0
DstReqKnown_A	166115166	164166966	0	0
SrcAckBusyChk_A	60995957	11026	0	0
SrcBusyKnown_A	60995957	58742266	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	53701	0	0
T1	0	281	0	0
T2	0	448	0	0
T3	0	262	0	0
T4	42743	57	0	0
T5	87962	146	0	0
T6	10997	24	0	0
T7	1670	0	0	0
T8	1722	0	0	0
T9	0	127	0	0
T12	0	922	0	0
T13	0	134	0	0
T21	0	26	0	0
T24	1500	0	0	0
T25	1055	0	0	0
T26	1739	0	0	0
T27	1568	0	0	0
T28	1068	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166115166	164166966	0	0
T4	20517	1255	0	0
T5	74648	74239	0	0
T6	21996	21943	0	0
T7	3342	3309	0	0
T8	3935	3806	0	0
T24	726	652	0	0
T25	850	749	0	0
T26	859	765	0	0
T27	753	638	0	0
T28	1046	999	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	11026	0	0
T1	0	56	0	0
T2	0	182	0	0
T3	0	32	0	0
T4	42743	6	0	0
T5	87962	28	0	0
T6	10997	8	0	0
T7	1670	0	0	0
T8	1722	0	0	0
T9	0	13	0	0
T12	0	372	0	0
T13	0	26	0	0
T21	0	7	0	0
T24	1500	0	0	0
T25	1055	0	0	0
T26	1739	0	0	0
T27	1568	0	0	0
T28	1068	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	58742266	0	0
T4	42743	2623	0	0
T5	87962	87544	0	0
T6	10997	10970	0	0
T7	1670	1654	0	0
T8	1722	1666	0	0
T24	1500	1346	0	0
T25	1055	952	0	0
T26	1739	1547	0	0
T27	1568	1328	0	0
T28	1068	1021	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T4,T21,T12
1	0	Covered	T5,T4,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Unreachable
1	0	Covered	T5,T4,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T5,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	60995957	61523	0	0
DstReqKnown_A	327611579	323716145	0	0
SrcAckBusyChk_A	60995957	17462	0	0
SrcBusyKnown_A	60995957	58742266	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	61523	0	0
T1	0	198	0	0
T2	0	449	0	0
T3	0	165	0	0
T4	42743	130	0	0
T5	87962	104	0	0
T6	10997	16	0	0
T7	1670	0	0	0
T8	1722	0	0	0
T9	0	268	0	0
T12	0	936	0	0
T13	0	94	0	0
T21	0	69	0	0
T24	1500	0	0	0
T25	1055	0	0	0
T26	1739	0	0	0
T27	1568	0	0	0
T28	1068	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327611579	323716145	0	0
T4	41032	2514	0	0
T5	143527	142707	0	0
T6	43990	43883	0	0
T7	6684	6618	0	0
T8	7870	7612	0	0
T24	1453	1305	0	0
T25	1807	1604	0	0
T26	1720	1531	0	0
T27	1505	1275	0	0
T28	2092	1999	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	17462	0	0
T1	0	56	0	0
T2	0	182	0	0
T3	0	32	0	0
T4	42743	24	0	0
T5	87962	28	0	0
T6	10997	8	0	0
T7	1670	0	0	0
T8	1722	0	0	0
T9	0	52	0	0
T12	0	377	0	0
T13	0	26	0	0
T21	0	28	0	0
T24	1500	0	0	0
T25	1055	0	0	0
T26	1739	0	0	0
T27	1568	0	0	0
T28	1068	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	58742266	0	0
T4	42743	2623	0	0
T5	87962	87544	0	0
T6	10997	10970	0	0
T7	1670	1654	0	0
T8	1722	1666	0	0
T24	1500	1346	0	0
T25	1055	952	0	0
T26	1739	1547	0	0
T27	1568	1328	0	0
T28	1068	1021	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T4,T21,T12
1	0	Covered	T5,T4,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Unreachable
1	0	Covered	T5,T4,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T5,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	60995957	85157	0	0
DstReqKnown_A	163046497	162065568	0	0
SrcAckBusyChk_A	60995957	17316	0	0
SrcBusyKnown_A	60995957	58742266	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	85157	0	0
T1	0	283	0	0
T2	0	449	0	0
T3	0	261	0	0
T4	42743	199	0	0
T5	87962	147	0	0
T6	10997	24	0	0
T7	1670	0	0	0
T8	1722	0	0	0
T9	0	427	0	0
T12	0	936	0	0
T13	0	136	0	0
T21	0	69	0	0
T24	1500	0	0	0
T25	1055	0	0	0
T26	1739	0	0	0
T27	1568	0	0	0
T28	1068	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163046497	162065568	0	0
T4	8953	1259	0	0
T5	71547	71353	0	0
T6	21976	21941	0	0
T7	3692	3678	0	0
T8	4312	4243	0	0
T24	707	652	0	0
T25	864	802	0	0
T26	821	766	0	0
T27	692	637	0	0
T28	1124	1096	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	17316	0	0
T1	0	56	0	0
T2	0	182	0	0
T3	0	32	0	0
T4	42743	24	0	0
T5	87962	28	0	0
T6	10997	8	0	0
T7	1670	0	0	0
T8	1722	0	0	0
T9	0	52	0	0
T12	0	377	0	0
T13	0	26	0	0
T21	0	28	0	0
T24	1500	0	0	0
T25	1055	0	0	0
T26	1739	0	0	0
T27	1568	0	0	0
T28	1068	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	58742266	0	0
T4	42743	2623	0	0
T5	87962	87544	0	0
T6	10997	10970	0	0
T7	1670	1654	0	0
T8	1722	1666	0	0
T24	1500	1346	0	0
T25	1055	952	0	0
T26	1739	1547	0	0
T27	1568	1328	0	0
T28	1068	1021	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T4,T21,T12
1	0	Covered	T5,T4,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Unreachable
1	0	Covered	T5,T4,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T5,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	60995957	136101	0	0
DstReqKnown_A	81522924	81032560	0	0
SrcAckBusyChk_A	60995957	17345	0	0
SrcBusyKnown_A	60995957	58742266	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	136101	0	0
T1	0	457	0	0
T2	0	631	0	0
T3	0	449	0	0
T4	42743	362	0	0
T5	87962	239	0	0
T6	10997	32	0	0
T7	1670	0	0	0
T8	1722	0	0	0
T9	0	759	0	0
T12	0	1313	0	0
T13	0	221	0	0
T21	0	69	0	0
T24	1500	0	0	0
T25	1055	0	0	0
T26	1739	0	0	0
T27	1568	0	0	0
T28	1068	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81522924	81032560	0	0
T4	4476	629	0	0
T5	35773	35676	0	0
T6	10988	10971	0	0
T7	1846	1839	0	0
T8	2156	2122	0	0
T24	354	327	0	0
T25	432	401	0	0
T26	410	382	0	0
T27	346	319	0	0
T28	561	547	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	17345	0	0
T1	0	56	0	0
T2	0	182	0	0
T3	0	32	0	0
T4	42743	24	0	0
T5	87962	28	0	0
T6	10997	8	0	0
T7	1670	0	0	0
T8	1722	0	0	0
T9	0	52	0	0
T12	0	377	0	0
T13	0	26	0	0
T21	0	28	0	0
T24	1500	0	0	0
T25	1055	0	0	0
T26	1739	0	0	0
T27	1568	0	0	0
T28	1068	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	58742266	0	0
T4	42743	2623	0	0
T5	87962	87544	0	0
T6	10997	10970	0	0
T7	1670	1654	0	0
T8	1722	1666	0	0
T24	1500	1346	0	0
T25	1055	952	0	0
T26	1739	1547	0	0
T27	1568	1328	0	0
T28	1068	1021	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T4,T21,T12
1	0	Covered	T5,T4,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Unreachable
1	0	Covered	T5,T4,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T5,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	60995957	60326	0	0
DstReqKnown_A	346015241	341956278	0	0
SrcAckBusyChk_A	60995957	17423	0	0
SrcBusyKnown_A	60995957	58742266	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	60326	0	0
T1	0	196	0	0
T2	0	449	0	0
T3	0	192	0	0
T4	42743	146	0	0
T5	87962	101	0	0
T6	10997	16	0	0
T7	1670	0	0	0
T8	1722	0	0	0
T9	0	262	0	0
T12	0	936	0	0
T13	0	92	0	0
T21	0	69	0	0
T24	1500	0	0	0
T25	1055	0	0	0
T26	1739	0	0	0
T27	1568	0	0	0
T28	1068	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	346015241	341956278	0	0
T4	42743	2623	0	0
T5	179513	178658	0	0
T6	45824	45712	0	0
T7	6963	6895	0	0
T8	8197	7928	0	0
T24	1514	1360	0	0
T25	1870	1658	0	0
T26	1792	1595	0	0
T27	1568	1328	0	0
T28	2180	2082	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	17423	0	0
T1	0	56	0	0
T2	0	182	0	0
T3	0	32	0	0
T4	42743	24	0	0
T5	87962	28	0	0
T6	10997	8	0	0
T7	1670	0	0	0
T8	1722	0	0	0
T9	0	52	0	0
T12	0	377	0	0
T13	0	26	0	0
T21	0	28	0	0
T24	1500	0	0	0
T25	1055	0	0	0
T26	1739	0	0	0
T27	1568	0	0	0
T28	1068	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	58742266	0	0
T4	42743	2623	0	0
T5	87962	87544	0	0
T6	10997	10970	0	0
T7	1670	1654	0	0
T8	1722	1666	0	0
T24	1500	1346	0	0
T25	1055	952	0	0
T26	1739	1547	0	0
T27	1568	1328	0	0
T28	1068	1021	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T4,T21,T12
1	0	Covered	T5,T4,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Unreachable
1	0	Covered	T5,T4,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T5,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	60995957	84903	0	0
DstReqKnown_A	166115166	164166966	0	0
SrcAckBusyChk_A	60995957	17213	0	0
SrcBusyKnown_A	60995957	58742266	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	84903	0	0
T1	0	282	0	0
T2	0	449	0	0
T3	0	263	0	0
T4	42743	170	0	0
T5	87962	147	0	0
T6	10997	24	0	0
T7	1670	0	0	0
T8	1722	0	0	0
T9	0	360	0	0
T12	0	936	0	0
T13	0	137	0	0
T21	0	69	0	0
T24	1500	0	0	0
T25	1055	0	0	0
T26	1739	0	0	0
T27	1568	0	0	0
T28	1068	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166115166	164166966	0	0
T4	20517	1255	0	0
T5	74648	74239	0	0
T6	21996	21943	0	0
T7	3342	3309	0	0
T8	3935	3806	0	0
T24	726	652	0	0
T25	850	749	0	0
T26	859	765	0	0
T27	753	638	0	0
T28	1046	999	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	17213	0	0
T1	0	56	0	0
T2	0	182	0	0
T3	0	32	0	0
T4	42743	18	0	0
T5	87962	28	0	0
T6	10997	8	0	0
T7	1670	0	0	0
T8	1722	0	0	0
T9	0	39	0	0
T12	0	377	0	0
T13	0	26	0	0
T21	0	28	0	0
T24	1500	0	0	0
T25	1055	0	0	0
T26	1739	0	0	0
T27	1568	0	0	0
T28	1068	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	58742266	0	0
T4	42743	2623	0	0
T5	87962	87544	0	0
T6	10997	10970	0	0
T7	1670	1654	0	0
T8	1722	1666	0	0
T24	1500	1346	0	0
T25	1055	952	0	0
T26	1739	1547	0	0
T27	1568	1328	0	0
T28	1068	1021	0	0