Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	273840	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1195106

1

T5

176

T6

5

T7

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	379099	1			T5	15		T6	6		T7	24
values[0x0]	502595	1			T5	170		T6	8		T7	10
values[0x1]	587252	1			T5	146		T6	5		T7	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	164782	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1304164

1

T5

228

T6

8

T7

24

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6101	1			T7	1		T1	1		T2	179
valid_sources[0x01]	5152	1			T2	183		T19	1		T29	6
valid_sources[0x02]	5497	1			T7	2		T1	5		T2	177
valid_sources[0x03]	5315	1			T1	3		T2	173		T18	1
valid_sources[0x04]	5108	1			T7	1		T1	3		T2	182
valid_sources[0x05]	5490	1			T1	2		T2	170		T20	1
valid_sources[0x06]	5941	1			T1	2		T2	162		T18	1
valid_sources[0x07]	7461	1			T1	2		T17	1		T2	167
valid_sources[0x08]	5184	1			T2	189		T29	2		T3	1
valid_sources[0x09]	5932	1			T1	3		T17	1		T2	204
valid_sources[0x0a]	5388	1			T1	2		T2	163		T29	1
valid_sources[0x0b]	6290	1			T1	3		T17	1		T2	170
valid_sources[0x0c]	5917	1			T1	1		T2	199		T29	3
valid_sources[0x0d]	5213	1			T7	1		T1	2		T2	183
valid_sources[0x0e]	5836	1			T1	2		T2	181		T19	2
valid_sources[0x0f]	5577	1			T7	1		T1	4		T2	194
valid_sources[0x10]	6742	1			T7	1		T1	3		T2	216
valid_sources[0x11]	5788	1			T1	4		T17	2		T2	187
valid_sources[0x12]	5008	1			T7	1		T1	2		T17	2
valid_sources[0x13]	5341	1			T1	1		T2	207		T19	1
valid_sources[0x14]	4920	1			T17	1		T2	180		T3	2
valid_sources[0x15]	6169	1			T2	178		T29	6		T3	2
valid_sources[0x16]	6040	1			T1	2		T2	171		T29	5
valid_sources[0x17]	5639	1			T2	152		T19	1		T29	2
valid_sources[0x18]	9229	1			T2	168		T29	1		T3	4
valid_sources[0x19]	6109	1			T2	186		T19	1		T29	2
valid_sources[0x1a]	7415	1			T2	174		T19	1		T10	3
valid_sources[0x1b]	5431	1			T1	2		T16	1		T2	180
valid_sources[0x1c]	5577	1			T1	1		T2	158		T19	1
valid_sources[0x1d]	5156	1			T7	1		T1	3		T2	174
valid_sources[0x1e]	5774	1			T7	1		T2	159		T28	1
valid_sources[0x1f]	4910	1			T1	4		T2	190		T18	1
valid_sources[0x20]	5929	1			T1	4		T2	176		T28	1
valid_sources[0x21]	5896	1			T1	3		T2	173		T29	5
valid_sources[0x22]	5753	1			T2	182		T29	4		T3	3
valid_sources[0x23]	6336	1			T1	2		T2	161		T3	5
valid_sources[0x24]	6184	1			T4	470		T2	214		T29	3
valid_sources[0x25]	5489	1			T2	184		T29	3		T3	2
valid_sources[0x26]	5700	1			T7	1		T2	166		T29	2
valid_sources[0x27]	5451	1			T2	181		T27	1		T29	14
valid_sources[0x28]	5196	1			T1	1		T2	198		T18	1
valid_sources[0x29]	5016	1			T1	2		T2	161		T29	4
valid_sources[0x2a]	5911	1			T7	1		T1	1		T2	198
valid_sources[0x2b]	6200	1			T1	2		T2	168		T21	1
valid_sources[0x2c]	6320	1			T1	1		T2	172		T19	3
valid_sources[0x2d]	4971	1			T1	1		T17	2		T2	173
valid_sources[0x2e]	4894	1			T1	2		T2	148		T18	1
valid_sources[0x2f]	6204	1			T17	1		T2	158		T19	1
valid_sources[0x30]	5046	1			T1	4		T16	1		T2	170
valid_sources[0x31]	5321	1			T1	2		T2	168		T21	1
valid_sources[0x32]	5769	1			T1	2		T2	163		T19	1
valid_sources[0x33]	5560	1			T1	1		T2	198		T18	1
valid_sources[0x34]	5994	1			T1	2		T2	204		T19	1
valid_sources[0x35]	5491	1			T1	1		T2	177		T29	4
valid_sources[0x36]	6314	1			T1	4		T2	168		T18	1
valid_sources[0x37]	5965	1			T1	2		T2	179		T18	3
valid_sources[0x38]	6012	1			T1	2		T2	174		T19	1
valid_sources[0x39]	5384	1			T17	1		T2	203		T29	3
valid_sources[0x3a]	6080	1			T1	1		T2	192		T29	3
valid_sources[0x3b]	5294	1			T2	188		T28	1		T3	2
valid_sources[0x3c]	5736	1			T1	1		T2	179		T19	1
valid_sources[0x3d]	5875	1			T2	187		T18	1		T29	1
valid_sources[0x3e]	4970	1			T2	221		T29	4		T3	2
valid_sources[0x3f]	5399	1			T1	2		T2	182		T19	1
valid_sources[0x40]	5363	1			T2	176		T29	8		T3	2
valid_sources[0x41]	5696	1			T1	3		T2	159		T18	3
valid_sources[0x42]	5511	1			T1	1		T2	181		T27	1
valid_sources[0x43]	4934	1			T7	1		T1	1		T16	1
valid_sources[0x44]	6295	1			T2	158		T29	9		T3	3
valid_sources[0x45]	5008	1			T2	177		T28	1		T29	5
valid_sources[0x46]	5852	1			T1	1		T2	193		T29	3
valid_sources[0x47]	5410	1			T1	3		T2	197		T19	1
valid_sources[0x48]	5833	1			T6	19		T1	5		T16	1
valid_sources[0x49]	6425	1			T1	2		T2	209		T19	1
valid_sources[0x4a]	5858	1			T1	1		T2	168		T3	3
valid_sources[0x4b]	5007	1			T1	1		T17	1		T2	191
valid_sources[0x4c]	5901	1			T1	2		T2	167		T3	5
valid_sources[0x4d]	6767	1			T1	2		T2	192		T29	4
valid_sources[0x4e]	5403	1			T2	161		T29	2		T85	1
valid_sources[0x4f]	5793	1			T1	3		T17	1		T2	191
valid_sources[0x50]	5812	1			T1	1		T2	173		T19	1
valid_sources[0x51]	5784	1			T1	2		T2	175		T21	1
valid_sources[0x52]	5393	1			T1	3		T2	195		T18	1
valid_sources[0x53]	5269	1			T7	1		T17	1		T2	182
valid_sources[0x54]	5846	1			T1	1		T2	161		T19	1
valid_sources[0x55]	5817	1			T1	1		T2	171		T21	2
valid_sources[0x56]	5164	1			T1	3		T2	172		T20	2
valid_sources[0x57]	6656	1			T1	1		T2	174		T19	1
valid_sources[0x58]	5211	1			T1	1		T2	187		T18	3
valid_sources[0x59]	5698	1			T1	3		T2	181		T29	1
valid_sources[0x5a]	5264	1			T1	2		T2	182		T29	10
valid_sources[0x5b]	6208	1			T1	5		T2	193		T29	3
valid_sources[0x5c]	6070	1			T1	1		T2	190		T19	1
valid_sources[0x5d]	5380	1			T2	161		T19	1		T3	2
valid_sources[0x5e]	5634	1			T7	1		T1	4		T17	2
valid_sources[0x5f]	4996	1			T2	169		T19	1		T20	1
valid_sources[0x60]	5412	1			T1	2		T16	1		T2	187
valid_sources[0x61]	5861	1			T1	1		T2	175		T29	3
valid_sources[0x62]	5437	1			T7	1		T1	2		T17	2
valid_sources[0x63]	5303	1			T7	1		T2	176		T27	1
valid_sources[0x64]	5785	1			T17	1		T2	178		T19	1
valid_sources[0x65]	5487	1			T1	2		T17	1		T2	196
valid_sources[0x66]	4907	1			T2	174		T19	2		T21	1
valid_sources[0x67]	5305	1			T1	5		T2	180		T19	1
valid_sources[0x68]	5052	1			T1	4		T2	186		T19	1
valid_sources[0x69]	6123	1			T1	1		T2	173		T19	1
valid_sources[0x6a]	5256	1			T1	1		T2	198		T19	1
valid_sources[0x6b]	5212	1			T1	2		T2	182		T19	2
valid_sources[0x6c]	5946	1			T7	2		T1	1		T2	195
valid_sources[0x6d]	4937	1			T1	1		T2	176		T19	1
valid_sources[0x6e]	5895	1			T1	1		T2	174		T18	1
valid_sources[0x6f]	5741	1			T1	1		T2	195		T18	3
valid_sources[0x70]	5940	1			T2	188		T20	1		T21	1
valid_sources[0x71]	5194	1			T1	2		T2	186		T18	1
valid_sources[0x72]	6064	1			T1	1		T2	159		T19	1
valid_sources[0x73]	5475	1			T2	166		T19	1		T29	7
valid_sources[0x74]	6330	1			T1	1		T2	164		T21	1
valid_sources[0x75]	5713	1			T2	155		T29	3		T3	5
valid_sources[0x76]	5037	1			T1	1		T2	175		T18	2
valid_sources[0x77]	5831	1			T1	2		T2	204		T19	1
valid_sources[0x78]	5346	1			T1	1		T2	180		T3	3
valid_sources[0x79]	6063	1			T1	1		T2	190		T18	4
valid_sources[0x7a]	5380	1			T1	4		T2	195		T18	4
valid_sources[0x7b]	5674	1			T7	1		T1	4		T2	177
valid_sources[0x7c]	5461	1			T1	1		T2	178		T29	12
valid_sources[0x7d]	5244	1			T1	4		T2	194		T19	1
valid_sources[0x7e]	5787	1			T2	206		T29	3		T3	8
valid_sources[0x7f]	5922	1			T1	1		T2	171		T18	3
valid_sources[0x80]	6065	1			T1	3		T17	1		T2	200

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

308379

1

T5

7

T6

3

T7

16

values[0x0]

all_enables

biggest_size

455199

1

T5

105

T6

1

T7

5

values[0x1]

all_enables

biggest_size

431528

1

T5

64

T6

1

T7

1