Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T2,T18
0	1	Covered	T2,T20,T29
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T18
1	0	Covered	T35,T36,T37
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	437025223	7545	0	0
GateOpen_A	437025223	13777	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437025223	7545	0	0
T2	2504795	166	0	0
T3	0	55	0	0
T18	5241	4	0	0
T19	149192	0	0	0
T20	3456	33	0	0
T21	4247	0	0	0
T22	3504	0	0	0
T23	232735	0	0	0
T27	47920	0	0	0
T28	4458	0	0	0
T29	537885	42	0	0
T35	0	5	0	0
T87	0	4	0	0
T88	0	4	0	0
T186	0	30	0	0
T189	0	15	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437025223	13777	0	0
T1	406911	0	0	0
T2	2504795	176	0	0
T4	134876	40	0	0
T6	11686	4	0	0
T7	4532	4	0	0
T16	9684	0	0	0
T17	3727	0	0	0
T18	5241	4	0	0
T19	149192	4	0	0
T20	3456	33	0	0
T21	0	4	0	0
T22	0	4	0	0
T27	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T2,T18
0	1	Covered	T2,T20,T29
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T18
1	0	Covered	T35,T36,T37
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	47992245	1810	0	0
GateOpen_A	47992245	3366	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47992245	1810	0	0
T2	458856	39	0	0
T3	0	14	0	0
T18	565	1	0	0
T19	16571	0	0	0
T20	369	4	0	0
T21	456	0	0	0
T22	374	0	0	0
T23	16415	0	0	0
T27	6001	0	0	0
T28	706	0	0	0
T29	58736	9	0	0
T35	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T186	0	7	0	0
T189	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47992245	3366	0	0
T1	45201	0	0	0
T2	458856	41	0	0
T4	10338	10	0	0
T6	1329	1	0	0
T7	488	1	0	0
T16	1061	0	0	0
T17	410	0	0	0
T18	565	1	0	0
T19	16571	1	0	0
T20	369	4	0	0
T21	0	1	0	0
T22	0	1	0	0
T27	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T2,T18
0	1	Covered	T2,T20,T29
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T18
1	0	Covered	T35,T36,T37
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	95984895	1917	0	0
GateOpen_A	95984895	3473	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95984895	1917	0	0
T2	917716	44	0	0
T3	0	13	0	0
T18	1129	1	0	0
T19	33141	0	0	0
T20	737	10	0	0
T21	911	0	0	0
T22	749	0	0	0
T23	32830	0	0	0
T27	12003	0	0	0
T28	1412	0	0	0
T29	117476	10	0	0
T35	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T186	0	8	0	0
T189	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95984895	3473	0	0
T1	90402	0	0	0
T2	917716	46	0	0
T4	20675	10	0	0
T6	2659	1	0	0
T7	976	1	0	0
T16	2121	0	0	0
T17	820	0	0	0
T18	1129	1	0	0
T19	33141	1	0	0
T20	737	10	0	0
T21	0	1	0	0
T22	0	1	0	0
T27	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T2,T18
0	1	Covered	T2,T20,T29
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T18
1	0	Covered	T35,T36,T37
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	193520106	1918	0	0
GateOpen_A	193520106	3478	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193520106	1918	0	0
T2	183878	42	0	0
T3	0	14	0	0
T18	2365	1	0	0
T19	66319	0	0	0
T20	1567	9	0	0
T21	1920	0	0	0
T22	1587	0	0	0
T23	122325	0	0	0
T27	19944	0	0	0
T28	1560	0	0	0
T29	233432	11	0	0
T35	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T186	0	7	0	0
T189	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193520106	3478	0	0
T1	180869	0	0	0
T2	183878	45	0	0
T4	69241	10	0	0
T6	5132	1	0	0
T7	2045	1	0	0
T16	4335	0	0	0
T17	1665	0	0	0
T18	2365	1	0	0
T19	66319	1	0	0
T20	1567	9	0	0
T21	0	1	0	0
T22	0	1	0	0
T27	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T2,T18
0	1	Covered	T2,T20,T29
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T18
1	0	Covered	T35,T36,T37
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	99527977	1900	0	0
GateOpen_A	99527977	3460	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99527977	1900	0	0
T2	944345	41	0	0
T3	0	14	0	0
T18	1182	1	0	0
T19	33161	0	0	0
T20	783	10	0	0
T21	960	0	0	0
T22	794	0	0	0
T23	61165	0	0	0
T27	9972	0	0	0
T28	780	0	0	0
T29	128241	12	0	0
T35	0	2	0	0
T87	0	1	0	0
T88	0	1	0	0
T186	0	8	0	0
T189	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99527977	3460	0	0
T1	90439	0	0	0
T2	944345	44	0	0
T4	34622	10	0	0
T6	2566	1	0	0
T7	1023	1	0	0
T16	2167	0	0	0
T17	832	0	0	0
T18	1182	1	0	0
T19	33161	1	0	0
T20	783	10	0	0
T21	0	1	0	0
T22	0	1	0	0
T27	0	1	0	0