Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	331497490	30228	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331497490	30228	0	0
T1	433350	332	0	0
T2	943070	840	0	0
T3	0	57	0	0
T4	346200	0	0	0
T9	0	134	0	0
T10	0	504	0	0
T11	0	344	0	0
T12	0	96	0	0
T13	0	993	0	0
T14	0	45	0	0
T15	0	176	0	0
T16	5640	0	0	0
T17	8320	0	0	0
T18	11820	0	0	0
T19	169260	0	0	0
T20	8080	0	0	0
T21	9500	0	0	0
T22	7855	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	66299498	4448	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	66299498	4448	0	0
T1	86670	52	0	0
T2	188614	109	0	0
T3	0	9	0	0
T4	69240	0	0	0
T9	0	19	0	0
T10	0	73	0	0
T11	0	45	0	0
T12	0	15	0	0
T13	0	131	0	0
T14	0	7	0	0
T15	0	26	0	0
T16	1128	0	0	0
T17	1664	0	0	0
T18	2364	0	0	0
T19	33852	0	0	0
T20	1616	0	0	0
T21	1900	0	0	0
T22	1571	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	66299498	4377	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	66299498	4377	0	0
T1	86670	49	0	0
T2	188614	109	0	0
T3	0	9	0	0
T4	69240	0	0	0
T9	0	19	0	0
T10	0	63	0	0
T11	0	44	0	0
T12	0	15	0	0
T13	0	129	0	0
T14	0	7	0	0
T15	0	21	0	0
T16	1128	0	0	0
T17	1664	0	0	0
T18	2364	0	0	0
T19	33852	0	0	0
T20	1616	0	0	0
T21	1900	0	0	0
T22	1571	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	66299498	6049	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	66299498	6049	0	0
T1	86670	65	0	0
T2	188614	169	0	0
T3	0	11	0	0
T4	69240	0	0	0
T9	0	30	0	0
T10	0	99	0	0
T11	0	70	0	0
T12	0	19	0	0
T13	0	199	0	0
T14	0	9	0	0
T15	0	35	0	0
T16	1128	0	0	0
T17	1664	0	0	0
T18	2364	0	0	0
T19	33852	0	0	0
T20	1616	0	0	0
T21	1900	0	0	0
T22	1571	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	66299498	6066	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	66299498	6066	0	0
T1	86670	67	0	0
T2	188614	173	0	0
T3	0	11	0	0
T4	69240	0	0	0
T9	0	26	0	0
T10	0	101	0	0
T11	0	71	0	0
T12	0	19	0	0
T13	0	200	0	0
T14	0	9	0	0
T15	0	37	0	0
T16	1128	0	0	0
T17	1664	0	0	0
T18	2364	0	0	0
T19	33852	0	0	0
T20	1616	0	0	0
T21	1900	0	0	0
T22	1571	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	66299498	9288	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	66299498	9288	0	0
T1	86670	99	0	0
T2	188614	280	0	0
T3	0	17	0	0
T4	69240	0	0	0
T9	0	40	0	0
T10	0	168	0	0
T11	0	114	0	0
T12	0	28	0	0
T13	0	334	0	0
T14	0	13	0	0
T15	0	57	0	0
T16	1128	0	0	0
T17	1664	0	0	0
T18	2364	0	0	0
T19	33852	0	0	0
T20	1616	0	0	0
T21	1900	0	0	0
T22	1571	0	0	0