Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T4,T2,T29

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	66299498	63999175	0	0
AllClkBypReqTrue_A	66299498	72690	0	0
IoClkBypReqFalse_A	66299498	63948476	0	2319
IoClkBypReqTrue_A	66299498	119171	0	0
LcClkBypAckFalse_A	66299498	64004214	0	0
LcClkBypAckTrue_A	66299498	67651	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	66299498	63999175	0	0
T1	86670	86624	0	0
T2	188614	187429	0	0
T4	69240	3317	0	0
T5	181840	181585	0	0
T6	1336	1262	0	0
T7	2129	1931	0	0
T16	1128	1096	0	0
T17	1664	1597	0	0
T18	2364	2228	0	0
T19	33852	33782	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	66299498	72690	0	0
T1	86670	0	0	0
T2	188614	188	0	0
T3	0	168	0	0
T4	69240	0	0	0
T6	1336	34	0	0
T7	2129	0	0	0
T16	1128	0	0	0
T17	1664	0	0	0
T18	2364	0	0	0
T19	33852	0	0	0
T20	1616	0	0	0
T21	0	94	0	0
T27	0	183	0	0
T28	0	12	0	0
T29	0	387	0	0
T83	0	260	0	0
T84	0	77	0	0
T86	0	10	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	66299498	63948476	0	2319
T1	86670	86622	0	3
T2	188614	187360	0	3
T4	69240	3295	0	3
T5	181840	181583	0	3
T6	1336	1195	0	3
T7	2129	1929	0	3
T16	1128	1094	0	3
T17	1664	1595	0	3
T18	2364	2226	0	3
T19	33852	33780	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	66299498	119171	0	0
T1	86670	0	0	0
T2	188614	861	0	0
T3	0	442	0	0
T4	69240	0	0	0
T6	1336	99	0	0
T7	2129	0	0	0
T16	1128	0	0	0
T17	1664	0	0	0
T18	2364	0	0	0
T19	33852	0	0	0
T20	1616	0	0	0
T21	0	48	0	0
T22	0	45	0	0
T27	0	406	0	0
T29	0	539	0	0
T83	0	438	0	0
T84	0	93	0	0
T86	0	103	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	66299498	64004214	0	0
T1	86670	86624	0	0
T2	188614	187400	0	0
T4	69240	3317	0	0
T5	181840	181585	0	0
T6	1336	1240	0	0
T7	2129	1931	0	0
T16	1128	1096	0	0
T17	1664	1597	0	0
T18	2364	2228	0	0
T19	33852	33782	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	66299498	67651	0	0
T1	86670	0	0	0
T2	188614	476	0	0
T3	0	218	0	0
T4	69240	0	0	0
T6	1336	56	0	0
T7	2129	0	0	0
T16	1128	0	0	0
T17	1664	0	0	0
T18	2364	0	0	0
T19	33852	0	0	0
T20	1616	0	0	0
T22	0	41	0	0
T27	0	316	0	0
T29	0	351	0	0
T83	0	200	0	0
T84	0	52	0	0
T86	0	53	0	0
T89	0	42	0	0