Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	828743080	7193	0	0
TransStop_A	828743080	3809	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	828743080	7193	0	0
T1	753644	0	0	0
T2	782140	88	0	0
T3	0	8	0	0
T4	288516	0	0	0
T7	8520	11	0	0
T16	18064	0	0	0
T17	6940	7	0	0
T18	9856	4	0	0
T19	276340	0	0	0
T20	6532	0	0	0
T21	7996	0	0	0
T29	0	101	0	0
T85	0	38	0	0
T87	0	4	0	0
T116	0	31	0	0
T117	0	15	0	0
T118	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	828743080	3809	0	0
T1	753644	0	0	0
T2	782140	57	0	0
T3	0	8	0	0
T4	288516	0	0	0
T7	8520	8	0	0
T16	18064	0	0	0
T17	6940	1	0	0
T18	9856	4	0	0
T19	276340	0	0	0
T20	6532	0	0	0
T21	7996	0	0	0
T29	0	64	0	0
T85	0	13	0	0
T87	0	4	0	0
T116	0	12	0	0
T117	0	9	0	0
T118	0	3	0	0
T119	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	207185770	1797	0	0
TransStop_A	207185770	950	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207185770	1797	0	0
T1	188411	0	0	0
T2	195535	17	0	0
T3	0	2	0	0
T4	72129	0	0	0
T7	2130	2	0	0
T16	4516	0	0	0
T17	1735	2	0	0
T18	2464	1	0	0
T19	69085	0	0	0
T20	1633	0	0	0
T21	1999	0	0	0
T29	0	25	0	0
T85	0	10	0	0
T87	0	1	0	0
T116	0	8	0	0
T117	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207185770	950	0	0
T1	188411	0	0	0
T2	195535	13	0	0
T3	0	2	0	0
T4	72129	0	0	0
T7	2130	2	0	0
T16	4516	0	0	0
T17	1735	0	0	0
T18	2464	1	0	0
T19	69085	0	0	0
T20	1633	0	0	0
T21	1999	0	0	0
T29	0	13	0	0
T85	0	4	0	0
T87	0	1	0	0
T116	0	4	0	0
T117	0	1	0	0
T119	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	207185770	1800	0	0
TransStop_A	207185770	948	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207185770	1800	0	0
T1	188411	0	0	0
T2	195535	20	0	0
T3	0	2	0	0
T4	72129	0	0	0
T7	2130	4	0	0
T16	4516	0	0	0
T17	1735	3	0	0
T18	2464	1	0	0
T19	69085	0	0	0
T20	1633	0	0	0
T21	1999	0	0	0
T29	0	26	0	0
T85	0	10	0	0
T87	0	1	0	0
T116	0	11	0	0
T117	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207185770	948	0	0
T1	188411	0	0	0
T2	195535	12	0	0
T3	0	2	0	0
T4	72129	0	0	0
T7	2130	2	0	0
T16	4516	0	0	0
T17	1735	1	0	0
T18	2464	1	0	0
T19	69085	0	0	0
T20	1633	0	0	0
T21	1999	0	0	0
T29	0	16	0	0
T85	0	3	0	0
T87	0	1	0	0
T116	0	3	0	0
T117	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	207185770	1794	0	0
TransStop_A	207185770	960	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207185770	1794	0	0
T1	188411	0	0	0
T2	195535	26	0	0
T3	0	2	0	0
T4	72129	0	0	0
T7	2130	2	0	0
T16	4516	0	0	0
T17	1735	2	0	0
T18	2464	1	0	0
T19	69085	0	0	0
T20	1633	0	0	0
T21	1999	0	0	0
T29	0	21	0	0
T85	0	8	0	0
T87	0	1	0	0
T116	0	7	0	0
T117	0	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207185770	960	0	0
T1	188411	0	0	0
T2	195535	16	0	0
T3	0	2	0	0
T4	72129	0	0	0
T7	2130	1	0	0
T16	4516	0	0	0
T17	1735	0	0	0
T18	2464	1	0	0
T19	69085	0	0	0
T20	1633	0	0	0
T21	1999	0	0	0
T29	0	15	0	0
T85	0	2	0	0
T87	0	1	0	0
T116	0	3	0	0
T117	0	3	0	0
T118	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	207185770	1802	0	0
TransStop_A	207185770	951	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207185770	1802	0	0
T1	188411	0	0	0
T2	195535	25	0	0
T3	0	2	0	0
T4	72129	0	0	0
T7	2130	3	0	0
T16	4516	0	0	0
T17	1735	0	0	0
T18	2464	1	0	0
T19	69085	0	0	0
T20	1633	0	0	0
T21	1999	0	0	0
T29	0	29	0	0
T85	0	10	0	0
T87	0	1	0	0
T116	0	5	0	0
T117	0	4	0	0
T118	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207185770	951	0	0
T1	188411	0	0	0
T2	195535	16	0	0
T3	0	2	0	0
T4	72129	0	0	0
T7	2130	3	0	0
T16	4516	0	0	0
T17	1735	0	0	0
T18	2464	1	0	0
T19	69085	0	0	0
T20	1633	0	0	0
T21	1999	0	0	0
T29	0	20	0	0
T85	0	4	0	0
T87	0	1	0	0
T116	0	2	0	0
T117	0	3	0	0
T118	0	1	0	0